CN102521460B - Filling method for matted metal - Google Patents
Filling method for matted metal Download PDFInfo
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- CN102521460B CN102521460B CN201110427611.0A CN201110427611A CN102521460B CN 102521460 B CN102521460 B CN 102521460B CN 201110427611 A CN201110427611 A CN 201110427611A CN 102521460 B CN102521460 B CN 102521460B
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Abstract
The invention discloses a filling method for matted metal. The filling method for matted metal includes lithographic simulation, extraction of circuit network lists, simulation of a circuit, delay limit of nodes of the circuit, computation of equivalent electric parameters under lithographic distortion condition, computation of parasitic capacitance limit, and filling of the matted metal under constraint conditions, so that filling of the matted metal with lithographic distortion is realized, influence of lithographic distortion on parasitic resistance and parasitic capacitance is taken into consideration in a parasitism estimation and redundant matted metal filling process, influence of changes of the parasitic resistance and the parasitic capacitance due to filling of redundant matted metal on designed performances of a circuit is controlled within a specified range, flatness of metal interconnection lines of various parts of the circuit is improved to the greatest extent, and accordingly manufacturability of a design of the integrated circuit is improved.
Description
Technical field
The present invention relates to a kind of mute metal filled method, particularly a kind of mute metal filled method for photoetching distortion.
Background technology
Chemically mechanical polishing is the important step of integrated circuit fabrication process flow process, and after integrated circuit fabrication process enters 65-45nm process node, interconnection line has become the deciding factor affecting chip performance and reliability.Due to the difference of the hardness of metal and insulating medium, chemically mechanical polishing can cause the thickness deviation of copper interconnecting line and dielectric layer, and these deviations bring negative effect can to the electrical parameter of interconnection line, and then has influence on the Performance And Reliability of chip.Mute metal filled for reducing the redundancy that the chip surface thickness fluctuation after chemically mechanical polishing carries out.
Redundancy is mute metal filled, can cause the growth of interconnect capacitance on the one hand and bring negative effect to the electrical characteristics of chip, and this has in the mute metal fill process of existing redundancy considered; The reason redundancy distorted due to dark nanoscale lithography is on the other hand mute metal filledly may cause distortion to cause interconnection line metallic pattern local narrow or broaden to the figure of existing metal interconnecting wires, the dead resistance that interconnection line is caused becomes large or diminishes, actual stray capacitance between filling metal and interconnection line metallic pattern is bigger than normal or less than normal than the stray capacitance of desirable estimation because there is certain difference between metallic pattern between actual range and ideal distance, the difference that the difference that the change of this dead resistance and electric capacity are estimated can cause circuit performance to estimate.
Summary of the invention
For solving the above-mentioned problems in the prior art, the invention provides and a kind ofly optimize the fill method of filling redundancy mute metal, solving the distort metal interconnecting wires dead resistance that causes and parasitic capacitor variations of photoetching in existing fill method affects the problem of circuit performance.
Concrete technical scheme is realized by following steps:
A kind of mute metal filled method, comprises the steps:
A lithography simulation semiconductor physical layout, obtains the semiconductor physics layout data distorted;
The semiconductor physics layout data of B to described distortion carries out parasitic parameter extraction, obtains the circuit meshwork list comprising spurious element device;
C carries out transient analysis by the circuit of circuit simulation to the semiconductor physics domain of described distortion, obtains transient analysis result;
E according to the latency limit of described circuit node and equivalent electrical information, introduce redundancy mute metal filled give described distortion physical layout gauze after, calculate described circuit node carrying limit stray capacitance;
F is the upper limit with described circuit node limit stray capacitance, repeatedly adjusts mute metal filled method, optimizes the mechanical planarization degree of the chip of semiconductor physics domain.
Preferably, the latency limit of circuit node described in step D calculates according to such as formula (1):
Tdealylimit，n ＝k/fclk；
Wherein, Tdealylimit, n are the latency limit on the gauze n of the physical layout of described distortion; Fclk is the clock signal frequency of gauze n direct correlation; K is constant, and its span is generally between [0.01,0.10].
Preferably, described equivalent electrical information comprises circuit node equivalent parasitic capacitances and circuit node equivalence conducting resistance.
Preferably, the existing stray capacitance sum that described circuit node equivalent parasitic capacitances is institute's wired network, the device namely comprising described gauze is connected to the stray capacitance between the stray capacitance of described gauze and described gauze interconnection line.
Preferably, the stray capacitance that the device of described gauze n is connected to described gauze calculates according to such as formula (2) Suo Shi;
Cnet.n，exist，dev＝∑Cnet.n，exist，dev，i
(2)
Wherein,
i＝1，2，3，…，Nnet，n，dev_cnum；
Nnet, n, dev_cnum are the stray capacitance quantity that on gauze n, device causes;
Cnet.n, exist, dev are the stray capacitance that the device of described gauze n is connected to described gauze.
Preferably, the stray capacitance between the mutual interconnection line of described gauze calculates and calculates according to such as formula (3) Suo Shi;
Cnet.n，exist，wire＝∑Cnet.n，exist，wire，i
(3)
Wherein,
i＝1，2，3，…，Nnet，n，wire_cnum；
Nnet, n, wire_cnum are the stray capacitance quantity that on described gauze n, interconnection line causes;
Cnet.n, exist, wir are the stray capacitance between described gauze n interconnection line.
Preferably, the computing method of described circuit node equivalence conducting resistance comprise the steps:
A calculate power supply to described gauze corresponding node between to power supply equivalent resistance;
B calculate ground wire to gauze corresponding node between equivalent resistance over the ground;
C is described in power supply equivalent resistance and described equivalent resistance over the ground, and choosing maximal value is described circuit node equivalence conducting resistance.
Preferably, described gauze limit stray capacitance is by calculating as shown in the formula (4):
Cnet，n，extra_limit＝Tdealylimit，n/Ron-Cnet.n，exist
Wherein,
Tdealylimit, n are the latency limit of gauze n;
Ron is described gauze equivalence conducting resistance;
Cnet.n, exist are the equivalent parasitic capacitances of gauze n;
Cnet, n, extra_limit are the mute metal filled limit stray capacitance introduced to gauze n of redundancy.
The present invention passes through lithography simulation, circuit meshwork list extracts, circuit simulation, circuit node latency limit, under photoetching distortion situation, equivalent electrical parameter calculates, limit stray capacitance calculates, mute metal filled achieving under constraint condition considers the mute metal filled of photoetching distortion, the impact that photoetching distorts on dead resistance and stray capacitance is considered in parasitism estimation and the mute metal fill process of redundancy, guarantee the mute metal filled dead resistance that causes of redundancy and parasitic capacitor variations to the impact of circuit design performance within preset range, improve the flatness of circuit portions metal interconnecting wires substantially, thus improve the manufacturability of integrated circuit (IC) design.
Accompanying drawing explanation
Fig. 1 is a kind of mute metal filled method flow diagram based on the circuit delay limit that the embodiment of the present invention provides;
Fig. 2 is the latency limit according to circuit node that provides of the embodiment of the present invention and equivalent electrical information, determines to introduce redundancy mute metal filled to after gauze, the process flow diagram of the limit stray capacitance of each circuit node carrying;
Fig. 3 is the existing equivalent parasitic capacitances process flow diagram of counting circuit node that the embodiment of the present invention provides;
Fig. 4 is the counting circuit node equivalent conducting resistance process flow diagram that the embodiment of the present invention provides;
Fig. 5 be the embodiment of the present invention provide optimize and revise mute metal filled method flow diagram.
Embodiment
Below in conjunction with embodiment, the present invention is further described in detail, the embodiment provided only in order to illustrate the present invention, instead of in order to limit the scope of the invention.
Below in conjunction with drawings and Examples, the present invention is described in detail below:
See Fig. 1, embodiments provide a kind of mute metal filled method based on the circuit delay limit, details are as follows:
Step S101 carries out the physical layout data distorted after lithography simulation obtains actual photoetching to physical layout;
The physical layout that step S102 distorts from photoetching extracts the circuit meshwork list comprising spurious element device;
Step S103 carries out transient analysis by circuit simulation to circuit under existing physical layout design;
Step S104 analyzes the equivalent electrical information of latency limit and the circuit node determining each circuit node to transient analysis result;
Step S105 determines according to the equivalent electrical information of the latency limit of each circuit node and circuit node the mute metal filled limit stray capacitance introduced to gauze of redundancy that each circuit node can carry;
Step S106 using the additional parasitic electric capacity that can carry for the upper limit as constraint condition, based on lithography simulation result, estimate stray capacitance, optimize and fill mute metal and guarantee the planarization of chemically mechanical polishing.
In the embodiment of the present invention, step S101 carries out the physical layout data distorted after lithography simulation obtains actual photoetching to physical layout: in dark nanometer-grade IC manufacture process, the optical wavelength of litho machine is far smaller than the feature process size of integrated circuit, the effect of interference and diffraction between light beam, there is certain difference in the desired metallic interconnection line figure of the actual metal interconnection line figure after causing photoetching and the physical layout design of integrated circuit, the metal interconnecting wires ghost effect that parasitic parameter can not react actual integrated circuit is extracted with original desirable layout data, in order to accurately react the metal interconnecting wires ghost effect of actual integrated circuit, lithography simulation must be carried out to desirable physical layout data, obtain the physical layout data after photoetching distortion, and then parasitic parameter extraction is carried out to these data.Lithography simulation by business software instrument, as the SOLID-C of PROLITH and the Sigma-C company of KLA-Tencor company, or can adopt inner photoetching emulation tool.
In the embodiment of the present invention, step S102 extracts the circuit meshwork list containing spurious element device from the physical layout that photoetching distorts: comprise the execution script automatically extracting the circuit meshwork list containing spurious element device from physical layout in the Process design kit (Process Design Kit, PDK) that Integrated circuit manufacturers is externally issued.Run business-like parasitic parameter extraction software, as the CALIBRE of STAR-RCX, MENTOR company and the Related product of other companies of ASSURA, SYNOPSYS company of CADENCE company, certainly also endophyte parameter extraction software can be run, perform corresponding script command, finally extract the circuit meshwork list containing spurious element device.Input data are the physical layout data that pass gram emulation obtains, and export the circuit meshwork list that data are SPICE form, CDL form or SPEF form.
In the embodiment of the present invention, the emulation of step S103 oversampling circuit carries out transient analysis to the circuit under existing physical layout design: transient analysis is one of basic function of integrated circuit emulation tool, the input data of transient analysis comprise containing spurious element device circuit meshwork list, test and excitation and run, measure and export control command.Circuit meshwork list containing spurious element device carries out calculating by parasitic parameter extraction software in previous step to physical layout data and produced; Test and excitation is provided by designer; Run, measure and export control command to be set by edit tool or graphic interface tool by designer, also can be analyzed by the circuit meshwork list of program to input and automatically generate, the generation of the measurement that particularly circuit meshwork list node is relevant and output control command.Transient analysis by running commercial circuit emulation tool, as SPECTRE and ULTRA-SIM of CADENCE, HSPICE and HSIM of SYNOPSYS, can realize; Also can realize by running internal circuit analysis tool.Transient analysis is activated by the operation control command of above-mentioned emulation tool, carry out among process in transient analysis, according to measurement control order and output control command, the electrical variable value to specified node carries out operation result of measurement, and output information carries out computation and analysis for subsequent step on request.
See Fig. 2, in the embodiment of the present invention, step S104 to transient analysis result analyze determine each circuit node latency limit, the equivalent electrical information of circuit node comprises under photoetching distortion situation
Step S10401 circuit node latency limit calculates;
The existing equivalent parasitic capacitances of step S10402 circuit node calculates;
Step S10403 circuit node equivalence conducting resistance calculates.
Latency limit computing formula following Tdealylimit, the n=k/fclk of step S10401 circuit node,
Wherein, Tdealylimit, n are the signal lag limit on gauze n;
Fclk is the clock signal frequency of gauze n direct correlation;
K is constant, and its span is generally between [0.01,0.10].
Calculating for the clock signal frequency fclk of gauze n direct correlation: if this gauze is clock signal gauze, then fclk is the online signal frequency of this clock cable, otherwise with this node for starting point, logical reach is in the scope of 1, find clock signal, the highest its frequency of clock signal of selecting frequency is as fclk; If the clock signal of not finding, with this node for starting point, distance is in the scope of 2, finds clock signal, and the highest its frequency of clock signal of selecting frequency is as fclk; If the clock signal of not finding, with this node for starting point, distance is in the scope of 3, finds clock signal, and the highest its frequency of clock signal of selecting frequency is as fclk; By that analogy, until find clock signal.
The equivalent electrical information spinner of circuit node will comprise this circuit node stray capacitance Cnet, n, extra_limit and be this circuit node stray capacitance Cnet, the conducting resistance Ron of n, extra_limit discharge and recharge.
See Fig. 3, in the embodiment of the present invention, the existing equivalent parasitic capacitances of step S10402 circuit node calculates and comprises:
The device itself that step S1030401 is connected to this gauze n is connected to the calculating of the stray capacitance of this gauze;
Stray capacitance between step S1030402 other gauze interconnection line and interconnection lines of gauze n calculates;
The existing equivalent parasitic capacitances of step S1040203 circuit node calculates.
The existing stray capacitance Cnet.n of gauze n, exist is the existing stray capacitance sum of this gauze, comprise the stray capacitance Cnet.n that the device itself being connected to this gauze n is connected to this gauze, exist, dev, stray capacitance Cnet.n between other gauze interconnection line and interconnection lines of gauze n, exist, wire.
The device itself that step S1040201 is connected to this gauze n is connected to the stray capacitance Cnet.n of this gauze, the calculating of exist, dev: read in circuit meshwork list that parasitic parameter extraction obtains, that comprise spurious element device; The device that traversal gauze n connects; The stray capacitance that these devices are connected with this gauze is obtained from circuit simulation output file; They are sued for peace, can Cnet.n be obtained, exist, dev:
Cnet.n，exist，dev＝∑Cnet.n，exist，dev，i
Wherein,
i＝1，2，3，…，Nnet，n，dev_cnum；
Nnet, n, dev_cnum are the stray capacitance quantity that on gauze n, device causes.
Stray capacitance Cnet.n between step S1040202 other gauze interconnection line and interconnection lines of gauze n, the calculating of exist, wire: read in circuit meshwork list that parasitic parameter extraction obtains, that comprise spurious element device; The stray capacitance that on traversal gauze n, interconnection line causes; They are sued for peace, can Cnet.n be obtained, exist, wire:
Cnet.n，exist，wire＝∑Cnet.n，exist，wire，i
Wherein,
i＝1，2，3，…，Nnet，n，wire_cnum；
Nnet, n, wire_cnum are the stray capacitance quantity that on gauze n, interconnection line causes.
The existing equivalent parasitic capacitances of step S1030203 circuit node calculates the calculating of Cnet.n, exist: sue for peace to Cnet.n, exist, dev and Cnet.n, exist, wire, can obtain Cnet.n, exist:
Cnet.n，exist＝Cnet.n，exist，dev+Cnet.n，exist，wire
See Fig. 4, in the embodiment of the present invention, step S10303 circuit node equivalence conducting resistance calculates: be this circuit node stray capacitance Cnet, the calculating of the conducting resistance Ron of n, extra_limit discharge and recharge comprises:
Step S1040301 calculate power supply to gauze n corresponding node between to power supply equivalent resistance Rp_on;
Step S1040302 calculate calculate ground to gauze n corresponding node between to power supply equivalent resistance Rn_on;
Step S1040303 is this circuit node stray capacitance Cnet, the conducting resistance Ron of n, extra_limit discharge and recharge.
Step S1040301 calculate power supply to gauze n corresponding node between to power supply equivalent resistance Rp_on: using the corresponding node of gauze n as starting point, search out the DC channel of power supply; To calculate equivalent conducting conductance gp_on, i or conducting resistance rpon, the i of each conduction device to the bias condition of the device in the DC channel of power supply and conducting state thereof; Annexation according to these conduction devices and associated interconnect line dead resistance sets up the connection in series-parallel annexation of these conducting resistance and associated interconnect line dead resistance; According to the connection in series-parallel annexation of these equivalent conducting resistance rp_on, i and associated interconnect line dead resistance calculate power supply to gauze n corresponding node between to power supply equivalent resistance Rp_on;
Step S1040302 calculate calculate ground to gauze n corresponding node between to power supply equivalent resistance Rn_on: using the corresponding node of gauze n as starting point, search out ground DC channel; To calculate equivalent conducting conductance gn_on, i or conducting resistance rnon, the i of each conduction device to the bias condition of the device in the DC channel on ground and conducting state thereof; Annexation according to these conduction devices and associated interconnect line dead resistance sets up the connection in series-parallel annexation of these conducting resistance and associated interconnect line dead resistance; According to the connection in series-parallel annexation of these equivalent conducting resistance rn_on, i and associated interconnect line dead resistance calculate power supply to gauze n corresponding node between the Rn_on of equivalent resistance over the ground;
Step S1040303 is this circuit node stray capacitance Cnet, n, the conducting resistance Ron of extra_limit discharge and recharge: to power supply equivalent resistance Rp_on and choose equivalent resistance Rn_on over the ground resistance larger as gauze n circuit node stray capacitance Cnet, n, the conducting resistance Ron of extra_limit discharge and recharge, i.e. Ron=max (Rp_on, Rp_on).
In the embodiment of the present invention, step S105 determines according to the latency limit of each circuit node, the Guan Ke equivalent electrical information of circuit node under situation that distorts the mute metal filled limit stray capacitance introduced to gauze of redundancy that each circuit node can carry: the latency limit computing formula of gauze n is as follows
Tdealylimit，n＝Ron*(Cnet.n，exist+Cnet，n，extra_limit)
Wherein,
Tdealylimit, n are the latency limit of gauze n;
Conducting resistance when Ron is gauze discharge and recharge;
Cnet.n, exist are the existing stray capacitance of gauze n;
Cnet, n, extra_limit are the mute metal filled limit stray capacitance introduced to gauze n of redundancy.
The mute metal filled limit stray capacitance computing formula introduced to gauze n of redundancy is obtained to the conversion of this computing formula
Cnet，n，extra limit＝Tdealylimit，n/Ron-Cnet.n，exist
Wherein,
The latency limit Tdealylimit of gauze n, n is calculated by previous step;
Conducting resistance Ron_limit during gauze discharge and recharge is calculated by previous step;
Existing stray capacitance Cnet.n, the exist of gauze n are the existing stray capacitance sum of this gauze, comprise the device itself being connected to this gauze n and are connected to the stray capacitance of this gauze, the stray capacitance between other gauze interconnection line and interconnection lines of gauze n.
See Fig. 5, in embodiments of the present invention, step S106 using the extra limit stray capacitance that can carry for the upper limit as constraint condition, estimate based on lithography simulation stray capacitance, optimize fill mute metal guarantee that the planarization of chemically mechanical polishing comprises:
It is mute metal filled that step S10601 produces the redundancy of attempting;
Step S10602 lithography simulation;
Step S10603 parasitic parameter extraction;
The mute metal filled stray capacitance caused of step S10604 estimation circuit Nodes redundancy;
Step S10605 checks that Current redundant is mute and metal filledly whether meets constraint condition, if satisfy condition, then carries out next step, otherwise performs step S10601;
Step S10606 calculating target function, determine whether to select current filling and be left best to fill record according to optimized algorithm, repeat step step S10601 to step S10606, in optimized algorithm, cycling condition meets, constantly the mute metal filled target function value that makes of adjustment redundancy constantly reduces, until exit circulation when the cycling condition met in optimized algorithm does not meet, perform next step;
Step S10607 terminates to fill optimizing process.
In the mute metal process of filling, the additional parasitic capacitance pole limit value that previous step calculates can not be exceeded to the stray capacitance summation of each gauze, adjust the metal height standard deviation after pattern filling makes chemically mechanical polishing with this understanding, its mathematical description is as follows
Constraint condition: C net, n≤Cnet, n, extra_limit n=1,2 ..., Nnets
Objective function: f=min{SQRT [∑ (Hi-Hmean) 2/Nnet_wire] }
i＝1，2，...，Nnet_wire
Wherein
C net, n are that the n-th gauze is because of the stray capacitance that it is upper and lower, left and right is filled metal and introduced;
Cnet, n, extra_limit are the ultimate value of the n-th gauze because of the stray capacitance that it is upper and lower, left and right is filled metal and introduced;
Nnets is line screen;
Nnet_wire is gauze metal connecting line hop count.
Hmean is the average height of gauze metal connecting line, Hmean=∑ Hi i=1,2 ..., Nnet_wire.
Its calculation expression of C net, n is
C net，n＝∑C net，n，i
Wherein,
i＝1，2，...，Nnet，n，fc_num；
Nnet, n, fc_numw are the mute metal filled stray capacitance quantity caused to gauze n of corresponding redundancy;
C net, n, i are that redundancy is mute metal filled to i-th dead resistance causing of gauze n, this stray capacitance be corresponding redundancy mute metal filled after carry out lithography simulation and carry out the stray capacitance that parasitic parameter extraction obtains again.
For the optimization problem under constraint condition, existing simulated annealing, genetic algorithm, particle cluster algorithm all can the realizations of control and optimize process, and specific implementation with reference to the corresponding reference of these algorithms, can not be described in detail at this.
The above is only preferred embodiment of the present invention, therefore all equivalences done according to structure, feature and the principle described in patent claim of the present invention change or modify, and are included in patent claim of the present invention.
Claims (2)
1. a mute metal filled method, is characterized in that, comprise the steps:
A lithography simulation semiconductor physical layout, obtains the semiconductor physics layout data distorted;
The semiconductor physics layout data of B to described distortion carries out parasitic parameter extraction, obtains the circuit meshwork list comprising spurious element device;
C carries out transient analysis by the circuit of circuit simulation to the semiconductor physics domain of described distortion, obtains transient analysis result;
D calculates described transient analysis result, determines latency limit and the equivalent electrical information of circuit node in the circuit of the semiconductor physics domain of described distortion;
E according to the latency limit of described circuit node and equivalent electrical information, introduce redundancy mute metal filled give described distortion physical layout gauze after, calculate described circuit node carrying limit stray capacitance;
F is the upper limit with described circuit node limit stray capacitance, repeatedly adjusts mute metal filled method, optimizes the mechanical planarization degree of the chip of semiconductor physics domain;
Wherein, the latency limit of circuit node described in step D calculates according to such as formula (1):
Tdealylimit,n＝k/fclk；
(1)
Wherein, Tdealylimit, n are the latency limit of the circuit node on the gauze n of the physical layout of described distortion; Fclk is the clock signal frequency of described gauze n direct correlation; K is constant;
Wherein, described equivalent electrical information comprises circuit node equivalent parasitic capacitances and circuit node equivalence conducting resistance;
Wherein, the existing stray capacitance sum that described circuit node equivalent parasitic capacitances is institute's wired network, the device namely comprising described gauze is connected to the stray capacitance between the stray capacitance of described gauze and described gauze interconnection line;
Wherein, the stray capacitance that the device of described gauze is connected to described gauze calculates according to such as formula (2) Suo Shi;
Cnet.n,exist,dev＝ΣCnet.n,exist,dev,i
(2)
Wherein,
i＝1,2,3,…,Nnet,n,dev_cnum；
Nnet, n, dev_cnum are the stray capacitance quantity that on gauze n, device causes;
Cnet.n, exist, dev are the stray capacitance that the device of described gauze n is connected to described gauze;
Wherein, the stray capacitance between described gauze interconnection line calculates and calculates according to such as formula (3) Suo Shi;
Cnet.n,exist,wire＝ΣCnet.n,exist,wire,i
(3)
Wherein,
i＝1,2,3,…,Nnet,n,wire_cnum；
Nnet, n, wire_cnum are the stray capacitance quantity that on described gauze n, interconnection line causes;
Cnet.n, exist, wire are the stray capacitance between described gauze n interconnection line;
Wherein, the computing method of described circuit node equivalence conducting resistance comprise the steps:
A calculate power supply to described gauze corresponding node between to power supply equivalent resistance;
B calculate ground wire to gauze corresponding node between equivalent resistance over the ground;
C is described in power supply equivalent resistance and described equivalent resistance over the ground, and choosing maximal value is described circuit node equivalence conducting resistance;
Wherein, described limit stray capacitance is by calculating as shown in the formula (4):
Cnet,n,extra_limit＝Tdealylimit,n/Ron-Cnet.n,exist
(4)
Wherein,
Tdealylimit, n are the latency limit of gauze n;
Ron is described gauze equivalence conducting resistance;
Cnet.n, exist are the equivalent parasitic capacitances of gauze n;
Cnet, n, extra_limit are the mute metal filled limit stray capacitance introduced to gauze n of redundancy.
2. method according to claim 1, is characterized in that, the span of described constant k is between [0.01,0.10].
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Non-Patent Citations (2)
| Title |
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| 冯春阳.基于粗糙抛光垫模型的化学机械抛光工艺建模与仿真方法.《纳米集成电路化学机械抛光工艺建模与仿真及可制造性设计技术研究》.2010,第33-35、52-55页. * |
| 精确寄生参数提取软件设计和实现;孙世磊等;《计算机工程与应用》;20080721(第21期);第49-51页 * |
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