TW201629815A - Method, device and computer program product for integrated circuit layout generation - Google Patents

Abstract

A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Description

Method, device and computer program product for generating integrated circuit layout

The present disclosure relates to methods, apparatus, and computer program products for use in integrated circuit layout generation.

The recent trend toward miniaturization of integrated circuits (ICs) has resulted in smaller devices that consume lower power and provide more functionality at higher speeds. Miniaturization processes have resulted in more stringent design and/or manufacturing specifications. Develop different electronic design automation (EDA) processes to generate, optimize, and evaluate IC designs while ensuring compliance with design and manufacturing specifications.

Some embodiments of the present disclosure provide a method that is at least partially performed by a processor, the method comprising performing an air gap insertion process, the air gap insertion process comprising a plurality of meshes that sequentially sort the layout of the integrated circuits; Inserting an air gap pattern adjacent to the nets according to a sorting order of the nets; and producing a modified layout of the integrated circuit, the modified layout including the nets and the inserted air gap pattern.

Some embodiments of the present disclosure provide an apparatus including at least one processor for performing a virtual mesh and air gap insertion process, the virtual mesh and air gap insertion process including a plurality of meshes for sequentially arranging the layout of the integrated circuits; a sorting order of the nets, inserting a virtual net and an air gap pattern adjacent to the nets; and generating the product A modified layout of the body circuit, the modified layout including the mesh, the inserted virtual mesh, and the inserted air gap pattern.

Some embodiments of the present disclosure provide a computer program product comprising a non-transitory computer readable medium, comprising instructions therein, when executed by at least one processor, causing the at least one processor to perform in-product Selecting a candidate network for air gap insertion in a plurality of networks of the body circuit; determining various scaling ratios of the candidate network based on a length of the corresponding candidate network; estimating a capacitance of the candidate network based on a corresponding scaling ratio of the candidate network And performing at least one of full wiring, track distribution, and detailed routing based on the estimated capacitance of the candidate network, resulting in a layout of the integrated circuit.

200A‧‧‧ layout

202, 204, 206, 208, 210, 212‧‧‧

222, 224, 226, 228‧‧ air gap patterns

200B‧‧‧IC

231, 233‧‧‧ conductive layer

232, 234‧‧‧ dielectric layer

235, 244, 246, 248‧‧‧ conductive patterns

236, 238, 239‧‧‧ dielectric materials

237‧‧‧Transmission pathway

244, 246, 264, 266‧‧ air gap

400A‧‧‧ layout

402, 404, 406‧‧‧

407, 408‧‧‧ edge

411, 413, 431, 435, 437‧‧ air gap patterns

422, 424, 426, 428‧‧‧

442, 444, 446, 448, 450, 452‧‧

453, 455, 457, 459 ‧ ‧ air gap pattern

600A‧‧‧ layout

602, 604, 606‧‧‧

608, 610‧‧‧Virtual Network

611, 613, 615, 617‧‧ air gap patterns

600B‧‧‧ layout

622, 624, 626, 632‧‧‧

628, 630, 664, 684‧‧‧ virtual network

600C‧‧‧ layout

652, 654, 656, 658, 660, 662‧‧

671, 673, 675, 677, 679‧‧ air gap patterns

600D‧‧‧ layout

691, 693, 695, 677 and 699 ‧ air gap patterns

900A‧‧‧ layout

902, 904, 906, 908, 910‧‧

912‧‧‧ grid lines

913, 915 ‧ ‧ air gap pattern

922, 923‧‧‧

932, 934, 936‧‧‧ candidate network

937, 939 ‧ ‧ air gap pattern

941, 943‧‧ ‧ access

945, 947‧‧‧ areas

1100‧‧‧Computer system

1101‧‧‧ Processor

1102‧‧‧ memory

1104‧‧‧ Busbar

1106‧‧‧Network Interface (I/F)

1108‧‧‧Input/Output (I/O) devices

1110‧‧‧Storage

1114‧‧‧ core

1116‧‧‧User space

1118‧‧‧ hardware components

The aspects of the disclosure are best understood by the following detailed description and accompanying drawings. Note that various features are not drawn to scale in accordance with standard implementations of the industry. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 is a functional flow diagram illustrating at least a portion of an IC design process in accordance with some embodiments.

2A is a schematic plan view showing a partial layout of an IC in accordance with some embodiments.

2B is a partial cross-sectional view of an IC fabricated in accordance with some embodiments.

3 is a flow chart illustrating an air gap insertion method in accordance with some embodiments.

4A through 4D are schematic plan views illustrating different portions of an IC layout in accordance with some embodiments.

5 is a flow diagram illustrating a virtual network and air gap insertion method in accordance with some embodiments.

6A-6D illustrate different portions of an IC layout in accordance with some embodiments Plane schematic.

7 is a flow chart illustrating a portion of an IC design process in accordance with some embodiments.

8 is a functional flow diagram illustrating an EDA tool in accordance with some embodiments.

9A is a schematic plan view showing a portion of an IC layout in accordance with some embodiments.

9B illustrates a diagram for determining the scale used by an EDA tool in an IC design, in accordance with some embodiments.

9C-9E are schematic plan views illustrating different portions of an IC layout in accordance with some embodiments.

10 is a functional flow diagram illustrating at least a portion of an IC design process in accordance with some embodiments.

11 is a block diagram illustrating a computer system in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing the various features of the present application. Specific examples of components and configurations are described below to simplify the disclosure of the present application. Of course, these are merely examples and are not intended to limit the application. For example, the following description of forming an initial feature on or over a second feature may include forming first and second features of direct contact, and may also include embodiments for forming other features between the first and second features. Thus, the first and second features are not in direct contact. Furthermore, the application may repeat the component symbols and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and is not intended to govern the relationship between the various embodiments and/or the structures discussed.

1 is a functional flow diagram illustrating at least a portion of a design process 100 in accordance with some embodiments. The design process 100 uses one or more EDA tools for generating, optimizing, and/or evaluating the IC design prior to fabrication of the IC. In some embodiments, an EDA worker It is used to execute one or more sets of executable instructions for performing the functions referred to, as described herein.

In operation 110, the circuit designer provides the IC design. In some embodiments, the IC design includes a schematic, that is, a circuit diagram of the IC. In some embodiments, the generated or provided schematic is a netlist, such as a simulation program with integrated circuit emphasis (SPICE) netlist. In some embodiments, pre-layout simulations are performed on the design to determine if the design meets predetermined specifications. Redesign the IC when the design does not meet the predetermined specifications. In at least one embodiment, the pre-layout simulation is omitted.

At operation 120, an IC layout is generated based on the design. The layout includes the physical locations of the different circuit components of the IC, as well as the different networks interconnected with the circuit components. For example, the resulting layout is a graphic design system (GDS) file. Other file formats for describing the design are within the scope of various embodiments. In some embodiments, it is through an automatic placement and routing (APR) tool. The architecture and functionality of the example APR tool is depicted in FIG. 8, in accordance with some embodiments.

At operation 130, a virtual insertion process is performed to insert the virtual features into the layout. In at least one embodiment, the purpose of virtual feature insertion is to improve yield and quality. For example, IC production involves different processes including, but not limited to, deposition, optical microlithography, etching, chemical mechanical polishing (CMP), and the like. A CMP process is performed for etching back and planarizing the conductive material and/or the dielectric material, and chemical etching and mechanical polishing are involved in the material removal process. In some embodiments, the insertion of the dummy features improves the density of the conductive material in the fabricated IC, such as the density of the metal, to achieve a mechanical strength sufficient to ensure CMP quality. In another example, when adjacent conductive patterns are broadly spaced apart from each other by an interval greater than a predetermined value, a metal bias effect may occur during the manufacturing process, and a wide phase is caused. The width of the conductive pattern becomes wider than the width of the original design, thus causing variations in impedance, capacitance, and/or circuit performance in the unplanned. In some embodiments, the insertion of a virtual feature between the broadly spaced conductive materials reduces the likelihood of metal biasing effects and improves the quality and/or performance of the fabricated IC. In at least one embodiment, the virtual insertion process is performed by the APR tool and/or design-rule-check (DRC) tool described herein. For example, U.S. Patent No. 7,801,717 and U.S. Patent No. 8,307,321 are incorporated herein by reference. Again, in accordance with some embodiments, the virtual insertion process is as described in Figures 5 and 6A through 6D.

At operation 140, an air gap insertion process is performed to insert an air gap pattern in the layout. The air gap pattern inserted in the layout causes an air gap to be formed in the fabricated IC for reducing parasitic capacitance and improving the performance of the fabricated IC, as shown in FIGS. 2A to 2B. For example, according to some embodiments, the air gap insertion process is as described in Figures 3 and 4A through 4D.

At operation 150, a resistor and capacitor (RC) extraction is performed by the RC extraction tool. The RC extraction determines parasitic parameters of components in the IC, such as parasitic resistance and parasitic capacitance, for timing and/or power simulation in subsequent operations. This parasitic parameter is not what the circuit designer expects, but rather the result of the architecture and/or material that becomes a different component in the IC. The extracted parasitic parameters are included in the RC technical file. For example, according to some embodiments, the architecture and functionality of the RC extraction tool is as described in FIG.

In some embodiments, one or more evaluations and/or inspections are performed. For example, a layout-versus-schematic (LVS) check is performed to ensure that the resulting layout corresponds to the design. Furthermore, for example, the design rule check is performed by the DRC tool to ensure that the layout satisfies some manufacturing design rules, that is, to ensure that the IC can be manufactured. When one of the checks fails, the at least one layout or design is corrected by returning the process to operation 110 and/or operation 120.

At operation 160, a timing end check is performed (timing sign-off) Check) (also referred to as post-layout simulation) to determine if the layout meets the predetermined specifications. In some embodiments, when the post-layout simulation indicates that the layout does not meet a predetermined specification, such as when there is an undesirable time delay, by returning the process to any of operations 110-140, for at least one layout or Designed for correction. Otherwise, the layout passes to operation 170 for fabrication. In some embodiments, one or more of the above operations are omitted.

2A is a plan view showing a layout 200A of a portion of an IC in accordance with some embodiments. The layout 200A includes a plurality of nets 202, 204, 206, 208, 210, and 212. Layout 200A further includes a plurality of air gap patterns 222, 224, 226, and 228 between respective pairs of nets. For example, air gap pattern 222 is between web 202 and web 212, air gap pattern 224 is between webs 204 and 206, air gap pattern 226 is between webs 206 and 208, and air gap pattern 228. The system is between the networks 208 and 210.

Although not shown in FIG. 2A, layout 200A further includes a plurality of circuit elements interconnected by a plurality of nets. Circuit components are active components or passive components. For example, active components include, but are not limited to, transistors and diodes. For example, the transistor includes, but is not limited to, a metal oxide semiconductor field effect (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, and a bipolar complementary metal oxide semiconductor (bipolar). Junction transistor, BJT), high voltage transistor, high frequency transistor, p-channel and/or n-channel field effect transistor (PFET/NFET), FinFET, planar MOS transistor with rising source/drain . Passive components include, for example, but are not limited to, capacitors, inductors, fuses, and resistors. In some embodiments, the circuit component has one or more nodes from which electronic signals are output or output. In some embodiments, a pair of nodes are electrically connected to each other by interconnection. A set of electrical connections interconnect to form a mesh. In at least one embodiment, the network includes a single interconnect. In at least one embodiment, the IC includes a conductive layer and a dielectric layer in an interconnect configuration. An interconnect is formed in the conductive layer. In at least one embodiment, the net is included in a single guide One or more interconnects formed in the electrical layer. In at least one embodiment, the mesh includes interconnects formed in different conductive layers of the IC, and electrically interconnects one or more vias formed in the different conductive layers. For simplicity of illustration, the different network systems in the embodiments described herein are illustrated in one or more figures that comprise a single interconnect and/or are formed in a single conductive layer. The descriptions described herein also apply to embodiments in which the web comprises more than one interconnect and/or is formed in more than one conductive layer.

The plurality of networks includes signal networks 202, 204, 206, 208, and 210, and a virtual network 212. A signal network is a network used to transmit signals or power to circuit components. Signals include, for example, but are not limited to, data signals, control signals, clock signals, and the like. A virtual network is a network that is not used to transmit signals or power. The virtual network is, for example, a floating network. In the descriptions given herein, "net" means "signal network" and "virtual network" unless otherwise stated.

The air gap patterns 222, 224, 226, and 228 are patterns in the mask layer included in the layout 200A. The air gap patterns 222, 224, 226, and 228 cover corresponding spaces between adjacent nets. For example, the air spacing pattern 222 covers the spacing between adjacent webs 222, 212. When the IC is fabricated, a dielectric material is formed in the space covered by the air gap patterns 222, 224, 226, and 228, and a corresponding air gap is formed between adjacent nets, for example, as shown in FIG. 2B.

2B is a cross-sectional view showing a portion of the fabricated IC 200B in accordance with some embodiments. In the example of FIG. 2B, portions of the fabricated IC 200B correspond to the cross-sectional views along line II-II of FIG. 2A. The fabricated IC 200B includes a plurality of staggered conductive layers 231, 233 and dielectric layers 232, 234. For example, the dielectric layer 232 is disposed above the conductive layer 231, the conductive layer 233 is disposed above the dielectric layer 232, and the dielectric layer 234 is disposed above the conductive layer 233. Conductive layer 231 includes a conductive pattern 235 that is electrically connected to the underlying conductive layer or circuit component. Conductive pattern 235 is electrically coupled to conductive path 237 in dielectric material 236 of dielectric layer 232. Conductive layer 233 is included in the dielectric material A plurality of conductive patterns 244, 246, 248. The conductive pattern 248 is electrically coupled to the conductive pattern 235 by a conductive via 237 to form a mesh in the plurality of conductive layers, as described herein. Conductive patterns 244, 246, 248 correspond to nets 204, 206, and 208 in layout 200A of Figure 2A. The air gap 264 is between the conductive patterns 244 and 246. Air gap 266 is between the conductive patterns 246 and 248. The air gaps 264, 266 correspond to the air gap patterns 224, 226 in the layout 200A of Figure 2A. In one or more embodiments, a portion of the dielectric material is present between the air gap and the corresponding conductive pattern due to process variations and/or material properties. For example, although the air gap pattern 224 in the layout 200A covers the space between the meshes 204, 206 from the edge to the edge, portions 265, 267 of the dielectric material 238 are still present in the air gap 264 and the corresponding conductive patterns 244, 246. Between the spaces being covered. In some embodiments, the air gap extends from the edge to the edge between the corresponding conductive patterns, for example, portions 265, 267 of dielectric material 238 are not present in the fabricated IC. The area between adjacent conductive patterns that are not covered by the air gap pattern is filled with a dielectric material. For example, region 229 in layout 200A of Figure 2A is not covered by the air gap pattern and will be filled with dielectric material 238 in IC 200B being fabricated. Dielectric material 239 of dielectric layer 234 is tied over conductive layer 233. In at least one embodiment, the top of the air gap protrudes into the dielectric material 239 due to one or more factors associated with the material and/or process of forming the dielectric material 239. For example, the top 269 of the air gap 266 protrudes into the dielectric material 239. For example, the material of the conductive patterns 235, 244, 246, 248 and/or the conductive via 237 comprises a metal, such as copper. For example, the materials of dielectric materials 236, 238, 239 include, but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCNN, or combinations thereof. For example, U.S. Patent No. 8,456,009, the disclosure of which is incorporated herein by reference. The described architecture of the fabricated IC is an example. Other architectures are also within the scope of different embodiments.

For the purpose of circuit miniaturization, for example, the density of the interconnect structure of the interconnect and the circuit elements in the IC is increased, and the size of the interconnect and circuit components is reduced. Therefore, pass The parasitic capacitance between the conductive structures is potentially increased, which in turn potentially increases the power consumption and/or time delay of the signals transmitted between different circuit elements of the IC. The parasitic capacitance between the conductive structures depends on the dielectric constant of the insulation between the conductive structures. Since the dielectric constant of air (about 1) is lower than the dielectric constant of different dielectric materials, an air gap is formed between the conductive structures of ICs other than the dielectric material to reduce the relationship between adjacent conductive structures. The overall effective dielectric constant of the insulation and the reduction of parasitic capacitance. In some embodiments, the "air gap" includes air, vacuum, gas, or a substance having a dielectric constant lower than that of the dielectric material formed between the conductive structures of the IC. The air gap forms one or more air gap limits, as described herein. Some embodiments provide different air gap insertion methods for maximizing, optimizing, or increasing the effects of parasitic capacitance reduction while meeting air gap limitations.

FIG. 3 is a flow chart illustrating an air gap insertion method 300 in accordance with some embodiments. 4A through 4D are schematic plan views illustrating different portions of IC layouts 400A through 400D of various implementations of method 300, in accordance with some embodiments. The method 300 includes an air gap insertion process 305 in which an air gap pattern is inserted to be adjacent to a plurality of nets of the layout of the IC. The method 300 further includes an operation 315 in which a modified layout is generated that includes a plurality of meshes and an interposed air gap pattern.

In operation 325 of the air gap insertion process 305 of FIG. 3, the plurality of network systems in the layout or partial layout of the integrated circuit are sequentially sorted. In some embodiments, a plurality of networks are classified by the corresponding length of the network (also referred to herein as the length of the network). For example, as shown in FIG. 4A, the layers of layout 400A include nets 402, 404, 406. Net 404 is adjacent to nets 402, 406 and is separated from nets 402, 406 by edge-to-edge spacing s. For example, the spacing s is the distance between the edge 407 of the network 402 and the edge 408 of the mesh 404. The interval s satisfies the limitation of the air gap insertion. For example, the interval s is equal to or less than the maximum interval at which the air gap is inserted. When the spacing between adjacent nets is greater than the maximum spacing of air gap insertion, no air gap pattern is inserted between adjacent nets. In at least one embodiment, the spacing s is the design and/or system of the IC The minimum spacing between adjacent networks allowed by the specification is made, and the air gap is allowed to be inserted only between the two adjacent networks of the interval s. In the example architecture of FIG. 4A, the length of the net 404 (represented by "Length" in FIG. 4A) is greater than the length of the net 402, which is greater than the length of the net 406. The nets 402, 404, 406 are sorted in the order of corresponding lengths, that is, in the order of the net 404, the net 404, and the net 406.

After classifying the plurality of nets, the air gap pattern is inserted to be adjacent to the plurality of nets according to the sorting order of the plurality of nets. For example, in operation 335 of the air gap insertion process 305 of FIG. 3, the indicator i is set to one. This corresponds to selecting a first net for air gap insertion between the networks classified by the IC. In the example architecture of Figure 4A, prior to other webs 402, 406 having shorter lengths, the web 404 having the longest length is selected for air gap insertion.

At operation 345 of the air gap insertion process 305 of FIG. 3, at least one air gap pattern is inserted to be adjacent to the currently selected mesh, namely Net[i]. In the example architecture of FIG. 4A, air gap patterns 411, 413 adjacent to the currently selected mesh 404 are inserted. An air gap pattern 411 is inserted between the currently selected mesh 404 and the adjacent mesh 402 to reduce parasitic capacitance between the meshes 402, 404. An air gap pattern 413 is inserted between the currently selected mesh 404 and another adjacent mesh 406 to reduce parasitic capacitance between the meshes 404, 406.

At operation 355 of the air gap process 305 of FIG. 3, it is determined whether the air gap pattern that has been inserted satisfies the limit. In the example architecture of FIG. 4A, it is determined that the air gap patterns 411, 413 that have been inserted satisfy the limit. In some embodiments, the restriction includes an air gap density, that is, a ratio of an overall area of the air gap covered by the inserted air gap pattern to an overall area of the layer in which the air gap is to be formed. The overall area of the layer includes the area of the conductive structure (eg, mesh) in the layer and the area of insulation between the mesh (eg, air gap and dielectric material). When the air gap density of the air gap pattern that has been inserted is greater than a predetermined air gap density limit, the mechanical strength of the layer is potentially insufficient to resist stresses in the manufacturing process and/or in the final product. In some embodiments, air gap density limits 50%. Other air gap density limits and/or limitations other than air gap density are within the scope of different embodiments.

At operation 365 of the air gap insertion process 305 of FIG. 3, the index i is incremented in response to the determination that the inserted air gap satisfies the limit (ie, YES at operation 355). This corresponds to selecting the next net between the networks classified by the IC for air gap insertion. In the example architecture of Figure 4, the next network, i.e., network 402, is selected for air gap insertion. The process then returns to operation 345, where at least one air gap pattern adjacent to the mesh 402 is inserted, such as between the mesh 402 and another network adjacent to the mesh 402. Then, the process proceeds to operation 355 where it is determined whether the air gap patterns that have been inserted, such as the air gap patterns 411, 413, and one or more air gap patterns inserted adjacent to the mesh 402, satisfy the limit. In response to the assertion that the inserted air gap pattern satisfies the limit ("YES" at operation 355), the indicator i is incremented again, and operations 345, and 355 are performed for the next network, such as network 406 of FIG. 4A.

In operation 375 of the air gap insertion process 305 of FIG. 3, in response to the determination that the inserted air gap pattern does not satisfy the limit (NO at operation 355), the last inserted air gap pattern is removed, and the process proceeds to operation 315. A modified layout of the IC is produced with the remaining air gap pattern that has been inserted. For example, when the current mesh is the mesh 402 in the example architecture of FIG. 4A, and operation 355 refers to the air gap pattern that has been inserted that does not meet the limit, at least one air gap pattern inserted adjacent to the mesh 402 is removed. In some embodiments, all air gap patterns inserted adjacent to the current mesh are removed in response to a determination that the limit is satisfied when some of the air gap patterns have been inserted adjacent to the current mesh. In some embodiments, in response to the determination that the air gap pattern has been inserted adjacent to the current web without satisfying the limit, the inserted air gap patterns adjacent to the current web are removed one by one until the limit is met. Other configurations are within the scope of various embodiments.

In some embodiments, by classifying a plurality of networks in an IC or a portion of an IC, according to a corresponding length of the network, before a shorter length of the network, for a longer length of the network, Insert an air gap pattern. Thus, in one or more embodiments, along the long net, the parasitic capacitance reduction is optimized for the grid capacitance, and the long net has a greater impact on timing delay and circuit performance than the short network potential. An example of a conventional classification described. Other classification configurations are within the scope of various embodiments.

In some embodiments, the IC or a network in a portion of the IC is classified by a projection length. The projected length of a pair of adjacent nets is the length along which the adjacent nets extend along each other. In the example architecture of FIG. 4B, the projected length a of the nets 422, 424 is the length along which the nets 422, 424 extend along each other. The projected length a corresponds to the length of the air gap that can be inserted between the nets 422, 424. The projected length b of the nets 424, 426 is the length along which the nets 424, 426 extend along each other. The projected length b corresponds to the length of the air gap that can be inserted between the nets 424, 426. The projected length c of the nets 426, 428 is the length along which the nets 426, 428 extend along each other. The projected length c corresponds to the length of the air gap that can be inserted between the nets 426, 428. In the architectural example of FIG. 4B, the projection length a is greater than the projection length c, which is greater than the projection length b.

In some embodiments, after sorting the mesh by the corresponding projected length, inserting an air gap between the nets having a longer projected length, and checking the limits, as in FIG. 3, before the net having a shorter projected length Operations 335, 345, 355, 365, and 375 are described. In the architectural example of FIG. 4B, an air gap pattern 431 is first inserted between the nets 422, 424 having the longest projection length a. It is judged whether or not the inserted air gap pattern 431 satisfies the limit. Assuming that the inserted air gap pattern 431 meets the limit, the process proceeds to insert an air gap pattern 435 between the nets 426, 428 having the second long projected length c. It is judged whether or not the inserted air gap pattern 435 satisfies the limit. If the inserted air gap patterns 431, 435 satisfy the limit, the process proceeds to insert an air gap pattern between the webs 424, 426 having the projected length b (shown as 437 in Figure 4C). It is judged whether or not the inserted air gap pattern, such as the air gap patterns 431, 435, and the air gap pattern inserted between the nets 424, 426 satisfy the restriction. Assume that the inserted air gap pattern does not meet the limit, remove the net The last inserted air gap pattern between 424, 426 (shown as 437 in Figure 4C). A modified layout is created having nets 422, 424, 426, 428 and interposed air gap patterns 431, 435, as shown in Figure 4B. In implementing one or more embodiments of the sorting configuration shown in Figure 4B, the parasitic capacitance reduction is optimized for coupling the capacitance between the nets.

In some embodiments, the network in the IC or part of the IC is classified by a cost function. For example, the cost function Cost1 is the sum of the projected lengths along each net, as judged by the following equation: Where i is the i-th network in a plurality of networks, N is the number of networks adjacent to the i-th network among the plurality of networks, and j is adjacent to the i-th network among the N networks The jth net, Proj_Length(j) is the projection length of the i-th net and the j-th net extending along each other, and the length of the i-th net of the Length(i).

In the example architecture of Figure 4C, it is contemplated to use the same meshes 422, 424, 426, and 428 as shown in Figure 4B for air gap insertion. The nets 422, 424, 426 and 428 in Fig. 4C are sorted by replacing the projection length described in Fig. 4B with the cost function Cost1. For the net 422, the cost function Cost1 is the projection length a. For the net 424, the cost function Cost1 is the sum of the projection length a plus the projection length b, and the projection length b is the largest between the networks 422, 424, 426, 428. For the net 426, the cost function Cost1 is the sum of the projected length b and the projected length c, and the projected length c is the second largest between the nets 422, 424, 426, 428. For the net 428, the cost function Cost1 is the projected length c, which is the smallest between the networks 422, 424, 426, 428. Therefore, the networks are classified in the following order: network 424, network 426, network 422, and network 428.

In some embodiments, after classifying the net by the cost function Cost1, inserting the air gap pattern with a larger Cost1 before the net with a smaller Cost1 The nets are adjacent, as well as the check limits, as described in operations 335, 345, 355, 365, and 375 in FIG. In the example architecture of FIG. 4C, prior to the other nets 422, 426, 428, the air gap patterns 431 and 437 are inserted adjacent to the net 424 having the largest Cost1. It is judged whether or not the inserted air gap patterns 431, 437 satisfy the limit. Assuming that the inserted air gap patterns 431, 437 meet the constraints, since the mesh 426 has the second largest Cost1, the process proceeds until the air gap pattern is inserted between the meshes 426, 428 (shown as 435 in Figure 4B). It is judged whether or not the air gap pattern inserted between the inserted air gap patterns 431, 437 and the nets 426, 428 satisfies the limit. Assuming that the inserted air gap pattern does not meet the limit, the last inserted air gap pattern between the meshes 426, 428 is removed (as indicated by 435 in Figure 4B). A modified layout is produced having nets 422, 424, 426 and 428, and interposed air gap patterns 431, 437, as shown in Figure 4C. In one or more embodiments of implementing the classification configuration using the cost function Cost1 described in FIG. 4C, the parasitic capacitance reduction is optimized for the total capacitance of the network.

According to some embodiments, another example cost function Cost2 is the ratio of the cost function Cost1 of each network to the length of the network, as judged by the following equation: Cost2(i)=Cost1(i)/Length(i) (2)

In the example architecture of FIG. 4D, nets 442, 446, 448, 450, and 452 have the same length L, and net 444 has a length of 2L. For nets 444 and 450, the cost function Cost1 is 2L. However, the length of the net 444 is 2L, while the length of the net 450 is L. Therefore, the cost function Cost2 of the network 444 is 1, and the cost function Cost2 of the network 450 is 2. When the network is classified by the cost function Cost2, the ranking of the network 450 having the larger Cost2 is higher than that of the network 444 having the smaller Cost2.

In some embodiments, after classifying the net by the cost function Cost2, the air gap pattern is inserted adjacent to the net with the larger Cost2 before the net with the smaller Cost2, and the check limit is checked, as in FIG. Operations 335, 345, 355, 365, and 375 are described. For example, prior to inserting the air gap patterns 457, 459 adjacent to the lower ranked mesh 444, the air gap patterns 453, 455 are inserted to match the higher ranked mesh 450. Adjacent. Prior to implementing one or more embodiments of the classification configuration using the cost function Cost2 described in FIG. 4D, the parasitic capacitance reduction is optimized for the ratio of the total capacitance of the network to the length of the network.

The described classification configurations are examples, and other classification configurations are within the scope of various embodiments. In some embodiments, different classification configurations are applied at different portions of the IC. In some embodiments, when the sorting configuration results in an air gap pattern that has not passed the evaluation or inspection at a later stage, another sorting configuration is applied, again creating an air gap pattern.

In some embodiments, the parasitic capacitance reduction optimization process involves not only air gap insertion but also virtual mesh insertion.

FIG. 5 is a flow diagram illustrating a virtual mesh and air gap insertion method 500 in accordance with some embodiments. 6A-6B are schematic plan views illustrating different portions of IC layouts 600A-600B to illustrate different implementations of method 500, in accordance with some embodiments. The method 500 includes a virtual mesh and air gap insertion process 505 in which a virtual mesh and air gap pattern are inserted adjacent to a plurality of nets in the layout of the IC. The method 500 further includes an operation 515 in which a modified layout is generated that includes a plurality of nets and an inserted virtual mesh and air gap pattern.

In operation 525 of the virtual mesh and air gap insertion process 505 of FIG. 5, a plurality of nets in the layout of the integrated circuit or in a partial layout are sequentially sorted. In some embodiments, a plurality of nets are sorted by corresponding network lengths, as shown in Figure 4A. For example, as shown in FIG. 6A, the layer of layout 600A includes meshes 602, 604, 606. The net 604 has the longest length (indicated by "Length" in Fig. 6A) compared to the nets 602, 606.

After classifying the plurality of nets, the virtual net and the air gap pattern are inserted to be adjacent to the plurality of nets according to the sorting order of the plurality of nets. For example, in operation 535 of the virtual mesh and air gap insertion process 505 of FIG. 5, the indicator i is set to one. This is equivalent to selecting the first network between the classification networks of the IC for virtual network and air gap insertion. In the example architecture of Figure 6A, the selection has the longest before other networks 602, 606 having shorter lengths A length of network 604 for virtual network and air gap insertion.

In operation 540 of the virtual network and air gap insertion process 505 of FIG. 5, at least one virtual network is inserted to be adjacent to the currently selected network, namely Net[i]. In the example architecture of FIG. 6A, virtual networks 608, 610 are inserted at intervals s adjacent to the currently selected network 604, which allows the air gap pattern to be inserted between the virtual networks 608, 610 and the currently selected network 604. .

At operation 545 of the virtual mesh and air gap process 505 of FIG. 5, at least one air gap pattern is inserted adjacent to the currently selected mesh, namely Net[i]. In the example architecture of FIG. 6A, the interposed air gap patterns 611, 613, 615, and 617 are adjacent to the currently selected mesh 604. Specifically, on the one hand, between the currently selected net 604 and on the other hand between the corresponding nets 608 and 610, air gap patterns 611, 613, 615 and 617 are inserted to reduce parasitic capacitance between corresponding adjacent nets. .

At operation 555 of the virtual mesh and air gap insertion process 505 of FIG. 5, it is determined whether the air gap pattern that has been inserted satisfies the limit, as described in operation 355 of FIG.

In operation 565 of the virtual mesh and air gap insertion process 505 of FIG. 5, in response to the determination that the inserted air gap pattern satisfies the limit ("YES" at operation 555), the index i is incremented, and the process returns to operations 540 and 545, For the next network between the classification networks of the IC, at least one virtual network and at least one air gap pattern are inserted, as described in operation 365 of FIG.

In operation 575 of the virtual mesh and air gap insertion process 505 of FIG. 5, in response to the determination that the inserted air gap pattern does not satisfy the limit (NO at operation 555), the last inserted air gap pattern is removed, and then the process is performed. To operation 515, as described in operation 375 of FIG.

In some embodiments, in response to the determination that the already inserted air gap pattern does not satisfy the limit, the last inserted air gap pattern is removed and the last inserted virtual net is removed. In some embodiments, the response when some air gap patterns have been inserted and/or When the virtual network is adjacent to the current network and does not satisfy the limitation, the air gap pattern and the virtual network adjacent to the current network are removed. In some embodiments, in response to the determination that the limit is satisfied when some air gap patterns have been inserted and the virtual network is adjacent to the current network, the air gap pattern adjacent to the current network is removed one by one until the limit is met. When the air gap pattern inserted between the current network and the inserted virtual network is removed, the virtual network is also removed. Other configurations are within the scope of various embodiments.

Method 500 may achieve one or more advantages and/or effects of method 300, in accordance with some embodiments. In at least one embodiment, the additional insertion of the virtual mesh increases air gap coverage. For example, in the layout 400A of FIG. 4A, two air gap patterns 411, 413 are inserted, and in the layout 600A of FIG. 6A, four air gap patterns 611, 613, 615, 617 are inserted. Thus, in at least one embodiment, the method 500 can further enhance the parasitic capacitance reduction effect.

In some embodiments, the network in the IC or part of the IC is classified by a cost function. The example cost function Cost3 is judged by the following equation: Where i is the i-th network in the plurality of networks, N is the number of networks adjacent to the i-th network among the plurality of networks, and the j-th i-th net and the j-th net extend along each other Projection length, Cair_gap is the unit coupling capacitance between the i-th network and the j-th network, P is the number of insertable virtual networks adjacent to the i-th network, and k is insertable adjacent to the i-th network The kth network among the P virtual networks, Dummy_Length(k) is the length of the kth virtual network, and the unit coupling capacitance of the kth virtual network of the Cdummy system.

In the example architecture of FIG. 6B, layout 600B includes nets 622, 624, 626 and 632. The determination of the projected length of the web 624 relative to adjacent webs 622 and 626 is as described in Figure 4B. Based on the size and/or projected length of the nets 622, 624, 626, and 632, it is determined that the virtual nets 628, 630, and the virtual nets 628, 630 can be inserted adjacent to the net 624. Based on the size of the pluggable virtual network 628, 630, a cost function Cost3 (or Cap_Cost) associated with the capacitance inserted in the virtual network adjacent to the network 624 is determined. In a similar manner, the cost function Cost3 associated with the capacitance inserted in the virtual network adjacent to the other networks 622, 626 and 632 is determined, and the network 622, 624, 626 and 632 are classified by the cost function Cost3. The process then inserts the virtual network and air gap pattern as illustrated in FIG. One or more embodiments of the classification configuration are implemented in accordance with the cost function Cost3, which optimizes the parasitic capacitance reduction for the total capacitance of the network.

Another example cost function Cost4 is determined by the following equation: Cost 4( i )= Cap_Cost ( i ) / Length ( i ) (4) where i is the i-th network in the plurality of networks, and Length(i ) is the length of the i-th network.

After calculating the cost function Cost of the network, the network is classified by the calculated cost function value. The process then inserts the virtual network and air gap pattern as illustrated in FIG. In one or more embodiments that implement a classification configuration using the cost function Cost4, the parasitic capacitance reduction is optimized for the ratio of the total capacitance of the network to the length of the network.

Another example cost function Cost5 is determined by: Cost 5( i )= Cap_Cost ( i )× Res_Cost ( i ) (5) And the unit impedance of the kth virtual network of Rdummy.

After calculating the cost function Cost5 of the network, by calculating the cost Function value, classify the network. Then, the process inserts the virtual network and the air gap pattern, as shown in FIG. In one or more embodiments in which the classification configuration is implemented using the cost function Cost5, not only the cost function Cap_Cost associated with the capacitance of the inserted virtual network, but also the cost function Res_Cost associated with the resistance of the inserted virtual network is considered. In at least one embodiment, since the inserted virtual network contributes to the reduction in capacitance and at the same time increases the resistance due to the increased conductivity pattern corresponding to the virtual network, it is useful to additionally consider the resistance of the inserted virtual network.

The classification configuration of the virtual network and the air gap insertion is an example. Other classification configurations are also within the scope of various embodiments. In some embodiments, different classification configurations are applied in different portions of the IC. In some embodiments, when the sorting configuration results in an air gap pattern that does not pass the evaluation or inspection at a later stage, another sorting configuration is applied to regenerate the air gap pattern.

FIG. 6C illustrates a plan view of a portion of an IC layout 600C in accordance with some embodiments. Layout 600C includes nets 652, 654, 656, 658, 660, and 662. The adjacent webs 654, 656 are spaced apart from one another by an s that causes the air gap pattern 675 to be inserted between the webs 654, 656. Likewise, the spacing s between adjacent webs 658 and 660 and between adjacent webs 660 and 662 causes the corresponding air gap patterns 677, 679 to be inserted. However, the spacing between the webs 652 and 654 is 3 s, which is greater than the spacing s that allows air gap insertion. In some embodiments, a virtual network is inserted between two adjacent nets, the spacing of the two adjacent nets being greater than the maximum spacing for air gap insertion, such that the air gap pattern is inserted in the virtual network and two adjacent nets between. For example, a virtual network 664 of width s is inserted between the nets 652 and 654. Therefore, the interval between the virtual net 664 and each of the nets 652, 654 becomes an interval s that allows the air gap to be inserted. Accordingly, the air gap patterns 671, 673 can be inserted between the virtual net 664 and the corresponding nets 652, 654 to increase air gap coverage and reduce the parasitic capacitance of the nets 652, 654. The virtual network insertion technique described herein refers to a 3s virtual insertion. In some embodiments, a 3s virtual insertion is performed at operation 130, as described in FIG. In some embodiments, operation 130 After the 3s virtual insertion, the air gap insertion method is followed, as described in FIG. In some embodiments, a 3s virtual insertion is performed in virtual network and air gap insertion at operation 540, as described in FIG. Other configurations are also within the scope of various embodiments.

Taking layout 600C as an example, a 3s virtual insertion is performed in accordance with some embodiments to increase air gap coverage, however, virtual network and air gap insertion are not optimized. Figure 6D illustrates a partial plan view of an IC layout 600D with optimized virtual mesh and air gap insertion, in accordance with some embodiments. In at least one embodiment, layout 600D is obtained by performing method 500 of the classification configuration described using FIGS. 6A-6B and cost functions Cost3, Cost4, and Cost5. For example, as described in FIG. 6A, a classification configuration by network length is used in at least one embodiment to obtain a layout 600D. In the layout 600D, a virtual network 684 is inserted between the nets 654 and 658, and the air gap patterns 691, 693, 695, 677, and 699 are concentrated near the long nets 658, 660 and the inserted virtual net 684, as compared to the layout 600C. . Therefore, the parasitic capacitance of the long nets 658 and 660 is reduced, resulting in a greater amount of parasitic capacitance reduction than the layout 600C. In at least one embodiment, in layout 600C, the length of virtual mesh 664 and air gap patterns 671, 673, 675, and 679 are substantially equal to corresponding virtual mesh 684 and air gap patterns 691, 693, 695, and 699 in layout 600C. length. Thus, compared to layout 600C, layout 600D achieves a greater amount of parasitic capacitance reduction along the long and/or important mesh, and there is no substantial change to the coverage of the virtual mesh and air gap pattern.

FIG. 7 illustrates a partial flow diagram of an IC design process 700 in accordance with some embodiments.

At operation 715, an IC layout is generated. In at least one embodiment, the layout is generated by the APR tool described herein.

At operation 725, a virtual network insertion process is performed. In at least one embodiment, a virtual network is inserted to improve throughput and/or quality, as described in operation 130 of FIG. In at least one embodiment, a 3s virtual insertion is performed in the virtual network insertion process of operation 725.

At operation 735, an air gap insertion process is performed. In at least one embodiment, the air gap insertion method 300 is performed at operation 735. In some embodiments, the virtual mesh and air gap insertion method 500 is performed at operations 725 and 735. By operation 735, a modified IC layout is produced.

At operation 745, a timing end check is performed. In at least one embodiment, a timing end check is performed to determine if the modified IC layout satisfies a timing specification, as described in operation 160 of FIG.

The response-modified IC layout does not satisfy a timing specification ("NO" of operation 755), and the process proceeds to operation 765 to identify the failed signal path.

In some embodiments, the process further proceeds from operation 765 to operation 735 for air gap insertion optimization for the mesh in the failed signal path. For example, in one or more embodiments, for a network in an IC layout, using at least one of the classification configurations described in FIGS. 4A through 4D, such as net length, projection length, Cost1, or Cost2, the air gap insertion method is performed at operation 735. 300. The air gap insertion method 300 is again applied to the mesh in the failed signal path identified by operation 765 using at least one of the classified configurations, such as net length, projected length, Cost1 or Cost2. In at least one embodiment, the air gap insertion method 300 uses different sorting configurations for different process stages. For example, the air gap insertion method 300 uses a sorting configuration, such as a mesh length, to optimize the air gap insertion of the layout, and uses a different sorting configuration, such as Cost2, to optimize the air gap insertion of the failed signal path. Other configurations are also within the scope of various embodiments.

In some embodiments, the process proceeds further from operation 765 to operation 725 for virtual network and air gap insertion optimization for the network in the failed signal path. For example, in one or more embodiments, for a network in an IC layout, at least one of the classified configurations, such as network length, Cost3, Cost4, and Cost5, is used, and the virtual network and air gap insertion method is performed at operations 725, 735. 500. Use at least one of the described configurations, such as a network length Degree, Cost3, Cost4, or Cost5, the virtual mesh and air gap insertion method 500 is again applied to the network in the failed signal path identified by operation 765. In at least one embodiment, the air gap insertion method 300 performs different sorting configurations for different process stages. For example, the virtual network and air gap insertion method 500 uses a classification configuration, such as a network length, a virtual network and air gap insertion for optimizing the layout, and uses different classification configurations, such as Cost5, to optimize the virtual signal path for the failed signal path. The mesh is inserted into the air gap. Other configurations are also within the scope of various embodiments.

The response to the modified IC layout satisfies the determination of a timing specification ("YES" of operation 755), and the process ends at operation 755. In at least one embodiment, the modified layout has been evaluated or checked by the end of the sequence, or the output is used to fabricate the IC.

In other methods, air gap insertion is only a matter of production considerations, and when there is a violation of timing, the process returns to placement or is used to relocate and/or rearrange the program during the APR scheduling phase, which is time consuming. Compared to other methods, when there is a violation of timing, the IC design process 700 according to some embodiments does not return to the placement or scheduling phase; instead, the IC design process returns to the virtual network insertion and/or air gap insertion phase. Used to optimize the virtual network and/or air gap configuration described herein. According to some embodiments, the IC design process 700 does not involve a placement relocation and/or rescheduling procedure when one or more signal path timings end fails, and thus, in accordance with one or more embodiments, compared to other methods The IC design process 700 reduces cycle time. In some embodiments, the IC design process can be used for digital and analog design timing termination procedures for patching failed signal paths with reduced time periods. Method 700 may achieve one or more advantages and/or effects of method 300 and/or method 500, in accordance with some embodiments.

FIG. 8 illustrates a functional flow diagram of APR tool 800 in accordance with some embodiments. In at least one embodiment, APR tool 800 corresponds to the APR tool described in operation 120 of FIG. 1 and/or the APR tool described in operation 715 of FIG.

At operation 810, the APR tool 800 receives the input for generating the IC layout. In. In the architectural example of Figure 8, the input contains an IC design in the form of a netlist, as described in operation 110, containing a Synopsys design constraint (SDC) file for design constraints and layout plans. Other configurations are within the scope of various embodiments. For example, in some embodiments, the APR tool 800 layouts the program to identify circuit components that are electrically connected to each other and placed close to each other for reducing the area of the IC and/or reducing the interconnection or connection. The time delay of the signal on the network side of the connected circuit component. In some embodiments, the APR tool 800 differentiates to divide the design into a plurality of blocks or groups, such as a clock and a logical group.

In some embodiments, at operation 812, the APR tool 800 performs power planning based on an electronically designed differentiation and/or layout plan.

At operation 814, the APR tool 800 places. For example, one or more phase placements are performed including, but not limited to, pre-placement optimization, in-place optimization, and post-placement optimization before and/or after clock tree synthesis (CTS).

At operation 816, the APR tool 800 performs CTS to minimize skew and/or delay.

At operations 818, 820, and 822, the APR tool 800 is routed such that different nets interconnect the placed circuit components. Route the wiring to ensure that the arranged interconnect or network meets a set of restrictions.

Specifically, at operation 818, the APR tool 800 performs full wiring, allocating routing sources for the interconnect or network. For example, in the full-wiring process, the non-planar area is divided into sub-areas, the pins of the placed circuit components are mapped to the sub-area, and the mesh is constructed as a sub-area group, wherein the interconnects can be physically wired.

At operation 820, the APR tool 800 performs a track assignment to distribute the interconnect or net to the corresponding conductive layer of the IC.

At operation 822, the APR tool 800 performs detailed routing, routing interconnections or meshes within the assigned conductive layers and within the full wiring source. For example, in detail wiring In the process, physical interconnections are generated in the corresponding sub-wiring groups defined by the full wiring and in the conductive layers defined by the track classification.

At operation 824, the APR tool 800 outputs an IC layout that includes the placed circuit components and the wiring network. The operations described by the APR tool 800 are examples. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, one or more of the operations are omitted.

In some embodiments, the APR tool 800 is used to minimize the network length of the wiring network and/or to minimize the overall area of the IC during the routing operation. In some cases, routing operations tend to increase the density of the conductive elements and/or the projected length of the webs along each other. In some embodiments, to reduce parasitic capacitance and/or signal crosstalk associated with increased conductivity pattern density, APR tool 800 is further operative at 830 for RC estimation to estimate parasitic interconnections when interconnects are routed. Parameters, especially parasitic capacitance. The estimated parasitic capacitance is used in at least one operation of the wiring process, that is, at least one of full wiring, track distribution, or detailed routing to estimate the timing delay of various options of the wiring network. The timing delay estimate is then used to determine which routing option network to use and thus meets the predetermined performance goals.

In some embodiments, the APR tool 800 performs RC estimation and considers the air gaps that are subsequently inserted into the layout output by the APR tool 800, as described herein. The RC estimate includes operations 832, 834, and 836 as described in Figures 9A through 9E.

At operation 832, a candidate network for air gap insertion is selected among the plurality of networks of the IC. For example, Figure 9A illustrates an overview plan view of a portion 900A of an IC layout in accordance with some embodiments. The layout portion 900A includes nets 902, 904, 906, 908, and 910 configured on a routing grid having gridlines 912. The adjacent gridlines 912 are spaced apart from one another by an integer multiple of the spacing s, which is the minimum spacing between adjacent networks allowed by the design and/or manufacturing specifications of the IC. In the example architecture of Figure 9A, the distance between adjacent gridlines 912 is 2s. The net 904 is spaced apart from the nets 902, 906 by an interval s that is no greater than the air gap. The maximum interval of insertion. Thus, the air gap patterns 913, 915 can be inserted between the mesh 904 and the corresponding nets 902, 906, and the nets 902, 904, 906 can be identified as candidate nets that are inserted as air gaps. In at least one embodiment, the air gap patterns 913, 915 are not actually inserted until the APR tool 800 outputs the layout, and the air gap insertion process is performed as described in Figures 3 and 5. The webs 908, 910 are spaced apart from each other by 3 s, which is greater than the maximum spacing of the air gap insertion. Thus, no air gap pattern can be inserted between the nets 908, 910, and the nets 908, 910 are not recognized as candidate nets for air gap insertion. In some embodiments, the spacing s is the maximum spacing of the air gap insertion, that is, the air gap pattern can only be inserted between adjacent nets that are spaced apart from each other by s. In at least one embodiment, the spacing s is 0.08 microns. Judging the interval between adjacent networks based on the grid line 912 along which the network to be configured is to be configured or planned, and comparing with the maximum interval of air gap insertion, based on the comparison, judging the candidate network for air gap insertion . Other configurations for identifying the selected mesh after air gap insertion are within the scope of various embodiments.

At operation 834, various scalings of the candidate network are determined based on the length of the corresponding candidate network, and at operation 836, the capacitance of the candidate network is estimated based on the corresponding scaling. Scaling refers to the effect of the air gap on the capacitance of the corresponding candidate network. In some embodiments, the higher the scaling, the less the effect of the air gap on the capacitance of the corresponding candidate mesh. For example, FIG. 9B illustrates a diagram 900B for determining various scales in accordance with some embodiments. Figure 900B illustrates Figures 9C-9E, which are schematic plan views illustrating different portions 900C-900E of the resulting layout, in accordance with some embodiments.

In some embodiments, when the length of the candidate network is less than the first critical length, the scaling of the candidate network has a first scaling value. For example, as shown in FIG. 9B, when the length of the candidate network is less than the first critical length L1, the scaling of the candidate network has the first scaling value SR1. In at least one embodiment, the first scaling value SR1 is 1, which means that the air gap adjacent to the candidate network is not inserted, and the capacitance of the candidate network is not affected by the air gap. In at least one embodiment, the first critical length L1 is the smallest air gap insertable Net length. In at least one embodiment, L1 is 0.18754 microns. In the example architecture of FIG. 9C, since the mesh 922 is spaced apart from the adjacent mesh 923 by s, it is a candidate mesh into which the air gap is inserted. However, the length L of the mesh 922 is shorter than L1, and therefore, the airless gap pattern can be inserted adjacent to the mesh 922.

In some embodiments, when the length of the candidate network is not less than the first critical length and not greater than the second critical length, the scaling ratio of the candidate network increases as the corresponding length of the candidate network increases from the first critical length to the second critical length. Decreasing from the first scaling value to the second scaling value. For example, as shown in FIG. 9B, when the length of the candidate network is between the first critical length L1 and the second critical length L2, as the corresponding length of the candidate network increases, the scaling ratio of the candidate network is from the first scaling value SR1. Lower to the second scaling value SR2. In at least one embodiment, the second scaling value SR2 is 0.7, which means that when the air gap is inserted adjacent to the corresponding candidate network, the capacitance of the candidate network is reduced by 30%, that is, the air gap is not inserted. Corresponding to 70% of the capacitance of the candidate network. In at least one embodiment, the second critical length L2 is 6 microns. The specific values of SR1, SR2, L1 and L2 are merely examples. Other values are also within the scope of various embodiments.

In the example architecture of FIG. 9D, candidate networks 932, 934, 936 are of sufficient length such that air gap patterns 937, 939 can be interposed between candidate networks 932, 934 and nets 934, 936. However, the presence of vias 941, 943 for electrically coupling the candidate mesh 934 to other conductive patterns limits the effective length Lf of the insertable air gap patterns 937, 939 to the length L of the candidate nets 932, 934, 936. portion. The reason is that no air gap is formed in the regions 945, 947 surrounding the corresponding passages 941, 943, so that the possibility that the passages 941, 943 are located on the air gap cannot be reduced, for example, the possibility of misalignment during the manufacturing process cannot be reduced. The size of the regions 945, 947 is determined by the path limitation, and the spacing V between the path limiting system regions 945, 947 and the opposite edges of the corresponding vias 941, 943. In at least one embodiment, the V is 0.06 microns. Other values of V are also within the scope of various embodiments.

In Figure 9B, the scaling of the reduction in the length of the network between L1 and L2 The reaction pathway limits the effect on air gap insertion. When the length of the web is short, as shown in the example architecture of Figure 9D, the path limitation significantly limits the effective length L of the insertable air gap. Therefore, the amount of capacitance reduction that can be achieved by the insertion of the air gap is low, and the capacitance of the candidate network with the air gap insertion is close to the capacitance of the candidate network with no air gap insertion, which means that the scaling ratio is close to 1. As the length of the net increases, as shown in the example architecture of Figure 9E, the path restriction limits the effective length Lf of the insertable air gap to less than the length L of the candidate net. Therefore, the amount of capacitance reduction that can be achieved by the insertion of the air gap is increased, and the capacitance of the candidate mesh having the air gap insertion is lowered, which means that the scaling is lowered. In at least one embodiment, the scaling is fixed when the length of the net is long enough for the path limit to be ignored. For example, as shown in FIG. 9B, when the length of the candidate net is greater than the second critical length L2, the corresponding scaling has a second scaling value SR2.

The relationship between the length of the net and the scaling is only an example. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, the reduction in the scale of the web length between L1 and L2 is not linear, as shown in Figure 9B; in some embodiments, the reduction in scaling is non-linear or stepped.

Based on the determined scaling, the capacitance estimate of the candidate mesh with air gap insertion multiplies the corresponding scaling by the capacitance of the candidate mesh without air gap insertion. The estimated capacitance considering the air gap is used in the wiring operation as described herein. In one or more embodiments, the APR tool provides an optimized layout for subsequent air gap insertion as compared to other methods that do not account for air gaps during the routing phase. Thus, at least one embodiment maximizes or at least increases the performance benefits associated with air gap insertion.

In addition to the air gap considerations of the APR tool as described in FIG. 8 and/or the addition of the virtual mesh for increasing air gap coverage as described in FIGS. 5 and 6A through 6D, some embodiments consider air in subsequent design stages. Clearance, such as an air gap in an RC extraction operation.

10 illustrates at least one of the IC design process 1000 in accordance with some embodiments. Part of the functional flow chart.

At operation 1010, a netlist of the IC and an SDC file are provided. In at least one embodiment, the netlist and SDC file correspond to the output that produces the layout, as described in operation 810 of FIG.

At operation 1020, an original RC technical file is provided. An exemplary method for generating an RC technical file is described in U.S. Patent Application Publication No. 2009/007750, the entire disclosure of which is incorporated herein by reference. In at least one embodiment, the original RC technology file includes pre-stored parasitic capacitance and resistance of various original polygonal patterns. In at least one embodiment, the original RC technology file further includes a dielectric constant K for determining parasitic capacitance. When an air gap is inserted into the IC, the parasitic capacitance decreases. In at least one embodiment, the dielectric constant K is adjusted to simulate a parasitic capacitance reduction due to air gap insertion, as described herein. For example, the dielectric constant K is reduced to less than the actual dielectric constant of the dielectric material used to fabricate the IC and the parasitic capacitance occurs.

At operation 1030, the netlist and SDC file provided by operation 1010 and the original RC technology file provided at operation 1020 are used as input to the APR tool, which performs placement and routing operations to produce an IC layout, such as operation 120 of FIG. Said. In at least one embodiment, the APR tool 800 described herein is for placement and routing operations 1030.

At operation 1040, an air gap insertion process is performed to insert an air gap into the layout output by the APR tool to obtain a modified layout. In at least one embodiment, air gap insertion method 300 or virtual mesh and air gap insertion method 500 is performed at operation 1040.

At operation 1050, the modified layout output by the air gap insertion process of operation 1040 is RC extracted by an RC extraction tool. The RC extraction is performed to determine parasitic parameters in the modified layout of subsequent processing, as described in operation 150 of FIG. In at least one embodiment, the RC extraction of operation 1050 includes operations 1051 through 1059.

At operation 1051, based on RC extraction that does not consider air gaps, Static timing analysis (STA). In at least one embodiment, the RC extraction that does not consider air gaps extracts the parasitic resistance and capacitance from the modified layout while ignoring the interposed air gap. For example, the RC extraction tool divides the decorated layout from operation 1040 into blocks that contain the identifiable original polygon pattern defined by the original RC technology file provided at operation 1020. The RC extraction tool then extracts the parasitic resistance and capacitance of the modified layout by reading the corresponding pre-stored parasitic resistance and capacitance from the original RC technology file. Using the extracted parasitic resistance and capacitance to perform the STA, the time delay along the various signal paths in the IC is evaluated. In at least one embodiment, operation 1051 is performed by ignoring the intervening air gap and the complexity associated with the change in dielectric constant of the web having the interposed air gap, without the need to consider the air gap for modifying the layout. Time consuming RC extraction.

At operation 1052, at least one signal path for RC extraction with air gap considerations is identified based on a time delay along various signal paths derived from operation 1051. In at least one embodiment, the identified signal path is a critical signal path. In one example, the critical signal path is the signal path with the longest delay. In another example, the critical signal path is a signal path having a time delay that is near or above the timing limit. In some embodiments, more than one critical signal path is identified. For example, identify some of the most critical signal paths for RC extraction with air gap considerations. Other configurations of identifying signal paths for RC extraction with air gap considerations are also within the scope of various embodiments.

At operation 1053, for the signal path identified by operation 1052, an RC extraction with air gap considerations is performed. This RC extraction with air gap considerations refers to corner-based RC extraction. In at least one embodiment, the angle-based RC extraction is performed in a manner similar to the RC extraction described in operation 1051, with the difference being that the dielectric constant of the web having the interposed air gap is considered. Therefore, the angle-based RC extraction system provides a more accurate extraction parasitic parameter. In at least one embodiment, since the angle-based RC extraction covers corner examples corresponding to critical signal paths Thus, by performing angular-based RC extraction for one or more identified signal paths rather than other signal paths in the IC, processing time is reduced while ensuring correctness through the IC.

At operation 1054, two time delay values are obtained for each of the identified signal paths. Using the parasitic capacitance extracted by the angle-based RC extraction, a first time delay value, referred to herein as D _accurate , is used for the identified signal path. Using a RC extraction as described in operation 1051 without considering the parasitic capacitance extracted by the air gap, a second time delay value, referred to herein as D _corner , is used for the identified signal path. In at least one embodiment, D _corner is derived from the result of the STA of operation 1051.

At operation 1055, it is determined whether D _corner conforms to D _accurate . When the absolute value of the difference between D _corner percent and not greater than _D accurate X, D _corner are deemed to comply with Department _D accurate. In some embodiments, the X system is between 2% and 4%. In a lesser embodiment, X is 3%. D _corner so that the extent consistent with other _D accurate values X and / or configurations based on various embodiments.

At operation 1056, the response D _corner does not meet the D- _accuracy determination (NO at operation 1055), and the dielectric constant K in the original RC technology file is adjusted. In at least one embodiment, D _corner >D _accurate means that the parasitic capacitance extracted without considering the air gap is greater than the more accurate parasitic capacitance extracted by the angle-based RC extraction. In order to reduce the parasitic capacitance extracted by the unmeasured air gap to meet the parasitic capacitance extracted by the angle-based RC extraction, the dielectric constant in the original RC technical file is reduced, for example, by reducing it. In at least one embodiment, D _corner <D _accurate means that the parasitic capacitance extracted by the unmeasured air gap is less than the more accurate parasitic capacitance extracted by the angle-based RC extraction. In order to increase the parasitic capacitance extracted from the air gap that is not considered to conform to the parasitic capacitance extracted by the angle-based RC extraction, the dielectric constant K in the original RC technical file, such as the amplification dielectric constant K, is increased. In some embodiments, the signal path identifying the angle-based RC extraction and the adjustment of the dielectric constant K comprises a 1W1S signal path having a mesh having a minimum width (ie, 1 W) allowed by the IC specification and The minimum spacing (ie 1S) allowed by the IC specification from the adjacent network.

At operation 1057, the original RC technology file is updated with the dielectric constant K adjusted by operation 1056 to obtain a new RC technology file.

At operation 1058, the parasitic capacitance extracted without considering the air gap is updated with the adjusted dielectric constant K. For example, when the dielectric constant K is reduced in the adjustment of operation 1056, the parasitic capacitance is also reduced in accordance with the adjusted dielectric constant K. When the dielectric constant K is amplified in the adjustment of operation 1056, the parasitic capacitance is also amplified in accordance with the adjusted dielectric constant K. Perform STA, use the updated parasitic capacitance to recalculate the D _{corner of the} corresponding identification path. The process then returns to operation 1055 to determine if the recalculated D _corner meets D _accuracy . When D _corner recalculation not meet the _D accurate, the operation is repeated 1056, 1057 and 1058 to adjust the dielectric constant K.

At operation 1059, the response D _corner conforms to the D- _accuracy determination, corresponding to the dielectric constant K that matches D- _precision with D _corner , for other signal paths in the IC, used to adjust the parasitic capacitance extracted without considering the air gap. In some embodiments, when the dielectric constant K is reduced during the adjustment of operation 1056, the parasitic capacitance extracted by the other signal paths is also reduced according to the adjusted dielectric constant K. When the adjustment of the operation 1056 is to amplify the dielectric constant K, the parasitic capacitance extracted by the other signal paths is also amplified according to the adjusted dielectric constant K. The adjusted parasitic parameters are output for subsequent processing.

At operation 1060, the adjusted parasitic parameters are used for timing end IC layout. In at least one embodiment, the end of the sequence of operation 1060 corresponds to the end of the sequence described in operation 160 of FIG.

There are other ways to perform RC extraction of the IC and consider the air gap. When the isolation between adjacent conductive patterns is changed from the air gap to the dielectric material, the RC extraction is time consuming due to the change in the associated air gap and the dielectric constant. In addition, when the position of the air gap insertion is changed based on the analysis of the subsequent stage, the production is re-produced. A mask layer containing an air gap pattern is created and a time consuming RC extraction that takes into account the air gap is repeated for the IC. Therefore, design time and cost increase.

In contrast to other approaches, in accordance with some embodiments, the IC design process 1000 takes into account RC extraction of air gaps for one or more critical signal paths in the IC, rather than other paths. Thus, since the angle-based RC extraction covers angular examples corresponding to critical signal paths, processing time is reduced while ensuring correctness through the IC. In at least one embodiment, the turnaround time between the end of timing (eg, operation 1060) and the layout correction (eg, operation 1030 and/or operation 1040) is reduced compared to other methods. In at least one embodiment, RC extraction is performed without repeatedly producing a mask layer comprising an air gap pattern.

The above methods include example operations, but need not be performed in the order shown. Depending on the spirit and scope of the embodiments of the present disclosure, the operations may be added, replaced, changed, and/or eliminated as appropriate. Embodiments that combine different features and/or different embodiments are also within the scope of the disclosure, and are known to those of ordinary skill in the art after having the understanding of the disclosure.

11 is a block diagram illustrating a computer system 1100 in accordance with some embodiments. With one or more of computer system 1100 of FIG. 11, in some embodiments, one or more of the tools and/or engines and/or systems and/or operations described in FIGS. 1-7 are implemented. System 1100 includes at least one processor 1101, memory 1102, network interface (I/F) 1106, memory 1110, input/output (I/O) device communicatively coupled via bus 1104 or other interconnect communication mechanism 1108.

In some embodiments, memory 1102 includes random access memory (RAM) and/or other dynamic storage devices and/or read only memory (ROM) and/or other static storage devices coupled to bus bar 1104 for The data and/or instructions to be executed by the processor 1101 are stored, such as core 1114, user space 1116, portions of the core and/or user space, and components thereof. In some embodiments, the memory 1102 is also used to store temporary variables or other intermediate information during the execution of the instructions by the processor 1101.

In some embodiments, storage device 1110, such as a magnetic disk or optical disk, is coupled to busbar 1104 for storing data and/or instructions, such as core 1114, user space 1116, and the like. I/O device 1108 includes input devices, output devices, and/or combined input/output devices for causing a user to interact with system 1100. For example, the input device includes a keyboard, a keypad, a mouse, a trackball, a track pad, and/or a cursor direction key for communicating information and instructions with the processor 1101. For example, the output device includes a display, a printer, a voice synthesizer, etc. for communicating information with the user.

In some embodiments, the functionality and/or engine and/or system of one or more operations and/or tools described in FIGS. 1-7 is implemented by processor 1101, which is programmed for Do this and/or function. In some embodiments, processor 1101 is hardware of a particular architecture (eg, one or more special application integrated circuits (ASICs)). One or more memories 1102, I/F 1106, storage device 1110, I/O device 1108, hardware component 1118, and bus bar 1104 are operable to receive instructions, data, and designs for processing by processor 1101. Limits, design rules, netlists, layouts, models, and/or other parameters.

In some embodiments, the operations and/or functions are implemented as functions stored in a program stored in a non-transitory computer readable medium. In at least one embodiment, the operations and/or functions are implemented as functions of a program stored in memory 1102, such as a set of executable instructions. In at least one embodiment, the instructions stored in memory 1102 include functionality for implementing at least one of the process flows of FIGS. 1, 3, 5, 7, 8, and 10. Examples of non-transitory computer readable storage media include, but are not limited to, external/removable and/or internal/built-in storage or memory units, such as one or more optical discs such as DVDs, such as hard disk drives. For example, semiconductor memory such as ROM, RAM, memory card, and the like.

In some embodiments, an air gap is inserted in the IC layout based on the length of the mesh in the IC and/or other characteristics or cost functions. Thus, one or more embodiments Optimize the parasitic capacitance reduction effect due to air gap insertion.

In some embodiments, a virtual mesh is inserted in the IC layout to increase air gap coverage in areas where air gaps are not insertable. In some embodiments, the virtual mesh and air gap are inserted according to the length of the network in the IC and/or other characteristics or cost functions. Thus, in one or more embodiments, the parasitic capacitance reduction effect due to air gap insertion is optimized.

In some embodiments, during the APR phase, the air gap is considered for RC estimation even before the air gap is actually inserted into the layout. Thus, the APR stage outputs an optimized layout for subsequent air gap insertion that maximizes or at least increases the performance benefits associated with air gap insertion.

In some embodiments, for the critical signal path of the IC, the air gap is considered for angular-based RC extraction, while for other, less critical signal paths of the IC, RC extraction is not considered for air gaps. Therefore, by using the coverage angle example, the design turnaround time is reduced while ensuring correctness.

In some embodiments, the method performed at least in part by the processor includes performing an air gap insertion process. The air gap insertion process includes a plurality of nets that sequentially classify the integrated circuit layout, and inserts the air gap pattern adjacent to the plurality of nets according to the sorting order of the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The decorated layout includes a plurality of nets and an interposed air gap pattern.

In some embodiments, the apparatus includes at least one processor for performing the following operations. The virtual network and air gap insertion process includes a plurality of networks that sequentially classify the layout of the integrated circuit, and inserts the virtual network and the air gap pattern adjacent to the plurality of nets according to the sorting order of the plurality of nets. Produce a modified layout of the integrated circuit. The decorated layout includes a plurality of nets, an inserted virtual net, and an inserted air gap pattern.

In some embodiments, a computer program product includes a non-transitory computer readable medium, including instructions therein, when executed by at least one processor, Cause at least one processor to perform the following operations. In a plurality of networks of integrated circuits, candidate networks for air gap insertion are selected. The various scaling ratios of the candidate networks are determined based on the length of the corresponding candidate network. The capacitance of the candidate network is estimated based on the corresponding scaling of the candidate network. Based on the estimated capacitance of the candidate network, full wiring, track distribution, or detailed routing is performed to generate a layout of the integrated circuit.

The foregoing description summarizes the features of some embodiments, and those skilled in the art can understand the aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the present application. It should be understood by those skilled in the art that the present invention is not limited to the spirit and scope of the disclosure, and various changes, substitutions and changes can be made without departing from the spirit and scope of the disclosure.

110‧‧‧IC design

120‧‧‧APR

130‧‧‧virtual insertion

140‧‧‧Air gap insertion

150‧‧‧RC extraction

160‧‧‧End of sequence

170‧‧‧Manufacture

Claims (10)

A method, the method being performed at least in part by a processor, the method comprising: performing an air gap insertion process, the air gap insertion process comprising: sequentially sorting a plurality of nets arranged in one of the integrated circuits; a sorting order of the equal nets, inserting an air gap pattern adjacent to the nets; and a modified layout for producing the integrated circuits, the modified layout including the nets and the inserted air gap pattern. The method of claim 1, further comprising: after inserting at least one air gap pattern adjacent to a net in the nets, determining whether the air gap patterns that have been inserted satisfy a limit; responding to the already inserted The air gap pattern does not satisfy the determination of the limit, removing the inserted at least one air gap pattern, and performing the generation to the modified layout; and determining, in accordance with the classification order, that the air gap pattern that has been inserted satisfies the limit At least one other air gap pattern is inserted to be adjacent to the next one of the nets, and back to the determination. The method of claim 1, wherein the network comprises a signal network and at least one virtual network, and the method further comprises inserting the at least one virtual network adjacent to the at least one signal network prior to the air gap insertion process . The method of claim 1, further comprising: checking whether the integrated circuit satisfies a timing specification; and responding to the determination that the integrated circuit does not satisfy the timing specification, Identifying a failed signal path in the integrated circuit and performing the air gap insertion process for the network included in the failed signal path. An apparatus comprising: at least one processor for performing: a virtual network and an air gap insertion process, the virtual network and air gap insertion process comprising: sequentially sorting a plurality of networks of a layout of an integrated circuit; and according to the network a sorting order, inserting a virtual mesh and air gap pattern adjacent to the nets; and a modified layout for generating the integrated circuit, the modified layout including the nets, the inserted virtual nets, and the inserted Air gap pattern. The device of claim 5, wherein the inserting system comprises: inserting at least one virtual network to be adjacent to a network in the network; inserting at least one between the inserted at least one virtual network and the corresponding network An air gap pattern; and at least another air gap pattern is interposed between the corresponding net and an adjacent one of the nets. The device of claim 5, wherein the virtual network and air gap insertion process further comprises: inserting at least one virtual network to be adjacent to a network in the networks and corresponding to the inserted at least one virtual network After inserting at least one air gap pattern between the nets, determining whether the air gap pattern that has been inserted satisfies a limit; and removing the inserted at least one air gap pattern in response to the determination that the air gap pattern that has been inserted does not satisfy the limit, And performing the generation of the modified layout; and determining that the air gap pattern that has been inserted satisfies the limit, Inserting at least one other virtual network adjacent to the next one of the nets according to the sorting order, inserting at least another air gap pattern between the at least one other virtual net and the next net, and returning to The judgment. The device of claim 5, wherein the virtual network and air gap insertion process further comprises: inserting at least one virtual network to be adjacent to a network in the networks and corresponding to the inserted at least one virtual network After inserting at least one air gap pattern between the nets, determining whether the air gap pattern that has been inserted satisfies a limit; in response to the determination that the air gap pattern that has been inserted does not satisfy the limit, removing the inserted at least one virtual net, moving In addition to the insertion of at least one air gap pattern, and the generation to the modified layout; and in response to the determination that the air gap pattern that has been inserted satisfies the limit, in accordance with the sorting order, inserting at least another virtual network to The next network in the network is adjacent, at least another air gap pattern is inserted between the at least one other virtual network and the next network, and the determination is returned. A computer program product comprising a non-transitory computer readable medium, comprising instructions therein, when executed by at least one processor, causing the at least one processor to execute: a plurality of networks in an integrated circuit Selecting candidate networks for air gap insertion; determining various scaling ratios of the candidate networks based on the lengths of the corresponding candidate networks Example: estimating capacitances of the candidate networks based on corresponding scaling ratios of the candidate networks; and performing at least one of full wiring, track distribution, and detailed routing based on the estimated capacitance of the candidate networks, generating the integrated body A layout of the circuit. The computer program product of claim 9, wherein when the instructions are executed by the at least one processor, the instructions further cause the at least one processor to execute: the generated layout of the integrated circuit Inserting a virtual network and an air gap pattern; identifying a signal path in the integrated circuit, the signal path including at least one of the air gap patterns; extracting based on the at least one air gap pattern in the signal path Calculating a first time delay of the signal path by calculating at least one capacitance of the signal path; calculating a second time delay of the signal path, the calculating is based on extracting the at least one air gap pattern in the signal path At least one capacitance of the signal path, and an adjustable dielectric constant; adjusting the dielectric constant such that the second time delay matches the first time delay; and matching the first time delay based on the second time delay The adjusted dielectric constant adjusts the capacitance of other signal paths in the integrated circuit.