CN102508981B - Method and device for accelerating emulation of CMP (Chemical Mechanical Polishing) - Google Patents
Method and device for accelerating emulation of CMP (Chemical Mechanical Polishing) Download PDFInfo
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Abstract
The invention discloses a method and a device for accelerating the emulation of a CMP (Chemical Mechanical Polishing). The method for accelerating the emulation of the CMP comprises the following steps of: firstly, dividing a physical layout into a plurality of areas; secondly, dividing graphs in the areas into different geometry isomorphic sequences by using a geometry isomorphism; thirdly, selecting the graph in one area of the geometry isomorphic sequence for carrying out CMP emulation; fourthly, multiplexing the graphs in other areas in the geometry isomorphic sequences according to emulation data. According to the method and the device disclosed by the invention, through the division of the physical layout, the geometry isomorphism of the graphs in the areas, the CMP emulation in the areas and the multiplexing of CMP emulation data in the areas, the emulation speed of the CMP of a whole chip is increased and the emulation time of the CMP of the whole chip is shortened; and a CMP emulation task is merged in a graph isomorphic way; and on the basis of the graph isomorphism, primary calculation for the same CMP emulation task of the physical layout is carried out and the emulation result of the CMP is multiplexed, and thereby the emulation speed of the CMP of the whole chip is increased by reducing the quantity of the CMP emulation tasks.
Description
Technical field
The present invention relates to integrated circuit (IC) design automatic field, relate in particular to a kind of method and apparatus of the CMP of acceleration emulation.
Background technology
Copper need to be at etching interconnection channel and through hole after oxidation material deposit as the manufacturing process of interconnection line; Then be deposited with the thin barrier metal layer that is beneficial to submonolayer as seed layer; Copper is deposited to interconnection channel and through hole by the method for next, electroplating (ECP) by galvanochemistry; Finally, remove the unnecessary copper outside groove and through hole, produce interconnection graph.
Chemically mechanical polishing (CMP) is the technology of removing unnecessary copper and realizing silicon chip surface planarization.Therefore, being used as in the integrated circuit fabrication process of interconnection line at metallic copper, is one of important step of technological process for the CMP of silicon chip surface planarization, but has introduced extra stray capacitance.ECP and CMP technique are very responsive to physical layout figure, because copper deposit is relevant with domain figure with removal, graphic change can cause the problems such as dish-like depression, dielectric corrosion and metal thickness fluctuation, further causes interconnect resistance, capacitance fluctuations, even follow-up lithographic issues.In deep submicron process, the requirement of the depth of focus (DOF) becomes more strict, and chip surface fluctuation makes the shape of copper interconnecting line smudgy.
In order to solve the problems such as dish-like depression, dielectric corrosion and metal thickness fluctuation, integrated circuit (IC) design personnel and manufacturer are mute metal filled by inserting, and make pattern density homogenising, thereby reduce dish-like depression and dielectric corrosion.
CMP emulation is the effective ways of prediction chip surface thickness evenness, before actual manufacture, can predict dish-like depression, dielectric corrosion and metal thickness fluctuation based on ECP and CMP model.
Chip design presents system level chip (SOC) and network level chip (NOC) trend in scale, on sheet, device count reaches hundred million grades, 1,000,000,000 grades, 10,000,000,000 magnitudes even, the quantity of metal interconnecting wires is more at the more than several times of number of devices, and its corresponding physical layout data reaches tens Gb(10
9bit), even hundreds of Gb, on the physical layout of scale like this, carrying out CMP emulation is a very time taking task, in physical Design-CMP emulation-correction-emulation again-revise again in such iterative process, the speed of CMP emulation is one of key factor affecting the integrated circuit (IC) design cycle, traditional serial and parallel C MP emulation need to be made detailed complex simulation to each tiny area of integrated circuit diagram and calculate, and therefore speed is slow, has restricted the raising of design efficiency.
Summary of the invention
For the above-mentioned problems in the prior art, the invention provides a kind of method and apparatus of the CMP of acceleration emulation.
A kind of method that the invention provides the CMP of acceleration emulation, comprising:
Step 1, is divided into some regions by physical layout;
Step 2, utilizes how much isomorphisms that the figure in described some regions is divided into different geometry isomorphism sequences;
Step 3, chooses how much figures in a region in isomorphism sequence and carries out CMP emulation;
Step 4, carries out multiplexing according to emulated data to the figure in other regions in how much isomorphism sequences.
In one example, step 1 comprises:
Step 10, is placed on figure identical metal level number in same set;
Step 11, is divided into the figure in same set the region that Nrow is capable and Ncol is listed as, and Nrow and Ncol are positive integer; The grid of least unit is inner region;
Step 12, expands the grid obtaining to the mask pattern closing on as exterior domain outward by inner region.
In one example, step 2 comprises:
Step 20, carries out coordinate transform sequence to the figure in each exterior domain;
Step 21, carries out geometry isomorphism with constructive geometry isomorphism sequence to the figure in each exterior domain;
Step 22, treats simulating area sequence with the graphical configuration in first exterior domain in how much isomorphism sequences.
In one example, step 4 comprises: to each how much isomorphism sequence, according to the geometric transformation relation between the figure in other regions in the figure of first exterior domain in how much isomorphism sequences and how much isomorphism sequences, the simulation result of the figure of multiplexing first exterior domain; Geometric transformation comprises that rotational transform, rotational symmetry conversion and translation change.
In one example, in step 20, according to the coordinate figure after coordinate transform, figure is sorted.
In one example, in step 21, how much isomorphisms comprise direct how much isomorphisms and indirect how much isomorphisms; Be direct how much isomorphisms if the coordinate of two figures is identical, if the coordinate of two figures identical through the coordinate after mirror image and/or rotation be geometry isomorphisms indirectly.
In one example, in step 3, take the figure in exterior domain as simulation objectives, but only generate the CMP simulation result of the figure in inner region;
In step 4, the CMP simulation result of the figure in multiplexing inner region.
The device that the invention provides a kind of CMP of acceleration emulation, comprising:
Physical layout region division unit, for being divided into physical layout in some regions;
Descriptive geometry isomorphism detecting unit, for utilizing how much isomorphisms that the figure in described some regions is divided into different geometry isomorphism sequences;
CMP simulation unit, carries out CMP emulation for the figure of choosing in a region of how much isomorphism sequences;
Multiplexing Unit, for carrying out multiplexing according to emulated data to the figure in other regions of how much isomorphism sequences.
The present invention is multiplexing by the CMP emulation in descriptive geometry isomorphism, region in the division of physical layout region, region, region CMP emulated data, to improve the CMP simulation velocity to full chip, shortens the CMP simulation time to full chip; Merge CMP artificial tasks in figure isomorphism mode, based on figure isomorphism, identical physical layout CMP artificial tasks is once calculated, multiplexing its CMP simulation result, thus improve the CMP simulation velocity to full chip by reducing CMP artificial tasks quantity.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is described in further detail, wherein:
Fig. 1 is the method flow diagram that accelerates CMP emulation;
Fig. 2 is that process flow diagram is divided in physical layout region;
Fig. 3 A divides schematic diagram according to figure geometric position information planar;
Fig. 3 B is that adjustment schematic diagram is divided in region;
Fig. 4 is descriptive geometry overhaul flow chart in region;
Fig. 5 is region CMP simulation flow figure;
Fig. 6 is the multiplexing schematic diagram of region CMP Simulation result data;
Fig. 7 is the device schematic diagram that accelerates CMP emulation.
Embodiment
In integrated circuit physical Design, between regional area, design configuration has very large homogeny, this homogeny has determined CMP computation process between regional area and the homogeny of result of calculation, the multiplexing of result of calculation can be reduced complicated simulation calculation task effectively, improves chip entirety CMP simulation velocity under the condition of not sacrificing simulation accuracy.The present invention is multiplexing by the CMP emulation in descriptive geometry isomorphism, region in the division of physical layout region, region, region CMP emulated data, zones of different is carried out to CMP emulation to improve the CMP simulation velocity to full chip with parallel mode, shorten the CMP simulation time to full chip; Merge CMP artificial tasks in figure isomorphism mode, based on figure isomorphism, identical physical layout CMP artificial tasks is once calculated, multiplexing its CMP simulation result, thus improve the CMP simulation velocity to full chip by reducing CMP artificial tasks quantity.
A kind of method that the invention provides the CMP of acceleration emulation, mainly comprises: physical layout region is divided, descriptive geometry isomorphism in region, the CMP emulation in region and region CMP emulated data multiplexing.
Referring to Fig. 1, the method for the acceleration CMP emulation that the embodiment of the present invention provides comprises:
Step S101, is divided into some regions by physical layout;
Step S102, utilizes how much isomorphisms that the figure in described some regions is divided into different geometry isomorphism sequences;
Step S103, chooses how much figures in a region in isomorphism sequence and carries out CMP emulation;
Step S104, carries out multiplexing according to emulated data to the figure in other regions in how much isomorphism sequences.
As shown in Figure 2, step S101, mainly comprises:
Step S10101, level is divided;
Step S10102, region is slightly divided;
Step S10103, region is divided and is adjusted.
Wherein, it is according to the metal level in integrated circuit fabrication process that step S10101 level is divided, as the first metal layer M1 to the 12 metal level M12 divide, the division principle of this step is traversal physical layout data, retain metallic pattern data, within the figure that metal level number is identical is placed on same set, and within the different figure of metal level number is placed on different set;
Step S10102 slightly divides in region: to data metal layer, be the metallic pattern data in same set, divide according to figure geometric position information planar: by capable whole metal level division Nrow and Ncol row, form Nrow × Ncol lattice point region, as shown in Figure 3A;
Step S10103 region is divided and is adjusted: as shown in Figure 3 B, with corresponding region A, the B of Nrow × Ncol lattice point obtained in the previous step as a reference, region frame 301 is outwards extended, physical layout mask pattern Width is cut within part is included in the new frame 302 of former region frame after outwards extending, and the region that frame covers is inner region 303; Within continuation extension frame is all in frame near the mask pattern part of directly closing on interior frame, the region that this frame covers is exterior domain 304.Metallic pattern in set belongs to certain lattice point area part, just this part metals figure is inserted to metallic pattern subset corresponding to corresponding lattice point region.
Referring to Fig. 4, in step S102 region, descriptive geometry detects and mainly comprises:
Step S10201, region initial point determine;
Step S10202, the coordinate transform of graphical dots in region;
Step S10203, the sequence of figure in region;
Step S10204, descriptive geometry isomorphism in region;
Step S10205, structure realm isomorphism sequence, records the geometric transformation relation between isomorphism region;
Step S10206, treats simulating area sequence with first areal structure in each region isomorphism sequence.
Wherein, determining of step S10201 region initial point: the metallic pattern in traversal lattice point region, minimum X coordinate figure xmin and the minimum Y coordinate figure ymin of searching figure coordinate point, the initial point with (xmin, ymin) as this region;
The coordinate transform of graphical dots in step S10202 region: with (xmin, ymin) as the initial point in this region, metallic pattern data in lattice point region are done to relative position conversion, newly that coordinate figure is (xnew=xold – xmin, ynew=yold – ymin), xold and yold are former coordinate figure, record coversion T1;
The sequence of figure in step S10203 region: determine the minimum X coordinate figure order sequence from small to large of each metallic pattern according to the new coordinate figure of metallic pattern in lattice point region, the metallic pattern identical to minimum X value sorts according to minimum Y coordinate figure order from small to large, to minimum X coordinate figure and minimum Y coordinate figure all identical metallic pattern according to the order sequence from small to large of inferior minimum X coordinate figure, to minimum X coordinate figure, minimum Y coordinate figure and time minimum X coordinate figure all identical metallic pattern according to the order sequence from small to large of inferior minimum Y coordinate figure, by that analogy, until the order of the whole metallic patterns in lattice point region is completely definite,
How much isomorphisms between step S10204 region: be divided into direct how much isomorphisms and conversion geometry isomorphism afterwards, if the metallic pattern in two lattice point regions after the step S10203 metallic pattern according to the order Corresponding matching being ranked (coordinate figure of corresponding geometric point is identical), be direct how much isomorphisms, and the coordinate transform of mating between posting field between figure is related to the mapping relations between T2 and coupling figure;
To two regions of direct how much isomorphism failures, geometry mirror image and rotational transform are carried out in a rear region:
MNR90,MNR180,MNR270,MXR0,MXR90,MXR180，
MXR270，MYR0，MYR90，MYR180，MYR270，
Wherein MN indicates without mirror image, and MX represents X-axis mirror image, and MY represents Y-axis mirror image, and R0 represents to be rotated counterclockwise 0 degree, and R90 represents to be rotated counterclockwise 90 degree, and R180 represents to be rotated counterclockwise 180 degree, and R270 represents to be rotated counterclockwise 270 degree.And to this region execution step S10301, step S10302, step S10303, then judge conversion region and whether directly isomorphism of last lattice region afterwards, if so, original two regions are how much isomorphisms indirectly, and record coversion is related to the mapping relations between T3 and coupling figure;
Step S10205 structure realm isomorphism sequence: the region of how much isomorphisms is placed in to same isomorphism list, the region electricity not region of isomorphism is placed in zones of different list, thereby constructs the isomorphism list of some regions and the geometric transformation of recording between isomorphism region is related to T2/T3;
Step S10206 treats simulating area sequence with first areal structure in each region isomorphism sequence: for the numerous regions in an isomorphism zone list, only need one of them region to carry out numerous and diverse, detailed simulation calculation, in this list, the filling in other region can utilize detailed result of calculation above and assist with simple geometric transformation, therefore only treat simulating area sequence with first areal structure in each region isomorphism sequence in order to simplify simulation calculation, to detailed simulation calculation is carried out in these regions.
Pay particular attention to, step S102 is take the whole physical layout mask patterns in exterior domain as object.
Referring to Fig. 5, the CMP emulation of step S103 region, mainly comprises:
Step 10301, emulated data is extracted;
Step 10302, ECP emulation;
Step 10303, CMP emulation.
Wherein, step 10301 emulated data is extracted: extract in region in physical layout the width of interconnection line and copper density as the parameter of ECP and CMP process modeling;
Step 10302 ECP emulation: the variation in thickness of copper is calculated in ECP emulation based on ECP model, ECP model mainly uses live width and two parameters of distance between centers of tracks;
Step 10303 CMP emulation: CMP emulation is carried out based on CMP model, on each simulation time point, global simulation is calculated and local simulation calculation hockets.Global simulation is calculated the pressure distribution of each cellular, and each cellular has two height values, i.e. upper level and lower surface height; Local emulation is according to the removal speed on the upper and lower surface of calculation of pressure distribution of previous calculations, and the removal speed of each cellular that then local emulation obtains based on previous calculations is upgraded the height value on upper and lower surface.
What pay particular attention to is, step S103 is take the whole physical layout mask patterns in " exterior domain " as simulation objectives, but finally only generate the CMP simulation result of the whole physical layout mask patterns in " inner region ", because the CMP emulation of the physical layout mask pattern in " exterior domain " except " inner region " is also subject to the impact of physical layout mask pattern outside " exterior domain ", therefore only generate the CMP simulation result of the whole physical layout mask patterns in " inner region ".
Referring to Fig. 6, step S104 region CMP Simulation result data multiplexing, be applied to each region isomorphism sequence, since the 2nd region, be related to T2/T3 according to the geometric transformation in first region in this region and sequence, the simulation result data in multiplexing first region, thus the CMP simulation figure in this region obtained.No further details to be given herein in concrete geometric transformation.According to the evolution relation between first area and current region, the figure that the emulated data in first region is provided carries out the geometric transformation of following steps:
Step 10401, is rotated conversion according to the R0/R90/R180/R270 in T3;
Step 10402, carries out rotational symmetry conversion according to the MN/MX/MY in T3;
Step 10403, carries out translation variation according to the lower left corner coordinate figure of T1 and T1 '.
Wherein,
R0: without spin;
R90: 90-degree rotation;
R180: Rotate 180 degree;
R270: rotation 270 degree
MN: without mirror image
MX:X axle mirror image
MY:Y axle mirror image.
What pay particular attention to is, step S104 is the CMP simulation result of the whole physical layout mask patterns in multiplexing " inner region " only, because the CMP emulation of the physical layout mask pattern outside " inner region " is also subject to the impact of physical layout mask pattern outside " exterior domain ".
The invention provides a kind of device that accelerates CMP emulation based on region geometry isomorphism, this device comprises:
Physical layout region division unit, for physical layout is carried out to region division, is divided into hundreds of even hundreds thousand of regions;
Descriptive geometry isomorphism unit in region, for utilizing how much isomorphisms that the figure in described some regions is divided into different geometry isomorphism sequences;
CMP simulation unit in region, carries out CMP emulation for the figure of choosing in a region of how much isomorphism sequences;
The Multiplexing Unit of region CMP Simulation result data, for carrying out multiplexing according to emulated data to the figure in other regions of how much isomorphism sequences; CMP emulated data in multiplexing appointed area, according to the geometric transformation relation between this region, carries out following geometric transformation to it, obtains graph data after the CMP emulation in this region.
Referring to Fig. 7, the invention process provides, and a kind of device that accelerates CMP emulation based on region geometry isomorphism comprises: the Multiplexing Unit U104 of CMP simulation unit U103 and region CMP Simulation result data in descriptive geometry isomorphism detecting unit U102, region in physical layout region division unit U101, region.
The embodiment of the present invention is in the time accelerating CMP emulation based on region geometry isomorphism, and physical layout region division unit U101, for physical layout is carried out to region division, is divided into hundreds of even hundreds thousand of regions; Whether geometrically descriptive geometry isomorphism detecting unit U102 in region, for the isomorphism of its enclose pattern between judging area; CMP simulation unit U103 in region, for the physical geometry figure in region being carried out to CMP emulation with CMP model, obtains CMP actual physics figure afterwards; The Multiplexing Unit U104 of region CMP Simulation result data, for the CMP Simulation result data in multiplexing appointed area, according to the geometric transformation relation between this region, carries out following geometric transformation to it, obtains the actual physics figure after the CMP in this region.
The foregoing is only the preferred embodiment of the present invention, but protection domain of the present invention is not limited to this.Any those skilled in the art, in technical scope disclosed by the invention, all can carry out suitable change or variation to it, and this change or change all should be encompassed in protection scope of the present invention within.
Claims (5)
1. a method of accelerating CMP emulation, is characterized in that, comprising:
Step 1, is divided into some regions by physical layout;
Step 2, utilizes how much isomorphisms that the figure in described some regions is divided into different geometry isomorphism sequences; Described step 2 comprises: step 20, the figure in each exterior domain is carried out to coordinate transform sequence; Step 21, carries out geometry isomorphism with constructive geometry isomorphism sequence to the figure in each exterior domain; Step 22, treats simulating area sequence with the graphical configuration in first exterior domain in how much isomorphism sequences;
Step 3, chooses how much figures in a region in isomorphism sequence and carries out CMP emulation;
Step 4, carries out multiplexing according to emulated data to the figure in other regions in how much isomorphism sequences; Described step 1 comprises:
Step 10, is placed on figure identical metal level number in same set;
Step 11, is divided into the figure in same set the region that Nrow is capable and Ncol is listed as, and Nrow and Ncol are positive integer; The grid of least unit is inner region;
Step 12, expands the grid obtaining to the mask pattern closing on as exterior domain outward by inner region.
2. the method for acceleration CMP as claimed in claim 1 emulation, it is characterized in that, step 4 comprises: to each how much isomorphism sequence, according to the geometric transformation relation between the figure in other regions in the figure of first exterior domain in how much isomorphism sequences and how much isomorphism sequences, the simulation result of the figure of multiplexing first exterior domain; Geometric transformation comprises that rotational transform, rotational symmetry conversion and translation change.
3. the method for acceleration CMP as claimed in claim 1 emulation, is characterized in that, in step 20, according to the coordinate figure after coordinate transform, figure is sorted.
4. the method for acceleration CMP as claimed in claim 3 emulation, is characterized in that, in step 21, how much isomorphisms comprise direct how much isomorphisms and indirect how much isomorphisms; Be direct how much isomorphisms if the coordinate of two figures is identical, if the coordinate of two figures identical through the coordinate after mirror image and/or rotation be geometry isomorphisms indirectly.
5. the method for acceleration as claimed in claim 1 CMP emulation, is characterized in that, in step 3, take the figure in exterior domain as simulation objectives, but only generates the CMP simulation result of the figure in inner region;
In step 4, the CMP simulation result of the figure in multiplexing inner region.
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| CN103020384B (en) * | 2012-12-27 | 2015-03-04 | 中国科学院微电子研究所 | Chemical reaction kinetic simulation method of aluminum gate CMP (Chemical Mechanical Polishing) and optimization method of layout design |
| CN103559364B (en) * | 2013-11-13 | 2016-09-14 | 中国科学院微电子研究所 | Extract method and the CMP emulation mode of the layout patterns feature of chip layout |
| CN104123428B (en) * | 2014-08-14 | 2017-08-11 | 中国科学院微电子研究所 | CMP emulation mode and its analogue system |
| CN106815386B (en) * | 2015-12-02 | 2020-06-16 | 北京华大九天软件有限公司 | Array layout generation method for full-panel layout resistance-capacitance extraction |
| CN107291966B (en) * | 2016-04-11 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for chemical mechanical polishing simulation |
| CN107346350B (en) * | 2016-05-06 | 2020-08-28 | 中国科学院微电子研究所 | Distribution method, device and cluster system for integrated circuit layout data processing tasks |
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