JP2004157627A - Layout/wiring program and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout/wiring program and a manufacturing method of a semiconductor device that enable arbitrary connection correction after chip manufacture using a FIB device by forming desired wiring layers in all nets. <P>SOLUTION: The layout/wiring program has a wiring cell adding function of adding on a net a float wiring cell 11 having a plurality of connection pins 12 and 13 and an internal net 14 interconnecting the connection pins to thereby interconnect an output pin and an input pin via the float wiring cell 11. The layout/routing program can optimally lay out float wiring cells 11 assigned desired wiring layers to thereby form desired wiring layers in all nets. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a placement and routing program in semiconductor device design and a method of manufacturing a semiconductor device, and more particularly to assigning a specified wiring layer to a part of a specified wiring in a multilayer wiring process.
[0002]
[Prior art]
In the development of semiconductor integrated circuit devices, a placement and routing program using a gate-level cell library or an IP library for each functional block, except for a large-capacity general-purpose memory and some special devices that frequently use analog elements, has been developed. Used.
[0003]
FIG. 5 is a flowchart showing an outline of a conventional development process. The figure shows the design process after the specification is determined. The conventional development process is roughly divided into a design process 101, a manufacturing process 102, and an evaluation correction process 103.
[0004]
The design process 101 is divided into a logic design step 104 and a layout design step 105. First, in a logic design step 104, a stem design and a circuit design are performed according to the determined specification, and a net list is created. In the circuit design, a cell library or an IP library prepared in advance is used.
[0005]
Next, in a layout design step 105, a specific chip layout is created using the netlist and the library by the placement and routing program.
[0006]
The layout design step 105 includes a cell arrangement step 106, a schematic wiring step 107, an ECO step 108, a redundant cell arrangement step 109, and a detailed wiring step 110.
[0007]
In the cell arranging step 106, the gate level cell and the IP cell for each function block in the netlist are arranged in the areas determined at the time of designing the system. Here, “arranging” means determining the planar position of each cell on a chip based on the layout information of the cell in the library.
[0008]
In the general routing step 107, a wiring route between the pins of the arranged cells is globally determined based on the connection information in the netlist, and the result is added to the netlist as general wiring information. A pin corresponds to an input / output terminal of each cell in a logical design, and corresponds to a contact in an input / output portion of each cell layout or a small pattern of a wiring layer on the contact in a layout. At this stage, wiring grids indicating the types of wiring layers to be allocated to the respective wirings and the detailed spatial paths have not yet been allocated.
[0009]
In the ECO step 108, first, a timing-driven simulation is performed based on the obtained schematic wiring information to obtain a delay time for each net. The net is a concept in a logical design indicating a connection relationship between pins, and corresponds to each wiring connecting cells in a layout.
[0010]
Next, based on the result, the circuit is corrected so as to satisfy the specification, and the result is fed back to the netlist.
[0011]
In the redundant cell placement step 109, gate-level cells and their constituent elements are placed in empty areas on the chip in order to cope with design changes that may be made thereafter.
[0012]
In the detailed wiring step 110, the type of wiring layer is assigned to each net based on the schematic wiring information and the design rule on the layout, and the wiring grid position of the detailed route is determined. As a result, the positions of all cells and wirings on the chip are determined, and layout data of the entire chip can be created.
[0013]
When the design process 101 is completed, a chip of the semiconductor device is manufactured in a manufacturing process 102 based on the layout data. The manufacturing process 102 roughly includes a mask making step 111 and a chip manufacturing step 112.
[0014]
In a mask creation step 111, a mask used for each PEP at the time of manufacturing is created based on the entire layout data.
[0015]
In the chip manufacturing step 112, necessary circuit elements and wiring are formed on the wafer using the PEP technique.
[0016]
When the chip is completed in this way, the evaluation and correction process 103 evaluates the specification and, if possible, makes necessary corrections. In the evaluation step 113, the initial characteristics such as the circuit operation of the chip, the resistance to the use environment such as temperature and humidity, the power supply voltage, and the reliability against long-term aging due to the accelerated test are inspected in detail based on the specifications.
[0017]
Based on this result, it is determined in an evaluation determination step 114 whether or not the degree of completion of development is at a level that enables mass production and shipment as a product. If the specifications are completely satisfied and the degree of completion is determined to be sufficient (OK), the development of this product is terminated. If it is determined that there is a problem (NG), the process proceeds to analysis step 115, where a failure analysis for specifying the cause is performed.
[0018]
If the cause is specified and the circuit needs to be corrected as a solution, it is determined in FIB determination step 116 whether processing by the FIB device is possible or whether the processing solves the problem. If it is determined that the problem can be solved by the processing (OK), the necessary correction is made in the FIB processing step 117, and it is evaluated again in the evaluation step 113 whether the problem has been solved or not.
[0019]
If the processing by the FIB apparatus is impossible (NG), the necessary corrections are made to the layout data, and the process returns to the mask making step 111 to repeat the mask making and chip manufacturing.
[0020]
The process return to the mask creation step 111 is different from the process return to the evaluation step 113 by FIB processing, and a time loss of at least one month is required until a corrected chip is obtained, or several months depending on the correction content. . In addition, a cost for a correction mask and an additional wafer is required.
[0021]
With the recent advancement of CAD tools, especially simulation tools, unless there is a change in specifications or a process change due to unexpected trouble in manufacturing, there are almost no circuit modifications that can not be handled by using redundant cells and connection modification by FIB processing. Is coming. Therefore, whether the wiring connection can be changed by the FIB device greatly affects the development period and cost.
[0022]
On the other hand, since multi-layer wiring has become mainstream as a process technology, the probability that a net is formed only by lower-layer wiring covered by upper-layer wiring has increased. As described above, the pin of the cell is often a small pattern of a lower layer wiring as a layout, and a net connecting adjacent cells is usually realized only with the lower layer wiring. In this case, there is a problem that the wiring connection corresponding to this net cannot be changed by the FIB device.
[0023]
In order to solve this problem, after completion of the design process 101, corresponding wirings are searched for all nets on the chip, and a pair of via contacts (hereinafter referred to as a via-con) to the upper layer and an upper layer connecting them are connected. Patent Literature 1 discloses a method of searching for an area in which wiring can be arranged and adding them to layout data, and a method of providing a via connector up to the top layer as a corresponding layout for all pins of a cell library. It is described in Patent Document 2.
[0024]
However, even with these methods, not all nets can be freely changed in connection by FIB processing. Further, the method described in Patent Document 2 has a drawback that the degree of freedom of arrangement and wiring is significantly alienated by the via connector up to the uppermost layer, and there is a high possibility that the final chip size is greatly affected.
[0025]
FIG. 6 is a layout example for explaining these. FIG. 6A shows a case where gate-level cells 121 and cells 122 are arranged adjacent to each other. It is also assumed that cell 121 has pins 123 and 124, and cell 122 has pins 125 and 126. A net to another cell is connected to each of the pins 123 and 126 by a lower wiring, and a net connecting the adjacent pins 124 and 125 is also directly connected to the lower wiring 127.
[0026]
At this time, if the upper layer wiring 128 passes over the pins 124 and 125, the pin 124 and the pin 125 are laid out in order to lay out a via-con pair for drawing out the lower layer wiring 127 to the uppermost layer and the uppermost layer wiring connecting them. It is necessary to provide a condition that the wiring is sufficiently separated and that the upper layer wiring 128 does not exist at all in the upper part up to the uppermost layer. Such a condition is not satisfied by the cell arrangement at the gate level, and it is impossible to lay out the lower layer wiring 127 so that the connection can be changed by FIB processing.
[0027]
FIG. 6B similarly shows a case where gate level cells 140, 141, 142, 143, 144, and 145 are arranged in a 2 × 3 grid. Each of the cells 140 to 145 has two pins, and a via-con 146 up to the uppermost layer is formed at those pin positions. If the distance between the via-cons 146 arranged in the row direction is not more than twice the wiring pitch determined by the design rule, as shown in FIG. 6B, the via-cons 146 and 3 of the cells 140 and 141 in the first column are provided. The wiring connecting the via capacitors 146 of the cells 144 and 145 in the column cannot pass above the cells 142 and 143 in the second column.
[0028]
In this way, the method of forming via capacitors up to the uppermost layer at all pin positions, especially in the case of gate-level placement and routing, significantly alienates the freedom of wiring path selection and consequently greatly affects the chip size There is a problem that affects.
[0029]
[Patent Document 1]
JP-A-10-308452
[0030]
[Patent Document 2]
JP-A-11-214518
[0031]
[Problems to be solved by the invention]
As described above, the conventional placement and routing program and the method of manufacturing a semiconductor device cannot allocate a desired wiring layer to all nets, and cannot perform arbitrary connection correction using a FIB device after chip manufacture. There was a problem that the production and chip production might have to be redone.
[0032]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is a layout and wiring program capable of forming a desired wiring layer on all nets and performing arbitrary connection correction using a FIB device after chip manufacture. And a method for manufacturing a semiconductor device.
[0033]
[Means for Solving the Problems]
To achieve the above object, a placement and routing program according to the present invention has a plurality of circuit cells having input / output pins, arranged on a chip according to a netlist created by logic design, and an output between these circuit cells. A placement and routing program that has a net connected between a pin and an input pin according to the netlist, and generates layout data of the circuit cell and the net according to a predetermined layout design rule; and A floating wiring cell having an internal net connecting these connection pins is added to the net, and a wiring cell adding function of connecting between the output pin and the input pin via the floating wiring cell is provided. I have.
[0034]
According to the present invention, a floating wiring cell to which a desired wiring layer is allocated can be optimally arranged by using an evaluation function, so that a layout and wiring program capable of forming a desired wiring layer on all nets can be realized.
[0035]
Further, a method of manufacturing a semiconductor device of the present invention has a logic design step of performing a system design and a circuit design based on a specification and creating a netlist, and has input / output pins, and is arranged on a chip according to the netlist. A plurality of circuit cells, and a net in which output pins and input pins between the circuit cells are connected according to the netlist, and layout data of the circuit cells and the net is generated according to a predetermined layout design rule. And a chip manufacturing step of forming circuit elements and wiring on a wafer using the layout data. The layout designing step includes a plurality of connection pins and an internal network connecting the connection pins. Is added on the net, and the float wiring cell is connected through the float wiring cell. It is characterized by further comprising a wiring cell additional step of connecting the force and input pins.
[0036]
According to the present invention, a floating wiring cell having a desired wiring layer can be assigned to all nets in a net list, and the floating wiring cell can be optimally arranged using an evaluation function. It is possible to realize a method of manufacturing a semiconductor device that can easily and flexibly respond to a design change with the device and that can significantly shorten the development period.
[0037]
Further, according to the present invention, a floating wiring cell having a desired wiring layer can be assigned to an arbitrary net, so that an increase in wiring area can be minimized and a critical path can be easily connected with low resistance wiring. Thus, a semiconductor device manufacturing method capable of developing a higher-speed semiconductor device can be realized.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings.
[0039]
(1st Embodiment)
FIG. 1 is an image diagram showing functions of a placement and routing program according to the first embodiment of the present invention.
[0040]
FIG. 1A is an image diagram showing a floating wiring cell 11 which is a feature of the present invention. The float wiring cell 11 has connection pins 12 and 13 and an internal net 14 connecting them. The connection pins 12 and 13 have both an input pin function and an output pin function, and can be connected to an input pin or an output pin of another circuit cell by a net. Pins and nets are abstract concepts in logical design, but are represented in the figure by layout images corresponding to them.
[0041]
The floating wiring cell 11 uses the type of wiring layer, the width of the wiring, and the length of the wiring when the internal net 14 is formed as a layout, as layout information, so that the gate-level cell has the corresponding layout information. I have. Furthermore, when the external net connected to the connection pins 12 and 13 is assigned to a wiring layer different from the internal net 14 of the float wiring cell 11 when the layout is formed as a layout, the floating wiring cell 11 It also has layout information such as the type and shape of the via-con generated at the position.
[0042]
Unlike the gate-level cell, the float wiring cell 11 is not provided as a library but is generated as needed in a float wiring cell process 41 described later.
[0043]
Next, a method of using the floating wiring cell 11 in the placement and routing program of the present invention will be described using a simple example. FIG. 1B is a circuit example including three NAND gates, and FIG. 1C is an image diagram in which a float wiring cell 11 is added to the circuit of FIG. 1B.
[0044]
Now, as shown in FIG. 1B, it is assumed that there is a netlist in which the output pin 16 of the NAND 15, the one input pin 18 of the NAND 17, and the one input pin 20 of the NAND 19 are connected. Here, it is assumed that only one net can be connected to each of the pins 16, 18, and 20, and if necessary, a branch point 21 is provided on the net to branch the net as shown in FIG. I do.
[0045]
For such a netlist, a floating wiring cell 11a is generated as shown in FIG. That is, the float wiring cell 11a is inserted between the output pin 16 of the NAND 15 and the branch point 21, the output pin 16 of the NAND 15 is connected to the connection pin 12a of the float wiring cell 11a, and the connection pin 13a is connected to the branch point 21. I do. Next, the float wiring cell 11b is inserted between the input pin 18 of the NAND 17 and the branch point 21, the connection pin 12b of the float wiring cell 11b is connected to the branch point 21, and the connection pin 13b of the float wiring cell 11b is connected to the NAND 17 Input pin 18 is connected. Similarly, the floating wiring cell 11c is inserted between the input pin 20 of the NAND 19 and the branch point 21, the connection pin 12c of the floating wiring cell 11c is connected to the branch point 21, and the connection pin 13c of the float wiring cell 11c is connected to the NAND 19. Input pin 20 is connected.
[0046]
If the information of the type of the wiring, the width of the wiring, and the length of the wiring are given to the float wiring cells 11a, 11b, and 11c added in this manner so that the processing by the FIB apparatus becomes possible, In the layout that has been completed, the connection of the output pins 16 and the input pins 18 and 20 can be freely changed. Specifically, the wiring type depends on the capability of the FIB device, the design rule, etc., but the type of wiring is the uppermost layer excluding the wiring layer of the power supply main line, the wiring width is the minimum value of the design rule, and the wiring length is the wiring length. Several times the width is appropriate.
[0047]
The main power supply wiring is usually assigned to the uppermost layer or several layers from the uppermost layer, but has a wiring width of several tens of μm, and is removed with a size of several μm square as required when processing with a FIB device. However, it does not affect the operation of the chip at all. Therefore, even under the wiring layer of the main power supply line, there is no problem in the FIB processing as long as the other wiring does not cover the upper part.
[0048]
Although a very simple example has been described here, the floating wiring cell 11 may be added to the net in accordance with the following rules in order to enable connection change of all pins by FIB processing.
[0049]
That is, when the net connected to the pin has no branch point, that is, when the output pin and the input pin of the arranged cell are directly connected by one net, one float wiring is placed on the net. Cell 11 is added.
[0050]
When the net connected to the pin has a branch point, that is, when a plurality of input / output pins are connected by a plurality of nets via the branch point, as shown in FIG. One float wiring cell 11 is added on the net between the pin and the branch point.
[0051]
FIG. 2 is a flowchart showing an outline of a development process according to the first embodiment of the present invention. The figure shows the design steps after the specification is determined, as in FIG. The development process is roughly divided into a design process 31, a manufacturing process 32, and an evaluation correction process 33.
[0052]
The design process 31 includes a logic design step 34 and a layout design step 35. In the logic design step 34, a system configuration is determined based on the overall specifications, and a circuit design for each functional block is performed according to the detailed specifications. Is created.
[0053]
In the circuit design, a cell library or an IP library prepared in advance is used. Next, in a layout design step 35, a specific chip layout is created by the placement and routing program of the present invention using the netlist and the library.
[0054]
The layout design step 35 includes a cell placement step 36, a schematic wiring step 37, an ECO step 38, a redundant cell placement step 39, and a detailed wiring step 40, as in the prior art. , A wiring cell generation step 42, a wiring cell addition step 43, and a wiring cell placement step 44. The float wiring cell processing 41 is performed after the redundant cell arrangement step 39 and before the detailed wiring step 40.
[0055]
In the cell arranging step 36, the gate level cells and the IP cells in units of function blocks in the netlist are arranged in the areas determined at the time of configuring the system.
[0056]
In the general wiring step 37, the wiring route between the pins of the arranged cells is globally determined based on the connection information in the netlist, and the result is added to the netlist as general wiring information. At this stage, wiring grids indicating the types of wiring layers to be allocated to the respective wirings and the detailed spatial paths have not yet been allocated.
[0057]
In the ECO step 38, first, a timing-driven simulation is performed based on the obtained schematic wiring information to obtain a delay time for each net. Next, based on this result, change the buffer size for driving the net, add a buffer to the net corresponding to long-distance wiring, and adjust the buffer and net to distribute the net load so that the specifications are satisfied. Division or modification of the net connection to change the signal timing is performed. The results are fed back to the netlist, and the schematic wiring information is updated at the same time.
[0058]
In the redundant cell arranging step 39, the cell layout at the gate level or at the element level constituting the gate is arranged in an empty area of the chip. This is used for design changes accompanying small changes in specifications, modification of process parameters, detailed simulations, etc. performed after this stage. In some cases, it is also used for dealing with circuit bugs found in post-manufacturing evaluations.
[0059]
In the floating wiring cell processing 41, the floating wiring cell 11 is generated, added to the net, and placed on the chip based on the net list updated in the process up to the redundant cell arranging step 39 described above.
[0060]
First, in the wiring cell generation step 42, the type of wiring layer, the width of the wiring, and the length of the wiring used in the internal net 14 are determined, and the floating wiring cell 11 as layout information is generated. In addition to using these values given by default, in the next wiring cell addition step 43, the netlist at that stage is displayed as a circuit diagram image, and different values are interactively assigned to each floating wiring cell 11. To generate another layout cell having a different shape.
[0061]
When the type of the wiring layer is determined, a default wiring layer of the connection pins 12 and 13 is determined accordingly. Thus, when the wiring layers of the external nets to be connected to these are determined in the detailed wiring step 40, it is possible to determine whether or not to form a via connector there. What is important is that when the wiring layer used in the floating wiring cell 11 is the same as the wiring layer corresponding to the external net to be connected, no via connection is formed.
[0062]
Next, in a wiring cell addition step 43, the floating wiring cell 11 is added to all the pins in the netlist. As described with reference to FIG. 1C, if the net connected to the pin does not have a branch point, one additional floating wiring cell 11 is added to the net, and the additional rule is added to the net. If so, one float wiring cell 11 is added between the pin and the branch point.
[0063]
However, this is a rule for achieving the purpose of enabling connection of all pins to be corrected by FIB processing by adding the float wiring cell 11, and as will be described later, the float wiring cell 11 is used for another purpose. If you want to use it, you need to change to an additional rule suitable for it.
[0064]
Next, in a wiring cell placement step 44, each float wiring cell 11 is placed based on the schematic wiring information. By using the schematic wiring information, it is possible to prevent the floating wiring cells 11 from interfering with each other. Here, since the floating wiring cell 11 can be handled in the same manner as a conventional gate-level cell, a conventional wiring function can be used as it is as an evaluation function for placement and wiring.
[0065]
For example, the chip is divided into certain sections, and the evaluation function is defined using the pin and wiring congestion degree in each section, the number of wiring intersections at the section boundary, and the wiring delay, and the value is minimized. If the layout is determined as described above, the overall layout of the float wiring cell 11 can be optimized. This has the advantage that the conventional placement and routing algorithm can be used with little change.
[0066]
When the float wiring cell processing 41 is completed, in a detailed wiring step 40, a type of a wiring layer is assigned to each net, and a wiring grid position of the detailed route is determined. At this time, as described in the wiring cell generation step 42, when the wiring layer of the floating wiring cell 11 is different from the wiring layer of the external net connected to the floating wiring cell 11, it is necessary to add information for forming a via-conto there. . As a result, the positions of all cells and wirings on the chip are determined, and layout data of the entire chip can be created.
[0067]
When the design process 31 is completed, a chip of the semiconductor device is manufactured in a manufacturing process 32 based on the layout data. Since the manufacturing process 32 is the same as the conventional process, the description is omitted.
[0068]
When the chip is completed in this way, the evaluation and the necessary correction are performed on the specification in the evaluation correction step 33. In the evaluation step 45, based on the specifications, initial characteristics such as the circuit operation of the chip, resistance to a use environment such as temperature and humidity, and power supply voltage, and reliability against long-term aging due to an accelerated test are inspected in detail. .
[0069]
Based on the result, in an evaluation determining step 46, it is determined whether or not the degree of completion of the development is at a level that enables mass production and shipment as a product. If the specifications are completely satisfied and the degree of completion is determined to be sufficient (OK), the development of this product is terminated. If it is determined that there is a problem (NG), the process proceeds to an analysis step 47, where a failure analysis for identifying the cause is performed.
[0070]
As described above, when the placement and routing program of the present invention is used, the connection of all pins can be changed. Therefore, the cause is specified in the analysis step 47. Immediately, the circuit is corrected in the FIB processing step 48, and the process can return to the evaluation step 45.
[0071]
According to the first embodiment, by using the floating wiring cell 11, a part of the wiring connected to all the pins can be assigned to the upper wiring that can be subjected to the FIB process. The connection to all pins can be freely changed by the FIB device. Processing by the FIB apparatus is completed in one day unless the circuit is modified to be very complicated, so that the product development period can be significantly reduced as compared with the related art.
[0072]
In addition, since the layout of the floating wiring cell 11 can be optimized using a conventional evaluation function, the conventional wiring algorithm can be used with almost no change.
[0073]
Furthermore, since the floating wiring cell 11 does not generate unnecessary via connections in connection with an external net, the degree of freedom of the wiring path of the entire chip can be kept high, and the increase in the wiring area can be suppressed as a whole.
[0074]
By optimizing in this way, it is possible to minimize the increase in the wiring area even though all the pins can be processed by the FIB device.
[0075]
In the description of the present embodiment, as an example, a method of using the floating wiring cell 11 for the purpose of shortening the development period by FIB processing has been described, but the present invention is not limited to this. For example, the floating wiring cell 11 can be used for the purpose of preferentially allocating the gate-level connection wiring of the critical path to the low-resistance wiring in order to shorten the wiring delay of the critical path and speed up the circuit operation. In that case, based on the result obtained by the timing driven simulation, the required number of float wiring cells 11 may be added to the net whose speed is to be increased, and low-resistance wiring may be assigned to the wiring type of the internal net 14. .
[0076]
(Second embodiment)
FIG. 3 is an image diagram showing functions of a placement and routing program according to the second embodiment of the present invention.
[0077]
FIG. 3A is an image diagram showing a T-type float wiring cell 61. The T-type float wiring cell 61 has connection pins 62, 63, 64, and an internal net 65 connecting them. The internal net 65 has a branch point 66 in the T-type float wiring cell 61, and the connection pin 62 is connected to the branch point 66, the branch point 66 is connected to the connection pin 63, and the branch point 66 is connected to the connection pin 64.
[0078]
As in FIG. 1, the pins and the nets are represented by the corresponding layout images, and have the type of wiring, the width of the wiring, the length of the wiring, and the layout information of the via connector.
[0079]
FIG. 3B is an image diagram in which a T-type float wiring cell 61 is added to the circuit of FIG. 1B. That is, a T-type float wiring cell 61 is added at the position of the branch point 21 in FIG. 1B, the output pin 16 of the NAND 15 is connected to the connection pin 62 of the T-type float wiring cell 61, and the connection pin 63 and the NAND 17 are connected. , And the connection pin 64 is also connected to one input pin 20 of the NAND 19.
[0080]
As can be seen from comparison with FIG. 1C, this means that the three float wiring cells 11a, 11b, and 11c in FIG. 1C are connected at a branch point 21 in FIG. 1C (hereinafter referred to as a contraction). )). Therefore, if information on the type of wiring, the width of wiring, and the length of wiring is given to the T-type float wiring cell 61 so that processing by the FIB apparatus is possible, the output pin 16, the input pin 18, 20, the connection can be freely changed.
[0081]
This reduction step should be performed after the wiring cell addition step 43 for adding the float wiring cell 11 to the net and before the wiring cell placement step 44 in the development flow (FIG. 2) described in the first embodiment. Appropriate.
[0082]
The development flow using the T-type float wiring cell 61 is almost the same as that of the first embodiment, so that the detailed description is omitted here.
[0083]
According to the second embodiment, in addition to the effects of the invention described in the first embodiment, a plurality of float wiring cells 11 can be replaced by one T-type float wiring cell 61, so that the floating wiring cells 11 can be used in a placement and wiring program. Even if the hardware resources used are the same, there is an advantage that a larger-scale system can be developed.
[0084]
In the description of the present embodiment, the T-type float wiring cell 61 has three connection pins 62, 63, and 64, but the present invention is not limited to this. Although the T-type float wiring cell 61 is generated by reducing the float wiring cell 11, a cell library in which the number and types of connection pins and the form of the internal net connecting them are limited is prepared in advance. It is also possible to reduce, generate, and use only those that conform to.
[0085]
(Third embodiment)
FIG. 4 is an image diagram showing functions of a placement and routing program according to the third embodiment of the present invention.
[0086]
FIG. 4A is an image diagram showing another float wiring cell 81. The float wiring cell 81 has a connection pin 82. The float wiring cell 81 has layout information such as a via connector generated at the time of layout creation and a wiring type and a wiring width that define a small pattern of a wiring layer formed thereon, and a type and shape of the via connector. .
[0087]
That is, the floating wiring cell 81 may be considered to be equivalent to the floating wiring cell 11 in which the wiring length is set to 0. Therefore, generation of the floating wiring cell 81, addition to the net, and arrangement on the chip can be performed in the same manner as in the first embodiment. The only difference is that only one external net is connected to the connection pin 82, and the small pattern of the wiring layer formed on the via connector is isolated when the layout is created.
[0088]
This is because the floating wiring cell 81 is used for the purpose of drawing out the input / output pins of the redundant cell to the upper layer wiring. Hereinafter, description will be made using an example.
[0089]
FIG. 4B is an image diagram in which a floating wiring cell 81 is added to the redundant circuit. Here, a NAND 83 and a D latch 84 are shown as examples of the redundant circuit. Float wiring cells 81a-81g are connected to two input pins 85, 86 and output pin 87 of NAND 83, data input pin 88, clock input pin 89, and two output pins 90, 91 of D latch 84, respectively. Are connected using
[0090]
As described above, redundant cells are used to place extra circuits in empty areas of the chip in advance in order to cope with circuit modifications that may be made after the layout design. It has become. That is, the input / output pins of the redundant circuit are not connected to other nets on the netlist. Therefore, if a layout is generated as it is, a pattern corresponding to the input / output is used in a lower wiring layer, and it is no longer possible to use the FIB device after changing the connection after manufacturing the chip.
[0091]
There is also a method of generating via connectors up to the uppermost layer in advance for all I / O pins of the redundant circuit, but in that case, there is a high possibility that the upper part of the area where the redundant circuit cells are arranged can not be used as a wiring area .
[0092]
As shown in FIG. 4 (b), if the floating wiring cells 81a-81g are connected to these input / output pins 85-91, all the input / output pins of each redundant circuit are connected by the placement and routing program of the present invention. , Are pulled out to the upper wiring layer that can be processed by FIB, and the FIB device can cope with necessary correction. What is important is that the position of the float wiring cell 81 can be freely changed by a placement and routing program. Therefore, the upper region where the redundant circuit cells are arranged can also be freely used as the wiring region.
[0093]
Although the generation of the floating wiring cell 81 can be performed in the same manner as in the first embodiment, in view of the purpose, it is preferable to determine a default value for each development product and generate the same in the same shape. Further, the rule for adding to the net is to search for an isolated pin in the net list and connect to all the isolated pins. As described above, since the floating wiring cell 81 is considered to be a special form of the floating wiring cell 11, the placement evaluation function is the same as that of the first embodiment, and the placement and routing can be performed by the same algorithm without any problem. it can.
[0094]
The development flow using the float wiring cell 81 is the same as that of the first embodiment, and thus the detailed description is omitted here.
[0095]
According to the third embodiment, in addition to the effects of the invention described in the first embodiment, all the pins of the redundant circuit can be pulled out to the wiring layer that can be processed by the FIB device. By adding redundant circuits as well as connection changes, it is possible to flexibly cope with certain changes and modifications in the logic design.
[0096]
In the description of the third embodiment, the connection pin 82 has both functions of an input pin and an output pin. However, these are separated, and the floating wiring cell 81 for the input pin and the output pin for the output pin are respectively separated. Float wiring cell 81 of FIG.
[0097]
In the description of the first to third embodiments, the float wiring cells 11, 61, and 81 are generated as necessary in the wiring cell generation step 42, but they are registered in advance in the system as a cell library. You can also use this. Further, after the wiring cell adding step 43 or the wiring cell arranging step 44 is completed, the image may be displayed and added or corrected interactively.
[0098]
Further, the execution order of the floating wiring cell processing 41 using the placement and routing program of the present invention is not necessarily limited to the flow of FIG. It can be performed after the cell placement step 36 or after the general wiring step 37. Alternatively, in each of these steps including the step of arranging the redundant cells 39, it is also possible to narrow down the target in a stepwise manner.
[0099]
【The invention's effect】
As described above, according to the present invention, a floating wiring cell having a desired wiring layer can be assigned to all nets in a netlist, and the floating wiring cell can be optimally arranged using an evaluation function. In addition, it is possible to easily and flexibly respond to a design change using a FIB device after chip production, thereby realizing a significant reduction in the development period.
[0100]
Further, according to the present invention, a floating wiring cell having a desired wiring layer can be assigned to an arbitrary net, so that an increase in a wiring area can be minimized and a critical path can be easily formed with low resistance wiring. A high-speed semiconductor device which can be connected can be realized.
[Brief description of the drawings]
FIG. 1 is an image diagram showing functions of a placement and routing program according to a first embodiment of the present invention.
FIG. 2 is a development process flowchart showing an outline of a method of manufacturing a semiconductor device according to the first to third embodiments of the present invention.
FIG. 3 is an image diagram showing functions of a placement and routing program according to a second embodiment of the present invention.
FIG. 4 is an image diagram showing functions of a placement and routing program according to a third embodiment of the present invention.
FIG. 5 is a development process flowchart showing an outline of a conventional semiconductor device manufacturing method.
FIG. 6 is a diagram illustrating a problem in a conventional semiconductor device.
[Explanation of symbols]
11, 81 Float wiring cell
12, 13, 62, 63, 64, 82 connection pins
14, 65 Internal net
15, 17, 19, 83 NAND
16, 87, 90, 91 output pins
18, 20, 85, 86, 88, 89 input pins
21, 66 junction
31 Design process
32 Manufacturing Process
33 Evaluation correction process
34 Logic Design Step
35 Layout Design Step
36 cell placement steps
37 Schematic wiring steps
38 ECO Step
39 Redundant cell placement step
40 Detailed wiring steps
41 Float wiring cell processing
42 Wiring Cell Generation Step
43 Wiring Cell Addition Step
44 Wiring cell placement step
45 Evaluation steps
46 Evaluation Judgment Step
47 Analysis Step
48 FIB processing steps
61 T type float wiring cell

Claims (23)

It has input / output pins, a plurality of circuit cells arranged on a chip according to a netlist created by logic design, and a net connecting output pins and input pins between these circuit cells according to the netlist. And a layout and wiring program for generating layout data of the circuit cells and the nets according to a predetermined layout design rule,
A floating cell having a plurality of connection pins and an internal net connecting between the connection pins is added on the net, and a wiring cell adding function of connecting the output pin and the input pin via the float wiring cell is provided. A placement and routing program characterized by having. The wiring cell addition function,
If there is no branch point on the net, connect the float wiring cell having the two connection pins between the output pin and the input pin,
If a branch point exists on the net, the float wiring cell having the two connection pins is connected between an output pin or an input pin of the circuit cell and the branch point. 2. The placement and routing program according to 1. The wiring cell addition function,
If there is no branch point on the net, connect the float wiring cell having the two connection pins between the output pin and the input pin,
When a branch point exists on the net, the float wiring cell having the same number of the connection pins as the number of the nets connected to the branch point is connected between the output pin and the input pin. 2. The placement and routing program according to claim 1, wherein: 4. A wiring cell arranging function for arranging the floating wiring cells added to the net such that a predetermined evaluation function is minimized. Placement and routing program described in. The float wiring cell,
A type of a wiring layer to which the internal net is assigned;
Wiring width and wiring length when the internal net is laid out,
5. The storage medium according to claim 1, further comprising layout information including types and shapes of via contacts when the connection pins are laid out. 6. 6. The storage medium according to claim 5, wherein the float wiring cell has the layout information for allocating a low-resistance wiring layer to the internal net. 6. The storage medium according to claim 5, wherein the float wiring cell has the layout information for allocating an uppermost wiring layer excluding a wiring layer of a power supply main line to the internal net. A placement and routing program for generating layout data of circuit cells arranged on a chip having input / output pins according to a predetermined layout design rule,
A function of adding a float wiring cell having one connection pin corresponding to the input / output pin of the circuit cell and connecting the input / output pin of the circuit cell and the connection pin of the float wiring cell with a net. A placement and routing program characterized by the following. A netlist including the circuit cell, the float wiring cell, and the net; and a function of generating layout data based on the netlist in accordance with a predetermined layout design rule. A placement and routing program according to claim 8. 10. The placement and routing program according to claim 8, further comprising a function of arranging the circuit cells and the float wiring cells so that a predetermined evaluation function is minimized. The float wiring cell,
Types and shapes of via contacts when the connection pins are laid out,
11. The storage medium according to claim 8, further comprising layout information including a type and a shape of a wiring layer to be allocated to a conductive pattern formed on the via contact. . A function of displaying an updated netlist to which the float wiring cell has been added as a circuit diagram image according to the layout information;
A function of correcting the layout information based on the input data;
12. The program according to claim 5, further comprising: a function of redisplaying the updated netlist as a circuit diagram image in accordance with the corrected layout information. . A logic design process for performing system design and circuit design based on specifications and creating a netlist;
Layout data of a plurality of circuit cells having input / output pins and arranged on a chip according to the netlist, and layout data of a net connecting output pins and input pins between the plurality of circuit cells according to the netlist. , A layout design process for generating according to a predetermined layout design rule,
Using the layout data, a chip manufacturing step of forming circuit elements and wiring on the wafer,
The layout design process includes:
A wiring cell adding step of adding a floating wiring cell having a plurality of connection pins and an internal net connecting the connection pins to the net, and connecting the output pin and the input pin via the float wiring cell; A method for manufacturing a semiconductor device, further comprising: The wiring cell adding step,
If there is no branch point on the net, connect the float wiring cell having the two connection pins between the output pin and the input pin,
If a branch point exists on the net, the float wiring cell having the two connection pins is connected between an output pin or an input pin of the circuit cell and the branch point. 14. The method for manufacturing a semiconductor device according to item 13. The wiring cell adding step,
If there is no branch point on the net, connect the float wiring cell having the two connection pins between the output pin and the input pin,
When a branch point exists on the net, the float wiring cell having the same number of the connection pins as the number of the nets connected to the branch point is connected between the output pin and the input pin. The method for manufacturing a semiconductor device according to claim 13, wherein The layout design process includes:
16. The wiring cell arranging step of arranging the floating wiring cell added to the net such that a predetermined evaluation function is minimized. 13. The method for manufacturing a semiconductor device according to item 5. The float wiring cell,
A type of a wiring layer to which the internal net is assigned;
Wiring width and wiring length when the internal net is laid out,
17. The method of manufacturing a semiconductor device according to claim 13, further comprising layout information including a type and a shape of a via contact when the connection pin is laid out. 18. The method according to claim 17, wherein the float wiring cell has the layout information for allocating a low-resistance wiring layer to the internal net. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the float wiring cell has the layout information for allocating an uppermost wiring layer excluding a wiring layer of a power supply main line to the internal net. A layout design step of generating layout data of circuit cells arranged on a chip having input / output pins according to a predetermined layout design rule;
A chip manufacturing step of forming circuit elements and wiring on a wafer using the layout data,
The layout design process includes:
A method of manufacturing a semiconductor device, further comprising a wiring cell adding step of adding a floating wiring cell having one connection pin on a chip and connecting an input / output pin of the circuit cell and the connection pin by a net. The layout design process includes:
The method further includes a detailed wiring step of generating a netlist including the circuit cell, the float wiring cell, and the net, and generating layout data based on the netlist in accordance with a predetermined layout design rule. The method for manufacturing a semiconductor device according to claim 20, wherein The layout design process includes:
22. The semiconductor device according to claim 20, further comprising a wiring cell arranging step of arranging the circuit cell and the floating wiring cell such that a predetermined evaluation function is minimized. Method. The float wiring cell,
Types and shapes of via contacts when the connection pins are laid out,
23. The semiconductor device according to claim 20, further comprising layout information including a type and a shape of a wiring layer allocated to a conductive pattern formed on the via contact. Production method.

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