JPH06216249A - Automatic layout design system for ic chip - Google Patents

Abstract

PURPOSE:To prevent the breaking of a wiring path or the narrowing of a wiring and to increase an yield in manufacturing chips by providing the system with a flat function which fills an unwired part with dummy graphics. CONSTITUTION:Conventional automatic layout systems have five major functions including a layout library input function 1, a net list input function 2, an automatic arrangement function 3, an automatic wiring function 4, and a graphic data output function 5. Besides these functions, a flat function 6 is newly added to the conventional system. The flat function 6 is to fill an unwired space of each interconnection layer in the wiring layout where physical positions are already determined by the automatic wiring function. The flat function is executed after the automatic arrangement function 3 and the automatic wiring function 4 are executed. With the flat function, troubles such as the breaking of a wiring path due to a difference in level between the interconnection layers, which has never been considered in the conventional systems, can be 100% prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout design system for automatically designing layouts of LSIs and ICs.

[0002]

2. Description of the Related Art Generally, an LSI or IC design includes a layout design process, which is a process of creating a mask diagram which is an original diagram for realizing an electric circuit on an actual silicon chip. . When manufacturing a large-scale chip composed of hundreds of thousands of transistors called VLSI, it is difficult to manually create a mask diagram.
Therefore, an automatic layout design system (hereinafter referred to as an automatic layout system) is performed by using this computer for the layout design.

The structure of a conventional automatic layout system will be described with reference to FIG. This figure shows the configuration of a conventional general automatic layout system. This automatic layout system is realized by five major functions: a layout library input function 1, a netlist input function 2, an automatic layout function 3, an automatic wiring function 4, and a graphic information output function 5.

The layout library input function 1 is L
AND, NAND, OR, NOR, E called cell libraries are necessary for creating SI and IC.
There is graphic information indicating an electronic circuit such as an XOR. They are,
It can be considered as the smallest unit that constitutes an LSI or IC,
There is also a macro library in which a plurality of electronic circuits of the minimum unit are combined to form one cell library. The layout library data 11 is data of these various cells and macro libraries. In the layout library input function 1, the main function is to extract / select the cell library information necessary for the layout to be created and convert (input) the cell library information into the database 13.

The netlist input function 2 is a layout library input for inputting a part which is a framework for creating an LSI or an IC, and there is another necessary information as a material for creating an LSI or an IC. The information is "how to connect and assemble the skeleton layout library?" And is generally called a netlist. The electronic circuit, which is the layout library described above, has a portion called a "terminal" for exchanging information (input / output) with the external world.

The netlist data 12 is information expressing the connection relationship between terminals of this library and other libraries. In the netlist input function 2, connection of terminals between cell libraries required for a layout to be created. The main function is to convert (input) the netlist information, which is the relationship, into the database 13.

The automatic placement function 3 requires a physical coordinate position for the layout library, which is theoretical information input, in order to make it an LSI or IC product. This layout library has a problem of deciding the layout position "where on the LSI or IC should it be located?". Depending on whether the layout position is good or not, the LS after the layout design is performed.
This greatly affects the size (area) and performance of I and IC.

The automatic placement function 3 is a function mainly to determine an optimum layout library placement position in consideration of not only the size relation of the layout library but also the connection relation of the netlist and save the information in the database. Is.

With the automatic wiring function 4, it is necessary to connect terminals of the libraries according to the netlist by wiring to the layout library whose layout position is determined by the automatic layout function. With this automatic wiring function 4,
Using the space between the libraries arranged by the automatic placement function or the space on the library, determine the physical position of the connection wiring route (netlist) of the terminals of the libraries, Its main function is to save that information (wiring pattern) in the database. The wiring that normally connects terminals has different layers depending on the height. If multiple layers are used, the space divided by one wiring path (called a net) will pass through by shifting the layers. (Crossing) is possible. The conventional automatic wiring function fulfills its function by utilizing such a basic concept of a wiring layer.

The wiring must be created according to a wiring rule called a design rule. The information of this design rule includes "wiring grid", "wiring width type of each layer", "contact connecting wiring of each layer", "necessary interval between the same nets in the same layer", "necessary interval between different nets in the same layer", and " There are various information such as "required interval between same nets in different layers" and "required interval between different nets in different layers". The automatic wiring function 4 is configured with a complicated algorithm so that a wiring result satisfying these rules can be created.

The graphic information output function 5 is an automatic layout function 4
The layout information (database) that is the original drawing of the LSI or IC created by the automatic wiring function 4 needs to be converted into the information that serves as an interface in order to deliver it to the next manufacturing process. The graphic information output function 5 has a main function of producing the layout data 14 by performing the conversion output.

Recently, with the improvement of LSI and IC manufacturing technology,
Multilayered wiring layers have been developed in which the connection wiring (netlist) is divided into a number of layers for wiring. FIG. 7 shows an example of a cross-sectional view of an LSI or IC chip designed by the automatic layout system based on this multilayer structure. This section layout diagram is
1AL, 2AL, 3AL and three wiring layers 21, 22, 2
Designed using 3. The 1AL wiring 21 shows the lowermost layer of the wiring layer, the 2AL wiring 22 shows the middle layer of the wiring layer, and the 3AL wiring 23 shows the uppermost layer of the wiring layer. In addition, the space between the 1AL wiring layer 21 and the 2AL wiring layer 22 and the 2AL wiring layer 22 and the 3AL wiring layer 23
The space between and is an insulating layer for preventing an electrical short circuit between the upper and lower wirings.

[0013]

In the chip created by the above-mentioned conventional automatic layout system, the upper layer wiring 3AL wiring 23 is the lower layer wiring 1AL wiring 21 or 2AL wiring 22 for multilayering the wiring layers. Has caused a large step. Therefore, the 3AL wiring 23 that should be connected originally should be the disconnection point 25 of the wiring.
It has been cut at this point. Therefore, the original LS
The functions of I and IC cannot be satisfied, and LS
The yield at the time of manufacturing the I and IC chips is deteriorated, and the electrical reliability of the chips is also deteriorated.

The object of the present invention is to prevent the upper layer wiring from being cut or thinned by using such an automatic layout system, thereby improving the yield at the time of chip manufacturing and improving the electrical reliability of the chip. An object is to provide an automatic layout design system for the designed IC.

[0015]

The structure of an IC automatic layout design system of the present invention is such that design rule information and a database are input, wiring figure information of each wiring layer is created from these, and unwired of each wiring layer is created. It is characterized in that it has a flat function of creating a dummy figure in a portion and filling the unwiring portion with the dummy figure.

[0016]

1 is a block diagram showing the configuration of an automatic layout system having a flat function according to the present invention. This automatic layout system is characterized by the addition of the flat function 6 in addition to the conventional automatic layout system.

The flat function 6 is a function of filling an unwired space for each wiring layer of the wiring layout information whose physical position is determined by the automatic wiring function with a dummy figure. The flat function 6 is executed after the processing of the automatic placement function and the automatic wiring function is completed.

Next, the processing flow of the flat function 6 will be described with reference to the flow chart of FIG.

(1) Input processing of design rule information (S
1) Input the rule information of the layout for performing the flat processing. This is an input process of information necessary for considering a space and a size with a wiring figure when creating a dummy figure between wirings.

(2) Database input processing (S2) All wiring figures are input from the database. As the information to be input here, in addition to the wiring graphic, necessary information for generating a dummy graphic (such as a wiring graphic of a library or a netlist) is also input.

(3) Repetitive processing for each layer (S3) Here, the number of wiring layers used is judged to confirm whether there is a wiring layer which generates a dummy figure. The judgment as to whether the wiring layer is present or not can be entered from the design rule information. If there is a wiring layer, the logical operation structure expansion processing 4 of the next wiring figure information is performed for each layer.
Since the graphic logic operation processing 5 and the dummy graphic generation processing 6 are performed, the processing flows toward the "continuation". On the other hand, if there is no wiring layer, the processing will flow toward the "end".

(4) Logical operation structure development processing of wiring figure information (S4) The wiring figure in the wiring layer which generates the dummy figure is developed into the logical operation structure so that the figure logical operation can be performed.

(5) Graphic logical operation processing (S5) The graphic logical operation of the wiring graphic is performed. A for graphic logic operation
Although there are many calculation methods such as ND, OR, and EXOR, the purpose here is to obtain the used position of the wiring pattern by these calculations.

(6) Dummy figure generating process (S6) From the positions of the wiring figures obtained by the figure logical operation processing, spaces which are not used as wiring figures are searched for and generated as dummy figures. In this case, the design rule also considers the distance from the wiring figure, the size, and the like.

(7) Database Output Processing (S7) All information generated as dummy figures is output to the database. A flat function can be realized by the flow of these series of processes.

The layout figure of the chip created when the flat function 6 is used has a cross-sectional view as shown in FIG. 3, and the cutting points of the 3AL wirings 21 to 23 of FIG. The wiring break point 25 can be removed by inserting the dummy figure 24.

FIGS. 4A to 4D are plan views showing a part of a chip designed with two-layer wiring by this automatic layout system. FIG. 4 (A) shows a layout diagram designed by the conventional automatic layout system according to the two-layer rule using the 1AL layer 21 and the 2AL layer 22.
The AL wiring 21 is graphic information wired in a lower layer, and the 2AL wiring 22 is graphic information wired in an upper layer. In the conventional automatic layout system, there is no figure information in the unwired portion.

FIG. 4B is a layout diagram of the same portion designed by using the flat function of this embodiment. In this figure, the dummy figure 2 created by the flat function 6
Since the pattern 4 is difficult to understand, it will be described with reference to FIGS. 4C and 4D in which the 1AL wiring layer 21 and the 2AL wiring layer 22 are divided.

FIG. 4C shows the graphic information of only the 1AL wiring layer 21 when wiring is performed using this flat function. 1AL wiring 21 is a wiring figure created by a conventional automatic layout system, and is a dummy figure 2
Reference numeral 4 is a dummy figure created by the flat function 6 for filling an unwired portion.

Similarly, FIG. 4D is a diagram showing the graphic information of only the 2AL wiring layer 22, and the 2AL wiring 22 and the dummy graphic 24 are generated. Although there is some space between the 1AL wiring 21 and the dummy graphic 24 or between the 2AL wiring 22 and the dummy graphic 24, this is due to the electrical contact between the wiring and the dummy graphic. This is to avoid a short circuit, because the size of the interval is set in the input design rule information described in the flat function processing.

Next, an example of a special use method that can be realized by the flat function will be described with reference to FIG. In the first embodiment,
Although the example of filling the space other than the wiring with the generation of the dummy graphic 24 has been described, the present embodiment will describe an example of the flat function of generating the dummy graphic in consideration of the prohibited area 26 in which the dummy graphic cannot be generated. FIGS. 5A and 5B are diagrams of the same locations as the layout diagram described in the first embodiment.

The special function of this embodiment is that the area shown by the dummy figure prohibited area 26 of FIG. 5A is set in the design rule information in advance, and the flat function "input of design rule information" is set. You can enter the information in "Process".

The input dummy figure prohibited area is 1A shown in FIG. 5B in the "dummy figure generating process S6".
It is possible to prevent the dummy figure of the layout diagram of only the L wiring layer 21 from being generated in the designated prohibited area. In this example, it is explained that only the dummy figure prohibited area 26 of the 1AL wiring layer 21 is designated.
Not only the wiring layers but also all the wiring layers of the chip designed by the multilayer rule corresponding to the 2AL wiring layer and the 3AL wiring can individually specify the dummy figure prohibited area.

Such a function is effective when it is desired to intentionally manually modify a wiring figure in a layout diagram designed using the automatic layout system. If the prohibited area is designated in advance in the layer or place to be manually corrected, there is an advantage that the labor of deleting the dummy figure can be saved.

[0035]

As described above, according to the present invention,
It is possible to prevent 100% of the problem that the wiring route is cut and the wiring becomes thin due to the step of the wiring layer, which has not been considered in the conventional automatic layout system. This has the effect of improving reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing of the flat function of FIG.

FIG. 3 is a cross-sectional view of an example of a chip designed by the system of FIG.

FIG. 4 is a layout diagram of a chip designed by the system of FIG.

5 is a plan view of another example of a chip designed by the system of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional automatic layout system.

7 is a cross-sectional view of a chip designed with the system of FIG.

[Explanation of symbols]

 1 Layout Library Input Function 2 Netlist Input Function 3 Automatic Placement Function 4 Moving Wiring Function 5 Graphic Information Output Function 6 Flat Function 11 Layout Library Data 12 Netlist Data 13 Database 14 Layout Data 21 1AL Wiring 22 2AL Wiring 23 3AL Wiring 24 Dummy Graphic 25 Wiring cut point 26 Dummy graphic prohibited area S1 Design rule information input processing S2 Database input processing S3 Layer-by-layer repeated processing S4 Wiring graphic information logical operation structure expansion processing S5 Graphic logical operation processing S6 Dummy graphic generation processing S7 Database output processing

Claims (1)

[Claims] 1. Inputting design rule information and a database, creating wiring figure information of each wiring layer from these, creating a dummy figure in an unwired part of each wiring layer, and using the dummy figure to create the unwired part. An automatic IC layout design system characterized by having a flat function for filling in holes.