JP2003282712A - Wiring method for clock of semiconductor integrated circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring method for a clock of a semiconductor integrated circuit that enables a clock buffer for clock skew adjustment that is inserted in a path from a most significant route clock buffer to the end of a flip flop circuit and that can reduce the detour of clock wiring with keeping a hierarchy structure of a layout and the semiconductor integrated circuit thereof. <P>SOLUTION: In a step S2, grid-like upper mesh clock wiring is formed on a semiconductor chip. In a step S3, a virtual mesh clock terminal is formed on a cross point of the upper mesh clock wiring and the outer shape of a circuit block. Then, in a step S4, the upper mesh clock wiring on the circuit block is replaced with lower mesh clock wiring by setting a wiring grid for the mesh clock wiring so as to pass the virtual mesh clock terminal in the circuit block and by changing its property. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock wiring method and a semiconductor integrated circuit for a semiconductor integrated circuit, and more particularly to a clock wiring method and a semiconductor integrated circuit for a semiconductor integrated circuit capable of reducing clock skew.

[0002]

2. Description of the Related Art The circuit scale of semiconductor integrated circuits continues to increase, and in order to reduce the computer load and the design period when automatically laying out semiconductor integrated circuits,
It is common to design a layout by hierarchizing a semiconductor integrated circuit. In this method, layout design is performed for each layer of the integrated circuit, and clock distribution processing for reducing clock skew is also performed for each layer. As such a conventional example, Japanese Patent Laid-Open No. 2001-125937 discloses
It describes a clock wiring method when a layout design is performed by hierarchizing a semiconductor integrated circuit.

Next, a clock wiring method using the clock tree method described in the above publication will be described with reference to FIG.

FIG. 5 is a layout diagram of a semiconductor chip to which the clock wiring method according to the above publication is applied. The input / output buffer 5 arranged along the inner circumference of the semiconductor chip 51.
2 and an internal area 53 in which an internal circuit is arranged,
Circuit blocks 54, 55, and 56 are arranged in this internal region 53.

The circuit blocks 54 to 56 include a plurality of flip-flop circuits 57, and clock wiring is performed via clock buffers so that clock skew in each of the circuit blocks 54 to 56 is minimized. , A clock tree is generated.

For example, in the circuit block 54, a plurality of flip-flop circuits 57 are provided from the clock buffer 54 '.
The clock signal is supplied so that the clock skew becomes minimum.

Similarly, in the circuit block 55, the clock signal from the clock buffer 55 'is supplied to the clock buffer 5'.
51, 552, and further from these clock buffers 551, 552 a plurality of flip-flop circuits 5
The clock signal is supplied so that the clock skew becomes minimum with respect to 7.

At this time, a clock tree is generated in the circuit block 55 so that the delay of the clock signal becomes equal to all the flip-flop circuits forming the circuit block 55 from the clock buffer 55 '.

Similarly, in the circuit block 56, the clock signal from the clock buffer 56 'is supplied to the clock buffer 5'.
61 and 562, and further from these clock buffers 561 and 562 to the clock buffer 5 of the lower hierarchy.
611, 5612 and clock buffers 5613, 5
A clock signal is supplied to 614, and the clock signals are supplied from these clock buffers 5611 to 5614 to the plurality of flip-flop circuits 57. And
The clock tree is generated in the circuit block 56 so that the delay of the clock signal becomes equal to all the flip-flop circuits forming the circuit block 56 from the clock buffer 56 ′.

In this way, each circuit block 54-56
Adjusted to minimize clock skew within. Then, the average value of the delay values of the clock signals from the uppermost clock buffer of each circuit block to the terminal flip-flop circuit is calculated. For example, in the circuit block 55, the average value for the delay value of the clock signal from the clock buffer 55 ′ to the flip-flop circuit 57 is calculated.

Next, the clock buffers are laid out and the clock wirings are arranged in the upper hierarchy so that the clock skew from the root clock buffer 59 to the flip-flop circuits forming each circuit block is minimized.

More specifically, a clock signal is directly supplied from the root clock buffer 59 to the circuit block 56, and is also supplied to the circuit blocks 54 and 55 via the clock buffer 510. . At this time, the number of stages of the clock buffer 510 and the clock wiring 51 are set so that the clock skew from the root clock buffer 59 to the flip-flop circuit 57 forming each of the circuit blocks 54 to 56 is minimized.
The wiring length of 1 is adjusted.

Next, a second conventional technique for reducing the clock skew of the semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 3-232267 will be described with reference to FIG.

In the clock wiring method described in this publication, lattice-shaped mesh clock wiring is provided over the entire surface of the semiconductor chip 61.
A clock signal is supplied from 2 to the end flip-flop circuit 64 via the clock buffer 63.

In this clock wiring method, the wiring resistance of the clock wiring from the root clock buffer at the top to the flip-flop circuit at the terminal is reduced, so that the clock skew can be reduced.

[0016]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the clock wiring method described in Japanese Patent Laid-Open No. 125937, when there is a large difference in the number of circuit elements of each circuit block to which the clock signal is supplied from the highest-level root clock buffer or the number of flip-flop circuits forming the circuit block. In order to reduce the clock skew from the root clock buffer at the top to the flip-flop circuit at the end, the clock delay value in each circuit block greatly differs, and a large number of clock buffers for clock skew adjustment are provided. Alternatively, it is necessary to perform processing such as bypassing the clock wiring.

In other words, if the number of flip-flop circuits that become the load of the clock buffer of the upper layer and the wiring length of the clock wiring that also becomes the load of the clock buffer of the upper layer differ greatly from circuit block to circuit block, the clock delay will be different for each circuit block. The values will be very different.

Explaining it concretely in the example of FIG. 5, since there are only two flip-flop circuits 57 constituting the circuit block 54, one clock buffer 54 'for driving this flip-flop circuit 57 is sufficient. .

On the other hand, in the circuit block 55, the number of the flip-flop circuits 57 is as large as eight, so that the clock signal is driven by the three clock buffers 55 ', 551 and 552 of two layers.

Further, since the number of flip-flop circuits forming the circuit block 56 is even larger, 7 layers of 3 layers are provided.
Clock buffers 56 ', 561, 562, 561
The clock signal is driven by 1-5614.

Therefore, in order to reduce the clock skew from the uppermost root clock buffer to the end flip-flop circuit, five clock buffers 510 are connected in series between the root clock buffer 59 and the circuit block 54, and Three clock buffers 510 are connected in series between the clock buffer 59 and the circuit block 55. As described above, in order to reduce the clock skew, it is necessary to provide a large number of clock buffers for adjusting the clock skew, and to largely detour the clock wiring in order to increase the wiring capacity of the clock wiring.

Further, wiring delay changes due to changes in the driving capacity of the clock buffer for clock skew adjustment and clock wiring capacity due to manufacturing variations, and even if the clock skew is minimum at the center of manufacturing variations, other conditions are not satisfied. Then, there is a problem that the clock skew becomes large.

Further, in the clock wiring method for a semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 3-232267, the hierarchical structure of the semiconductor integrated circuit is developed into one layer, and the clock buffers are arranged and the clock wiring is performed collectively. Therefore, there is a problem that the processing amount of the computer becomes enormous.

Therefore, an object of the present invention is to generate mesh clock wirings in a lattice shape for each layer of a semiconductor integrated circuit and to connect the mesh clock wirings for each layer to each other, and to connect the mesh clock wirings for each layer to each other through these mesh clock wirings. By supplying a clock signal to this flip-flop circuit, the increase in the processing amount of the computer is suppressed, and the clock buffer for clock skew adjustment inserted in the path from the top root clock buffer to the end flip-flop circuit. Another object of the present invention is to provide a clock wiring method for a semiconductor integrated circuit and a semiconductor integrated circuit capable of reducing the detour of the clock wiring.

Another object of the present invention is to provide a clock wiring method for a semiconductor integrated circuit capable of shortening the design period without redesigning many times to design a necessary clock skew. It is to provide a semiconductor integrated circuit.

[0026]

Therefore, according to the clock wiring designing method for a semiconductor integrated circuit of the present invention, the circuit blocks constituting the semiconductor integrated circuit are arranged on the semiconductor chip based on the circuit connection information of the semiconductor integrated circuit. A first step; a second step of generating a lattice-shaped upper mesh clock wiring on which a clock signal from the outside propagates on the semiconductor chip; and an attribute of the upper mesh clock wiring on the circuit block is changed. Generate a lower mesh clock wiring from the upper mesh clock wiring on the circuit block, connect the upper mesh clock wiring and the lower mesh clock wiring, and set a wiring grid for the lower mesh clock wiring. The third step and one or more of the lower mesh clock wires are A fourth step of setting a clock signal line to be input to the block, a clock buffer is inserted and arranged between the flip-flop circuit forming the circuit block and the lower mesh clock wiring, and the clock buffer and the flip-flop circuit are arranged. And a fifth step of wiring between the clock buffer and the lower mesh clock wiring.

Further, the semiconductor integrated circuit according to the present invention comprises a circuit block arranged on a semiconductor chip, an upper mesh clock wiring provided on the semiconductor chip in a grid pattern for propagating an external clock signal, and the circuit. Changing the attribute of the upper mesh clock wiring on the block, the lower mesh clock wiring generated from the upper mesh clock wiring on the circuit block,
The upper mesh clock wiring and the lower mesh clock wiring are connected, a wiring grid is set for the lower mesh clock wiring, and the clock skew of the flip-flop circuit in the circuit block is within a predetermined value, It is characterized in that a clock buffer connected to the lower mesh clock wiring is inserted and arranged, and a wiring length of a clock wiring connecting the clock buffer and the lower mesh clock wiring is adjusted.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a flow chart showing a clock wiring method for a semiconductor integrated circuit according to the present invention. Step S1
Then, referring to the circuit connection information 100, the circuit blocks forming the semiconductor integrated circuit are arranged on the semiconductor chip.

FIG. 2A shows a part of the circuit connection information 100. The clock input terminals 6 of the circuit blocks 3, 4 and 5 are routed from the external clock input terminal 1 through the root clock buffer 1 '. , 7 and 8 are connected to the clock signal line 2.

Next, in step S2, a lattice-shaped upper mesh clock wiring is generated on the semiconductor chip and a wiring connecting the root clock buffer and the upper mesh clock wiring is generated.

FIG. 2B shows the circuit blocks 3, 4, and 5 arranged on the semiconductor chip 101 in step S1 and the upper mesh clock wiring 9 generated in step S2.
10 and a root clock buffer 1 ′ that uses one of the input / output buffers 102 arranged along the inner circumference of the semiconductor chip 101 to supply a clock signal to the flip-flop circuit arranged in the semiconductor chip 101, and a root clock. FIG. 10 is a layout diagram showing a buffer 1 ′ and a virtual wiring 2 ′ that connects the clock input terminals 6, 7, and 8. The upper mesh clock wiring 9 in the horizontal direction is composed of, for example, five layers of metal wiring, and the upper mesh clock wiring 10 in the vertical direction is composed of, for example, six layers of metal wiring. The intersection with 10 is connected by a through hole and has the same potential.

The positions of the clock input terminals 6, 7, and 8 are not fixed in the process of step S2, and they are virtually arranged on the outer shapes of the circuit blocks 3, 4, and 5. The wiring width and mesh interval of the upper mesh clock wiring are selected so that the wiring resistance becomes sufficiently small.

It should be noted that the wiring grids of the upper mesh clock wirings 9 and 10 are defined outside the circuit blocks 3, 4, and 5 so that the layout tool can recognize the upper mesh clock wirings 9 and 10. So
The upper mesh clock wirings 9 and 10 can be used outside the circuit blocks 3, 4, and 5.

However, the wiring grids of the upper mesh clock wirings 9 and 10 are not defined inside the circuit blocks 3, 4 and 5, and the layout tool for automatic placement and automatic wiring recognizes the upper mesh clock wirings 9 and 10. Therefore, the upper mesh clock wirings 9 and 10 cannot be used in the internal areas of the circuit blocks 3, 4, and 5. That is, the upper mesh clock wirings 9 and 10 are
It is in a state where it simply passes through the circuit blocks 3, 4, and 5.

Next, in step S3 of FIG. 1, a virtual mesh clock terminal which is a virtual terminal is generated at the intersection of the upper mesh clock wiring and the outer shape of the circuit block. This virtual mesh clock terminal defines a wiring grid of the lower mesh clock wiring inside the circuit block, and is a virtual mesh clock terminal required to connect the upper mesh clock wiring 9 and the lower mesh clock wiring with the virtual mesh clock terminal. This is the terminal information, and the terminal data is not actually generated.

Next, in step S4 of FIG. 1, a wiring grid for mesh clock wiring is set in the circuit block so as to pass the virtual mesh clock terminal, and the upper mesh clock wiring on the circuit block and the lower mesh clock wiring are set. Replace with.

The upper mesh clock wiring and the lower mesh clock wiring that replaces the upper mesh clock wiring are formed in the same wiring layer, and the upper mesh clock wiring and the lower mesh clock wiring each have properties (attributes). Thus, it is determined whether the wiring is the upper mesh clock wiring or the lower mesh clock wiring.
Therefore, the processing content of replacing the upper mesh clock wiring with the lower mesh clock wiring means replacing the property of the upper mesh clock wiring with the property of the lower mesh clock wiring.

FIG. 3A shows the upper mesh clock wirings 9 and 10 generated in step S2 of FIG.
FIG. 4 is a layout diagram shown together with the circuit block 3, the clock input terminal 6, and the virtual wiring 2 ′ shown in FIG.
2B is a layout diagram showing the virtual mesh clock terminal 11 generated in step S3 of FIG. 1 and the lower mesh clock wirings 9 ′ and 10 ′ generated in step S4.

The wiring layer of the lower mesh clock wiring 9'is five layers like the wiring layer of the upper mesh clock wiring 9, and the wiring layer of the lower mesh clock wiring 10 'is
There are six layers, which are the same as the wiring layers of the upper mesh clock wiring 10, and the intersections of the lower mesh clock wiring 9'and the lower mesh clock wiring 10 'are connected by through holes and have the same potential.

By the processing of step S4, the layout tool can recognize the lower mesh clock wiring integrated with the wiring grid even inside the circuit block, and the semiconductor chip of the semiconductor chip can be recognized inside or outside the circuit block. Allows mesh clock wiring to be integrated with the wiring grid defined for the layout tool at any location.

That is, outside the circuit block, the clock signal is supplied to the flip-flop circuit arranged outside the circuit block by using the upper mesh clock wiring, and inside the circuit block, the clock signal is supplied by using the lower mesh clock wiring. A clock signal is supplied to the flip-flop circuit that constitutes the.

Returning to FIG. 1 and continuing the explanation, step S
At 5, one or more of the virtual mesh clock terminals are set as clock input terminals.

At the step S4, the clock signal is supplied from the external clock input terminal 1 shown in FIG. 2 to the upper mesh clock wiring, and further, the clock signal is supplied to the lower mesh clock wiring via the virtual mesh clock terminal. Since the lower mesh clock wiring and the clock signal line are not connected, the clock signal is not supplied to the clock input terminal of the flip-flop circuit which constitutes the circuit block as it is.

Therefore, by setting one or more of the virtual mesh clock terminals as clock input terminals in step S5, step S6 to be described next.
In this process, wiring is performed so that the clock input terminal of the flip-flop circuit forming the circuit block and the lower mesh clock wiring are connected, and the external clock input terminal 1 → root clock buffer → upper mesh clock wiring → virtual mesh A clock signal is supplied in the order of clock terminal → lower mesh clock wiring → clock wiring → clock input terminal of a flip-flop circuit forming a circuit block.

More specifically, the clock input terminal 6 of the circuit block 3 shown in FIG. 3B is set to the virtual mesh clock terminal 11A shown in FIG. 3C. That is, with this setting, 11A is recognized as a virtual mesh clock terminal that connects the upper mesh clock wiring and the lower mesh clock wiring, and is also recognized as a clock input terminal that supplies a clock signal to the flip-flop circuit that constitutes the circuit block 3. To be done.

Next, in step S6 of FIG. 1, a clock signal is supplied from the lower mesh clock wiring to the flip-flop circuit forming the circuit block in the circuit block, and a clock distribution process is performed so as to minimize the clock skew. .

Specifically, the clock buffer is inserted and arranged and the clock wiring length is adjusted so that the delay values from the lower mesh clock wiring to the flip-flop circuit become equal.

At this time, the clock skew is minimized not only in the circuit block but also in the clock skew from the external clock input terminal 1 shown in FIG. 2 to the flip-flop circuit constituting each circuit block. Clock distribution processing is performed in the circuit block so as to minimize the clock.

That is, τ (outer) is the delay value from the external clock input terminal to the clock input terminal of the circuit block, and τ (inner) is the delay from the clock input terminal of the circuit block to the flip-flop circuit forming the circuit block. If the value is set, the process of inserting and arranging the clock buffer in the circuit block and the clock wiring having the delay adjusted clock wiring length are set so that τ (outer) + τ (inner) is constant in all the circuit blocks. Is generated.

Next, the process of step S6 will be specifically described with reference to FIGS. 4 (a) to 4 (c).
Flip-flop circuit 13 arranged in the circuit block 3
13 is a layout diagram showing A, 13B to 13E, a clock input terminal 6, and virtual wirings 12A to 12E connecting the clock input terminal 6 and the flip-flop circuits 13A to 13E.

FIG. 4B shows the lower mesh clock wirings 9'and 10 'generated in step S4 of FIG.
It is a layout diagram showing a virtual mesh clock terminal 11A set as the clock input terminal 6 in step S5.

4C, the clock buffer 14A inserted and arranged so that the delay values from the clock input terminal 6 to the flip-flop circuits 13A to 13E forming the circuit block 3 are equal in step S6.
14B and 14C, a clock wiring 15A connecting the clock buffer 14A and the flip-flop circuits 13D and 13E, and a clock wiring 15B connecting the clock buffer 14B and the flip-flop circuits 13A and 13B.

Needless to say, the clock buffer 14A
14C and the clock wirings 15A and 15B are inserted and arranged so that the delay values from the clock input terminal 6 to the flip-flop circuits 13A to 13E are equal, but at the same time, the external clock input terminal 1 shown in FIG. To the flip-flop circuits forming the respective circuit blocks 3 to 5, clock distribution processing within the circuit block, that is, insertion and placement of the clock buffers 14A to 14C and delay in the circuit block 3 are performed. The clock wirings 15A and 15B having the adjusted clock wiring length are generated.

In the above, as shown in FIG. 2A, the hierarchy is the semiconductor chip level and 2 of the circuit blocks 3-5.
Although the case of the hierarchy has been described, the circuit blocks 3 to 5 are lower circuit blocks 31 to 3 m (m is an integer of 2 or more),
The present invention can be similarly applied to the case of 51 to 5n (n is an integer of 2 or more). That is, the circuit blocks 3 to 5
1 is applied to generate mesh clock wiring, and circuit blocks 31 to 3m and 51 to 5n are generated.
Then, the processing from step S3 is performed.

In the case where the number of layers is further increased, the layered upper mesh clock wiring and the layered lower mesh clock wiring connected to this upper layer mesh clock wiring are generated by the same method, and the present invention is implemented. Can be applied.

Although the upper mesh clock wiring and the lower mesh clock signal wiring have been described as being in the same wiring layer, they may not be in the same layer. In this case, a through hole for connecting the upper mesh clock wiring and the lower mesh clock wiring is provided so that the clock signal propagates from the upper mesh clock wiring to the lower mesh clock wiring.

[0058]

As described above, the clock wiring method for a semiconductor integrated circuit and the semiconductor integrated circuit according to the present invention generate a mesh clock wiring corresponding to the hierarchical structure of the layout while maintaining the hierarchical structure of the layout. Then, a clock signal is transmitted from the external clock terminal to the lower mesh clock wiring by using the generated mesh clock wiring, and finally in the lowest circuit block, the flip-flops forming all the circuit blocks from the external clock input terminal are transmitted. The clock distribution processing is performed so that the clock skew to the flip-flop circuit is minimized, and the clock signal is supplied to the flip-flop circuit that constitutes the circuit block.

Therefore, since the clock signal propagates to the flip-flop circuit at the end via the low resistance mesh clock wiring, the fluctuation of the clock skew due to the manufacturing process can be reduced.

Further, since the clock wiring method for the semiconductor integrated circuit according to the present invention performs the processing while maintaining the hierarchical structure of the layout, the processing amount of the computer is greatly increased as compared with the conventional method of developing and processing the layout hierarchy. Can be reduced and the design period can be shortened.

Further, since the required clock skew can be realized by the unified design method, there is an effect that the design period can be shortened without repeating the design again and again to satisfy the clock skew.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a clock wiring method for a semiconductor integrated circuit of the present invention.

FIG. 2A is a part of circuit connection information for specifically explaining a clock wiring method for a semiconductor integrated circuit according to the present invention and a semiconductor integrated circuit according to the present invention using the same. 2 (b) is a layout diagram showing the circuit blocks arranged in step S1 of FIG. 1, the upper mesh clock wiring generated in step S2, and virtual wiring connecting the root clock buffer and the clock input terminal. is there.

FIG. 3 is a layout diagram for specifically explaining the clock wiring method of the semiconductor integrated circuit of the present invention.

FIG. 4 is a layout diagram for specifically explaining the clock wiring method of the semiconductor integrated circuit of the present invention.

FIG. 5 is a layout diagram of a semiconductor chip for explaining a clock wiring method described in Japanese Patent Laid-Open No. 2001-125937.

FIG. 6 is a layout diagram of a semiconductor chip for explaining a clock wiring method described in Japanese Patent Laid-Open No. 3-232267.

[Explanation of symbols]

1 External Clock Input Terminal 1 ', 59 Root Clock Buffer 2 Clock Signal Line 2', 12A-12E Virtual Wiring 3-5, 54-56 Circuit Block 6-8 Clock Input Terminal 9, 10 Upper Mesh Clock Wiring 9 ', 10 'Lower-order mesh clock wiring 11, 11A Virtual mesh clock terminals 13A to 13E, 57, 64 Flip-flop circuits 14A, 14B, 14C, 54' to 56 ', 510, 5
51, 552, 561, 562, 5611-5614,
63 clock buffers 15A, 15B, 58, 511 clock wiring 51, 61, 101 semiconductor chips 52, 102 input / output buffer 53 internal area 62 mesh clock wiring 100 circuit connection information

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F038 CD06 CD08 CD09 EZ09 EZ10                       EZ20                 5F064 BB19 BB26 DD03 EE12 EE22                       EE47 EE54 EE58 HH09 HH10                 5J042 BA02 CA00 CA12 CA15 DA00                 5J056 AA39 BB00 BB59 CC00 CC05                       CC14 EE00 FF01 HH03 KK00                       KK02

Claims (6)

[Claims] 1. A first step of arranging a circuit block constituting the semiconductor integrated circuit on a semiconductor chip based on circuit connection information of the semiconductor integrated circuit, and an external clock signal propagating on the semiconductor chip. A second step of generating a lattice-shaped upper mesh clock wiring, and changing an attribute of the upper mesh clock wiring on the circuit block to generate a lower mesh clock wiring from the upper mesh clock wiring on the circuit block And a third step of connecting the upper mesh clock wiring and the lower mesh clock wiring, and setting a wiring grid for the lower mesh clock wiring, and one or more of the lower mesh clock wirings in the circuit. A fourth step of setting as a clock signal line input to the block; A clock buffer is inserted and arranged between a flip-flop circuit forming the clock and the lower mesh clock wiring, and a wiring is provided between the clock buffer and the flip-flop circuit and between the clock buffer and the lower mesh clock wiring. A method of designing a clock wiring for a semiconductor integrated circuit, comprising: 2. The upper mesh clock wiring in the horizontal direction and the lower mesh clock wiring, and the upper mesh clock wiring in the vertical direction and the lower mesh clock wiring are in the same wiring layer, respectively. 2. A method for designing a clock wiring of a semiconductor integrated circuit according to 1. 3. A through hole for connecting the lower mesh clock wiring and the lower mesh clock wiring in the vertical direction at an intersection of the lower mesh clock wiring in the horizontal direction and the lower mesh clock wiring in the vertical direction. The clock wiring design method for a semiconductor integrated circuit according to claim 1, wherein the clock wiring design method is provided. 4. A first step of arranging a circuit block constituting the semiconductor integrated circuit on a semiconductor chip based on circuit connection information of the semiconductor integrated circuit, and a clock signal from the outside propagates on the semiconductor chip. A second step of generating a lattice-shaped upper mesh clock wiring, and a third step of generating a virtual mesh clock terminal at the intersection of the upper mesh clock wiring and the outer shape of the circuit block.
And a wiring grid is set so as to pass through the virtual mesh clock terminal, the attribute of the upper mesh clock wiring on the circuit block is changed, and the upper mesh clock wiring on the circuit block is changed to the lower mesh. A fourth step of generating a clock wire and connecting the upper mesh clock wire and the lower mesh clock wire, and setting one or more of the virtual mesh clock terminals as clock input terminals for inputting to the circuit block A fifth step, inserting and arranging a clock buffer between the flip-flop circuit forming the circuit block and the lower mesh clock wiring, between the clock buffer and the flip-flop circuit, and between the clock buffer and the lower mesh clock. Wiring between wiring Clock wiring designing method of a semiconductor integrated circuit comprising: the sixth step, the. 5. In the sixth step, the clock buffer placement process and the lower order process are performed so that a delay value of a clock signal from the virtual mesh clock terminal to the flip-flop circuit becomes constant in the circuit block. 5. The method of designing a clock wiring of a semiconductor integrated circuit according to claim 4, wherein the wiring processing of the clock wiring from the clock mesh wiring to the flip-flop circuit is performed. 6. A circuit block arranged on a semiconductor chip, an upper mesh clock wiring provided on the semiconductor chip in a grid pattern for propagating an external clock signal, and the upper mesh clock on the circuit block. A lower mesh clock wiring generated from the upper mesh clock wiring on the circuit block by changing a wiring attribute; the upper mesh clock wiring and the lower mesh clock wiring are connected; Inserting and arranging a clock buffer connected to the lower mesh clock wiring so that the wiring skew is set for the wiring and the clock skew of the flip-flop circuit in the circuit block is within a predetermined value; Connect to the lower mesh clock wiring A semiconductor integrated circuit, wherein the wiring length of the lock wiring is adjusted.