JP4523290B2 - Cell layout, semiconductor integrated circuit device, semiconductor integrated circuit design method, and semiconductor integrated circuit semiconductor manufacturing method - Google Patents

Description

  The present invention relates to a cell layout related to a standard cell or a macro cell used for designing a semiconductor integrated circuit device, and more particularly to a cell layout of a delay cell. The present invention also relates to a semiconductor integrated circuit device using the cell layout, a semiconductor integrated circuit design method, and a semiconductor manufacturing method of the semiconductor integrated circuit.

In recent years, semiconductor integrated circuits tend to move to finer processes with higher speed and higher integration. In recent fine processes, manufacturing costs tend to increase as the process evolves due to complicated data processing processes such as optical proximity correction (OPC) processing and the increase in wiring metal layers.
Further, in a complicated mask manufacturing process or semiconductor manufacturing process, a manufacturing period from when a designer outputs layout data to an actual chip tends to increase.

  On the other hand, the design of semiconductor integrated circuits has become increasingly difficult due to the increased operating frequency and the complicated parasitic resistance and capacitance of fine processes. The use of a delay cell (buffer cell) to cope with this problem is a method already known to many semiconductor integrated circuit designers (see, for example, Patent Document 1).

  FIG. 12 shows a general cell layout of a buffer cell (delay cell) used conventionally. FIG. 12A shows a cell layout, and FIG. 12B shows a circuit diagram. 94a is an input terminal of the cell, and 94b is an output terminal. Since the input / output logic of the buffer cell is equivalent, it is often used literally as a buffer or used for delay adjustment of wiring. In automatic placement and routing, other functional cells such as inverters and NAND gates are placed, and input / output terminals of those cells are metal-wired to generate a layout from a circuit diagram. The layout of these small functional cells is the same height or an integral multiple of the basic height and is called a standard cell.

  These standard cells are placed by an automatic placement and routing tool, and a desired netlist layout is generated by wiring between terminals of the standard cells. FIG. 13 shows an example of automatic placement and routing.

FIG. 14 shows an example of delay adjustment. When it is desired to synchronize all the cells of the flip-flop circuit (FF) connected to the standard cell, a plurality of delay cells are inserted before the output cell of the standard cell, and delay adjustment is performed at the time of circuit operation verification. “Circuit operation verification” refers to post-layout simulation performed with the actual layout shape taken into account after the layout is generated, and evaluation of a semiconductor integrated circuit actually formed into a chip. For example, in the circuit configuration shown in FIG. 14A, when there is a time t _ns delay in the operation waveform CK2 at the point a due to the operation of the cell CKBF1 (FIG. 14B), a delay cell is placed before the cell CKBF1. A method of adding so as to be delayed by t _ns is used. FIG. 14C shows a circuit configuration to which this technique is applied. The delay cell is a circuit in which the two stages of the output cell preceding the cell CKBF2 generate a delay of time t _ns , and the timings of the operation waveforms CK1 and CK2 coincide. (FIG. 14D). In this case, the delay cell is composed of two stages, but there are cases where a delay of time t _ns can be obtained by one delay cell or delay cells of two or more stages are used.
The delay cell is also used for correcting timing errors such as setup and hold, and these methods are widely used among semiconductor designers.

  At this time, the layout related to FIG. 14C is improved as shown in FIG. That is, first, as shown in FIG. 15A, delay cells are arranged in advance as Delay 1 to Delay 3 (in the drawing, for convenience of explanation, the lower layer layout is eliminated and only the terminals of the delay cells are shown). . As for the delay value, it is preferable to consider the characteristics of the delay cell so that an arbitrary delay value can be obtained based on the design prediction. When the design is improved, the delay cells are used to change the wiring so as to obtain a desired result.

JP-A-4-74453

However, when such a design improvement is performed, it is necessary to change a plurality of metal wirings or via holes, that is, to change a plurality of mask layers, which directly leads to an increase in cost.
In addition, when revisions are required in places other than the delay adjustment, it is necessary to change the metal wiring for the delay adjustment.
On the other hand, the correction of the delay adjustment results in repeated semiconductor manufacturing processes even when using dummy cells, leading to an increase in TAT.

  The present invention has been made in view of the above problems in the prior art, and a cell layout capable of minimizing the change of a metal layer, a semiconductor integrated circuit device using the same, and a method for designing a semiconductor integrated circuit Another object of the present invention is to provide a semiconductor manufacturing method of a semiconductor integrated circuit.

The present invention provided to solve the above-described problems relates to a standard cell or a macro cell that is used for designing a semiconductor integrated circuit and has an input cell terminal, an output cell terminal, and a plurality of cell units that are continuously arranged. In the cell layout, to the metal layer of the cell unit, the input dummy metal wiring that crosses the metal layer and can be mutually connected to the adjacent cell unit, and the input dummy metal wiring An output dummy metal wiring to be wired and an input terminal and an output terminal provided between the input dummy metal wiring and the output dummy metal wiring are arranged, and the input dummy metal wiring and the output dummy metal wiring The input terminal of an arbitrary cell unit selected from the plurality of cell units is connected to the input cell terminal. Connected to the dummy metal wiring for output or dummy metal wiring for output, the output terminal is connected to the output dummy metal wiring or the adjacent output cell terminal, and the output dummy metal wiring is connected to the input terminal and the output terminal In this case, the function of the cell unit is used by deleting between the connection portions, and at least an input dummy metal of the cell unit selected from the plurality of cell units is an output dummy metal. The function of the cell unit is not used by preventing the output terminal from being connected to the output dummy metal wiring or the adjacent output cell terminal without being connected to the wiring. This is a cell layout.
For convenience of explanation, an input dummy metal wiring and an output dummy metal wiring are used. However, there is no clear classification, and wiring is performed for the purpose of obtaining a desired circuit configuration using both dummy metal wirings.

The cell unit has a structure in which the metal layers are stacked and the input terminal and the output terminal are connected between upper and lower metal layers, and one of the stacked metal layers is selected. in is preferably can be connected with the output dummy metal wires and the input terminals of the output terminal and the other cell units of one cell unit.
At this time, the selection of the metal layer is based on the disconnection of the connection between the metal layer selected from the output terminal of the one cell unit and the input terminal of the other cell unit and the metal layer above it. Is good.

Further, it is preferable that at least one of the cell units is a delay cell unit.
The plurality of cell units are preferably delay cell units having different delay values.

  Further, it is preferable that the standard cell or the macro cell is composed of a combination of a delay cell unit and other functional cell units.

The present invention provided to solve the problems is a semiconductor integrated circuit device on which at least one standard cell or macro cell having the cell layout according to any one of claims 1 to 6 is mounted.

The present invention provided to solve the above-described problems is a method for designing a semiconductor integrated circuit using the cell layout according to any one of claims 1 to 6 .

Moreover, this invention provided in order to solve the said subject performs the semiconductor manufacture of two semiconductor integrated circuits using the cell layout as described in any one of Claims 1-6 , and one side is a middle metal layer. A semiconductor integrated circuit semiconductor characterized in that the semiconductor manufacturing is stopped at a stage, and then the metal layer after the stopped metal layer is changed based on the evaluation result of the semiconductor integrated circuit manufactured to the other end. It is a manufacturing method.

As an effect of the present invention , according to the cell layout of the present invention, the condition of the metal wiring is changed only to the minimum necessary, and this revision has almost no influence on other portions.
For example, a clock buffer or the like often includes a delay cell for delay adjustment in the preceding stage, and by integrating them, it is possible to perform accurate delay adjustment without causing unnecessary wiring between cells. I can do it.
Further, according to the present invention, for example, in the case of a delay cell, the delay time can be changed by selecting a metal layer. That is, the timing error can be easily corrected with a small number of metal layers. In recent years, it has been possible to change the fewest metal layers in mask manufacturing, which has become increasingly expensive due to its complicated processing steps. Further, when the present invention is used, for example, when the metal layer needs to be revised at a place other than the delay adjustment, the delay of the delay cell of the present invention can be changed according to the revised layer.
In addition, the semiconductor integrated circuit manufactured up to any metal in the manufacturing process is revised with unmanufactured wiring metal from the evaluation result of the fully manufactured semiconductor integrated circuit, thereby reducing the manufacturing period of the semiconductor integrated circuit. Can be greatly shortened.
In particular, correction in the metal layer near the top layer greatly helps TAT reduction.

Embodiments of the present invention will be described below.
An example of a delay cell to which the cell layout of the present invention is applied is shown in FIG. At this time, in the lower layer structure before metal such as diffusion and poly, there is no difference from the general delay cell shown in FIG. The basic structure is a shape in which a plurality of types of delay cells are arranged side by side.

The delay cell shown in FIG. 1 has an input cell terminal 4a, an output cell terminal 4b, and a plurality of delay cell units (Delay1, Delay2, Delay3, and Delay4) arranged continuously. Each delay cell unit has an input terminal 11 and an output terminal 12.
Here, each delay unit has a delay element in which the gate width (W) and gate length (L) of the transistor are adjusted so that different delay values can be obtained. For example, in Delay 1 in FIG. 1, 0.4 ns, Delay 2 The delay value is 0.2 ns, Delay 3 is 0.15 ns, and Delay 4 is 0.1 ns. In the present invention, one delay cell unit may be one cell and a plurality of cells may be continuously arranged, or a configuration having a plurality of delay cell units as shown in FIG. 1 is a delay cell. But you can.

Regarding the cell layout according to the present invention, the metal 1 layer which is the metal layer used in the basic cell unit is as shown in FIG. That is, as shown in FIG. 2 (a), each wiring grid is classified into a power source connection, a through metal, a transistor connection, a terminal, and the like, and a cell layout as shown in FIG. 2 (b) is obtained. . The present invention is characterized in that a metal wiring (1 metal layer) has a metal wiring 1 crossing the metal layer, and the metal wiring 1 is arranged between adjacent cell units by arranging delay cell units. Thus, the metal wires 1 are connected to each other. This wiring utilization method will be described later.
In addition, although the metal wiring 1 is made into the linear shape in FIG.2 (b), it is not limited to it, A curved shape may be sufficient.

FIG. 3 shows a cross-sectional structure of the input terminal 11 and / or the output terminal 12 of the delay cell unit as a cell layout according to the present invention. In FIG. 3A, terminal mask patterns metal1 on the metal layer (metal 1 layer) to terminal mask pattern metal8 on the uppermost metal layer are stacked as the terminals of the delay cell unit, and the respective terminal mask patterns are moved up and down. It has a structure in which via holes (via1 to via7) are connected between metal layers.
In FIG. 3 (b), the terminal mask pattern metal1 on the metal layer (metal 1 layer) to the terminal mask pattern metal8 on the uppermost metal layer are stacked as the terminals of the delay cell unit as in FIG. 3 (a). Each terminal mask pattern has a structure in which upper and lower metal layers are connected by via holes (via1 to via7), but has a shape that can be cut at a hatched portion A in the drawing. Here, the two types of stacked metal structures of the present invention have been described, but the designer may freely select and use them depending on the shape to be changed.

FIG. 4 illustrates the basic form of the cell layout according to the present invention, taking as an example a metal layer of a delay cell having the input terminal 11 and / or the output terminal 12 of the laminated structure shown in FIG.
The delay cell shown in FIG. 4 has a cell layout having an input cell terminal 4a, an output cell terminal 4b, and a plurality of delay cell units (Delay1, Delay2, Delay3, and Delay4) arranged continuously.

  The metal layer of each delay cell unit includes an input dummy metal wiring Delay In (1a) that is an independent metal wiring that crosses the metal layer and is mutually connected to an adjacent cell unit, and the input Output dummy metal wire Delay Out (1b), input dummy metal wire Delay In (1a) and output dummy metal wire Delay Out (1b) The input terminal 11 and the output terminal 12 provided between are arranged in a layout. The delay cell of FIG. 4 is a basic form to the last, and the present invention is not limited to this.

  The input terminal 11 is provided for each metal layer up to the input terminal of the final delay cell unit, and the output terminal 12 is provided for each metal layer up to the output terminal of the first delay cell unit.

  At this time, if the input dummy metal wiring Delay In (1a) and the output dummy metal wiring Delay Out (1b) are wired in the minimum space from the input terminal 11 and the output terminal 12, the terminals 11 and 12 are input. There is no wiring between the dummy metal wiring Delay In (1a) and the output dummy metal wiring Delay Out (1b). Specifically, when the minimum space determined by the design rule is 0.2 μm and the minimum width is 0.3 μm, it is preferable that wiring is performed at an interval smaller than (minimum space × 2) + minimum width = 0.7 μm.

The input terminal 11 of the cell unit is connected to the input dummy metal wiring Delay In (1a) or the output dummy metal wiring Delay Out (1b) to which the input cell terminal 4a is connected, and the output terminal 12 is the output dummy metal. When the input terminal 11 and the output terminal 12 are connected, the output dummy metal wiring Delay Out (1b) is connected to the wiring Delay Out (1b) or the adjacent output cell terminal 4b. By being deleted, the function of the cell unit is used.
FIG. 5 shows an example in which the delay cell units Delay1, Delay3, and Delay4 are changed to be used based on the basic cell layout of FIG.
The input cell terminal 4a is connected to the input dummy metal wiring Delay In (1a) (C portion in the figure). Thereby, the input cell terminal 4a and the input terminal 11 of Delay 1 are connected via the input dummy metal wiring Delay In (1a). The output terminal 12 of Delay 1 is wired to the input terminal 11 of Delay 3, and the output terminal 12 of Delay 3 is wired to be connected to the input terminal 11 of Delay 4 via the output dummy metal wiring Delay Out (1 b) (FIG. Middle C part). At this time, the output dummy metal wiring Delay Out (1b) in Delay 1 is deleted up to the connection portion with the output terminal 12, and each input terminal 11 of Delay 3 and Delay 4 is connected to the input dummy metal wiring Delay In (1a). It has been deleted (B portion in the figure). Also, the metal wiring is deleted so that the output dummy metal wiring Delay Out (1b) in Delay 3 is disconnected between the connection portion of the Delay 3 with the input terminal 11 and the connection portion of the output terminal 12 (FIG. Middle B part). Furthermore, the output terminal 12 of Delay 4 is connected to the output cell terminal 4b (C portion in the figure). The portion after connection with the output terminal 12 of the output dummy metal wiring Delay Out (1b) in Delay 4 is deleted (B portion in the figure).

FIG. 6 shows an example in which the delay cell units Delay2 and Delay3 are changed to be used based on the basic cell layout of FIG.
The input cell terminal 4a is connected to the input dummy metal wiring Delay In (1a) (C portion in the figure). In the delay cell unit Delay2, the output terminal 12 is connected to the output dummy metal wiring Delay Out (1b) (C portion in the figure), and the output dummy metal wiring Delay Out (1b) is connected to the output terminal 12 The metal wiring is deleted so as to be cut before the portion (B portion in the figure). In the delay cell unit Delay3, the input terminal 11 is not connected to the input dummy metal wiring Delay In (1a) (B portion in the figure) and is connected to the output dummy metal wiring Delay Out (1b). (C portion in the figure). At this time, the metal wiring is deleted so that the output dummy metal wiring Delay Out (1b) in Delay 3 is disconnected between the connection portion with the input terminal 11 and the connection portion with the output terminal 12 (in the drawing). B part). The output cell terminal 4b is connected to the output dummy metal wiring Delay Out (1b) (C portion in the figure).

  Normally, the input of a delay cell is fixed (Tie Cell / Tie-down (up)), but the delay cell of the present invention changes the state of the cell terminal and the input terminal of the delay cell unit at the time of the basic type. There is no. That is, according to the present invention, it is possible to perform delay adjustment without changing the metal layer while leaving the wiring of the input terminal 11 of the unused delay cell unit as it is.

  On the other hand, when it is desired to control the delay value, for example, as shown in FIG. A desired delay value can be realized without changing. In this case, if a layered terminal structure is routed to the uppermost metal in advance, cutting at a metal layer at an arbitrary level is possible.

  In the above explanation diagrams, the layout of delay cells that can be changed for all metal layers in the manufacturing process has been described. However, if all the metal layers are not required, the configuration can be freely changed according to the layout. It ’s fine.

  FIG. 7 shows another example of a delay cell as a cell layout according to the present invention. The delay cell is a standard cell together with a cell such as CLKBUF, and can be realized by applying the configuration of FIG. 4 to FIG.

  FIG. 8 shows a flow of a method for designing a semiconductor integrated circuit using the cell layout of the present invention. Here, parts related to the present invention will be described.

  First, logical design is performed in step a, and layout design is performed in step b. In the layout design of step b, the design is performed using the basic delay cell layout shown in FIG. In this case, a plurality of basic delay cell layouts are prepared, and the designer can select and use a desired delay cell layout.

  After the layout design is performed, a post layout simulation taking into account the layout shape is performed (step c). The layout detected at that time is revised including the adjustment of the delay cell. Here, regarding the delay cell, it is preferable to prepare a cell layout other than the basic shape of FIG. 4 and replace it. For example, the basic delay cell layout of FIG. 4 is changed to a delay cell layout using delay cell units Delay 1, 3, 4 as shown in FIG.

  Further, this delay cell layout can be evaluated after the trial production of the semiconductor integrated circuit (step e) (step f), and the defect detected there can be replaced. At this time, it becomes possible to change the delay value of the delay cell by using only the necessary metal layer by revising the part other than the delay adjustment (step g). For example, when it is necessary to change the metal 2 as a metal layer at a place other than the delay adjustment, the revision using the delay cell of the present invention may use only the metal 2 or only the metal 3. In this case, the revision may be made by changing only the metal 3.

FIG. 9 shows a flow of a semiconductor manufacturing method of a semiconductor integrated circuit using the cell layout of the present invention.
In the trial manufacture of a semiconductor integrated circuit, the semiconductor manufacturing of two semiconductor integrated circuits is performed using the cell layout of the present invention, one of which is stopped at the middle metal layer stage (step i), and then the final of the other. The semiconductor integrated circuit manufactured up to the above is manufactured (step h) and evaluated (step l). Next, the metal layer after the metal layer that has been stopped based on the evaluation result is changed (revised) (step j), and the semiconductor integrated circuit semiconductor is manufactured (step k).

The present invention is characterized by a metal laminated structure on a terminal and a structure having a dummy wiring metal, and is not limited to the delay cell described above, but can be equivalently controlled for a normal function cell. Become.
That is, for example, as shown in FIG. 10, even in the inverter 51 in which the input terminal and the output terminal have a one-to-one relationship, the cell layout processing of the present invention is added by making the input / output of the inverter 51 into a laminated terminal shape. This makes it possible to freely add and delete inverters.

  An example of the NAND gate 52 whose input / output is not one-to-one is shown in FIG. It is preferable to apply a fixed potential to the input terminals that are no longer needed. The laminated power metal is not particularly limited to be on the power rail.

It is a figure which shows the example of a delay cell structure to which the cell layout of this invention is applied. It is a figure which shows the example of wiring grid use in the cell unit to which the cell layout of this invention is applied. FIG. 4 is a cross-sectional structure diagram of an input terminal and / or an output terminal of a delay cell unit to which the cell layout of the present invention is applied. It is a figure which shows the basic form of the cell layout which concerns on this invention. FIG. 5 is a diagram illustrating an example in which the delay cell units Delay1, Delay3, and Delay4 are changed based on the cell layout of FIG. FIG. 5 is a diagram showing an example in which the delay cell units Delay2 and Delay3 are changed based on the cell layout of FIG. It is a figure which shows the other structural example of the delay cell to which the cell layout of this invention is applied. It is a flow of the design method of a semiconductor integrated circuit using the cell layout of the present invention. It is a flow of the semiconductor manufacturing method of a semiconductor integrated circuit using the cell layout of this invention. It is a figure which shows the structural example which applied the cell layout of this invention to the inverter. It is a figure which shows the structural example which applied the cell layout of this invention to the NAND gate. It is a figure which shows the cell layout and circuit structure of the conventional delay cell. It is a figure which shows an example of the automatic placement wiring of the conventional standard cell. This is a conventional delay adjustment example (1). This is a conventional delay adjustment example (2).

Explanation of symbols

1 Metal wiring 1a Dummy metal wiring for input Delay In
1b Dummy metal wiring for output Delay Out
2,92 Contact hole 3a, 93a Metal 1 layer (VDD)
3b, 93b Metal 1 layer (GND)
4a, 94a Input cell terminal 4b, 94b Output cell terminal 5,95 N diffusion 6,96 P diffusion 7,97 Poly
8,98 Cell frame 9,99 N well 11 Input terminal 12 Output terminal 51 Inverter 52 NAND gate

Claims (9)

A cell layout relating to a standard cell or a macro cell, which is used for designing a semiconductor integrated circuit and has an input cell terminal, an output cell terminal, and a plurality of cell units arranged continuously,
An input dummy metal wiring that crosses the metal layer and can be mutually connected to the adjacent cell unit, and an output dummy wired in the same manner as the input dummy metal wiring. Metal wiring, and an input terminal and an output terminal provided between the input dummy metal wiring and the output dummy metal wiring are arranged ,
The dummy metal wiring for input and dummy metal wiring for output are
An input terminal of an arbitrary cell unit selected from the plurality of cell units is connected to an input dummy metal wiring or an output dummy metal wiring to which an input cell terminal is connected, and an output terminal is an output dummy metal wiring or When the output dummy metal wiring is connected to the adjacent output cell terminal and the input terminal and the output terminal are connected, the function of the cell unit is reduced by deleting the connection between the input terminals and the output terminals. To be used,
An input terminal of an arbitrary cell unit selected from the plurality of cell units is not connected to at least the output dummy metal wiring, and the output terminal is not connected to the output dummy metal wiring or the adjacent output cell terminal. A cell layout characterized in that the function of the cell unit is not used . The cell unit has a structure in which the metal layers are stacked and the input terminal and the output terminal are connected between upper and lower metal layers, and one of the stacked metal layers is selected by one selected metal layer. cell layout according to claim 1, wherein the output terminal and the other cell unit of the cell unit can be connected with the output dummy metal lines and the input terminal of the. The selection of the metal layer is based on disconnection of the connection between the metal layer selected from the output terminal of the one cell unit and the input terminal of the other cell unit and the metal layer above it. The cell layout according to claim 2 . At least one, cell layout according to any one of claims 1-3, characterized in that the delay cell unit of the cell unit. The cell layout according to claim 1, wherein each of the plurality of cell units is a delay cell unit having a different delay value. The standard cell or macro cell, delay cell unit and other functions claims 1-5 for any one to a cell layout, wherein the a combination of a cell unit. The semiconductor integrated circuit device at least one mounting cell standard cell or macro cell having a layout according to any one of claims 1-6. A method for designing a semiconductor integrated circuit, wherein the cell layout according to any one of claims 1 to 6 is used. The semiconductor layout of two semiconductor integrated circuits is manufactured using the cell layout according to any one of claims 1 to 6 , and one of the semiconductor manufacturing is stopped at the middle of the metal layer, and then the manufacturing of the other is completed. A method for manufacturing a semiconductor integrated circuit, comprising: changing a metal layer after the metal layer stopped based on the evaluation result of the semiconductor integrated circuit.

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