JP2006237123A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce substantially a cost in the time of a circuit correction by making a connection wiring so that existing wiring layout is not changed as much as possible and that the mask correction number of layers may be reduced as much as possible in the time of the circuit correction. <P>SOLUTION: In consideration of the circuit correction after the mask formation, as shown in an arrangement view in Fig. 6, in the same way as a conventional technology, a spare cell 101 is beforehand located to a place which does not have a function cell 102. The necessary input pin of the spare cell 101 for the circuit correction is connected to the power supply/ground wiring 202 of the upper layer in a chip, and the wiring 203 shown in Fig. 1 wired by the necessary output pin is connected to the lowest wiring layer through the top wiring layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit to which a layout design technique that can easily correct a circuit after manufacturing a mask is applied.

In developing LSIs for specific applications, the design method is mainly gate array (Gate
There are two types: an array method and a standard cell method. In the standard cell method described above, it is necessary to manufacture masks for all layers for each individual chip. When circuit correction is performed after mask creation, cell placement / wiring must be changed each time, and all layers are again formed. However, there is a problem that the development period / cost increases.

  Patent Document 1 ("Japanese Patent Laid-Open No. 11-126823") discloses a semiconductor integrated circuit that solves the above problems and a method for manufacturing the same.

In the above-mentioned Patent Document 1, as shown in FIG. 6, in a standard cell type semiconductor integrated circuit, an unwired spare cell 101 is arranged in advance in a chip 301, so that it is easy to change an aluminum wiring mask. It is described that the circuit can be changed and the circuit can be easily corrected as in the gate array system.
JP-A-11-126823

  However, the circuit correction using the above-described conventional technique has the following problems.

  In circuit correction after mask creation, a technology called ECO (Engineering Change Order) is used, in which connection information of spare cells 101 that have been inserted in advance is changed, and only the changed portions are connected while keeping existing wiring information as much as possible. However, in the normal ECO wiring process, the correction points are connected at the shortest distance, so that wiring is performed across multiple layers, and it is necessary to correct the mask of all wiring layers or multiple layers. Yes, the mask manufacturing cost for circuit correction increases.

  Therefore, the present invention was created in order to solve the above-described problems. The wiring is connected so as not to change the existing wiring shape as much as possible by circuit correction, and the number of mask correction layers at the time of circuit correction is minimized. An object of the present invention is to provide a semiconductor integrated circuit that can reduce the cost for circuit correction significantly.

  In order to achieve the above-described object, the present invention employs the technical configuration described below.

  In a semiconductor integrated circuit according to the present invention, in a standard cell type semiconductor integrated circuit, in order to stabilize the potential of a required input pin of a spare cell for circuit correction, power supply / ground wiring is wired to an upper layer in the chip. It is characterized by being connected.

  Further, the semiconductor integrated circuit according to the present invention is characterized in that, in addition to the above-described configuration, a wiring routed from the highest wiring layer to the lowest wiring layer is connected to a required output pin.

  A semiconductor integrated circuit according to the present invention is characterized in that, in the above configuration, each wiring layer is wired stepwise.

  Furthermore, the semiconductor integrated circuit according to the present invention is characterized in that, in the above configuration, when a layout technique for changing the circuit of the semiconductor integrated circuit is used, the circuit is corrected by using only the wiring layer.

  According to the semiconductor integrated circuit of the present invention, the input / output pins of the spare cell are wired in advance to each wiring layer, so that it can be reused when the circuit is modified, and one wiring layer and one contact layer can be reused. This can be realized with a two-layer mask manufacturing cost, and the cost can be greatly reduced.

  Further, by wiring the above wiring structure stepwise, it can be realized at a mask manufacturing cost of only one wiring layer, and the cost of circuit correction can be reduced to the limit.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 to 5 show examples of embodiments of the present invention. In the drawings, the same reference numerals as those in the drawings denote the same components, and the basic configuration is the same as the conventional one shown in the drawings. .
(Description of First Embodiment)

  Hereinafter, a first embodiment of a semiconductor integrated circuit using a layout for changing the circuit of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic wiring diagram of the semiconductor integrated circuit according to the first embodiment.

  As in the conventional technique, in order to consider circuit correction after mask manufacturing, as shown in the layout diagram of FIG. 6, the spare cell 101 is arranged in advance in a place without the function cell 102 and the circuit correction spare cell 101 is required. This is a semiconductor integrated circuit characterized in that various input pins are connected to a power / ground wiring 202 having a mesh wiring as shown in the power / ground wiring diagram shown in FIG.

Thus, in this embodiment, as shown in the schematic wiring diagram of the semiconductor integrated circuit of FIG. 1, the required input pins of the circuit correction spare cell 101 are connected to the power / ground wiring 202 in the upper layer in the chip. As a result, it is possible to stabilize the potential and prevent a power supply drop.
(Description of Second Embodiment)

  Hereinafter, a second embodiment of a semiconductor integrated circuit using a layout for changing the circuit of the semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

  In a spare cell similar to that of the first embodiment, the wiring 203 shown in FIG. 1 wired to the lowest wiring layer through the uppermost wiring layer is connected to a required output pin.

  Here, for example, as shown in the schematic wiring diagram of FIG. 8, when the function cells 103 and 104 are connected by the wiring 204, circuit correction is necessary after the mask is manufactured, and the function cell 103 and the function cell 104. 9 is deleted, the wiring 205 is deleted as shown in the schematic wiring diagram of FIG. 9 so that the wiring distance of the spare cell 101 of the prior art that has not been wired is minimized. Then, ECO wiring for adding the wirings 206 and 207 is performed, and it is necessary to modify all wiring layers or a plurality of wiring layers even by the best method, and the mask manufacturing cost increases.

  On the other hand, in this embodiment, ECO wiring is performed as shown in the wiring schematic diagram of FIG. If the spare cell uses the technique of the first embodiment, the connection between the function cell 103 and the spare cell 101 can be changed by adding the wiring 208 and deleting the contacts 401 and 402.

If the spare cell uses the technique of the second embodiment, the connection between the function cell 104 and the spare cell 101 can be changed by adding the wiring 209 and deleting the contact 403. In the above correction, the circuit correction is performed by manufacturing the two-layer mask of the wiring layer 2 and the contact 1 layer, and the cost for correcting the circuit can be minimized.
(Description of the third embodiment)

  Hereinafter, a third embodiment of a semiconductor integrated circuit using a layout for changing the circuit of the semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

  FIG. 2 is a schematic wiring diagram of the semiconductor integrated circuit according to the third embodiment.

  In a spare cell similar to the first and second embodiments of the present invention, a semiconductor integrated circuit is characterized in that each wiring layer is wired stepwise as shown in FIG. 2 in a wiring process.

In the present embodiment, as shown in FIG. 4, each wiring layer is wired stepwise, the wiring 210 is deleted, and the wiring 211 is added to change the wiring layer of one layer, thereby connecting information. Can be changed. Similarly, the wiring 212 can be realized by changing only the wiring layer 2 and the above circuit correction can be realized at a mask manufacturing cost of only one layer.
(Explanation of Fourth Embodiment)

  Hereinafter, a fourth embodiment of a semiconductor integrated circuit using a layout for changing the circuit of the semiconductor integrated circuit according to the present invention will be described.

  In the semiconductor integrated circuit, the circuit correction is performed using only the wirings 201 and 203 connected to the circuit correction spare cell.

  If an antenna violation problem occurs, change the connection to the antenna diode cell or higher layer to avoid the antenna violation. In the antenna avoidance method described above, at least a plurality of layers of masks must be manufactured. Here, when an antenna violation occurs in the wiring 204 in FIG. 5, if the technique of the third embodiment is used, the contacts 404 and 405 are deleted and the wiring 203 is connected to the wiring 204 as shown in FIG. 3. By connecting in this manner and deleting the wiring 213, the connection to the highest layer is realized by changing the mask manufacturing of the two layers of the wiring layer 4 and the contact 1 layer. Furthermore, if the technique of the third embodiment is used, it can be realized only by the mask manufacturing cost of the wiring layer 4.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

It is a wiring schematic diagram of a semiconductor integrated circuit in the present invention. It is a wiring schematic diagram of the semiconductor integrated circuit in the 3rd Embodiment of this invention. It is the wiring schematic diagram after ECO wiring in the 2nd Embodiment of this invention. It is the wiring schematic diagram after ECO wiring in the 3rd Embodiment of this invention. It is the wiring schematic diagram after ECO wiring in the 4th Embodiment of this invention. It is a layout view of spare cells used in the conventional technology. It is a power supply / ground wiring diagram. It is a wiring schematic diagram before circuit correction. It is the wiring schematic diagram after ECO wiring in the prior art.

Explanation of symbols

101 Spare cell 102, 103, 104 Function cell 201 Wiring connected to required input pin of spare cell 202 Power supply / ground wiring 203 Wiring connected to required output pin of spare cell 204 Existing wiring 205 Deleted in conventional technology Wirings 206, 207 In the prior art, added wirings 208, 209, 211, 212 In the present invention, added wiring 210 In the present invention, deleted wiring 301 Semiconductor integrated circuits 401, 402, 403, 404, 405 In the present invention, deleted contacts

Claims (4)

In standard cell semiconductor integrated circuits,
A semiconductor integrated circuit characterized by being connected to a power supply / ground wiring that is wired in an upper layer in a chip in order to stabilize a potential of a required input pin of a circuit correction spare cell.   2. The semiconductor integrated circuit according to claim 1, wherein in the circuit correction spare cell, a wiring that passes through the highest wiring layer and reaches the lowest wiring layer is connected to a required output pin.   3. The semiconductor integrated circuit according to claim 1, wherein each wiring layer is wired stepwise in the wiring step of the circuit correcting spare cell.   4. The circuit correction according to claim 1, wherein, when a layout technique for changing a circuit of a semiconductor integrated circuit is used, the circuit correction is performed using only the wiring connected to the circuit correction spare cell. The semiconductor integrated circuit according to Item.

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