JP5196525B2 - Version number information holding circuit and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a version number information holding circuit and a semiconductor integrated circuit, and more particularly to a version number information holding circuit for holding information indicating a version number and a semiconductor integrated circuit including such a version number information holding circuit.

  Some semiconductor integrated circuits retain version number information for version number management. For example, consider an LSI named XBX. Assume that it is necessary to change some functions of the XBX. The reason for the function change is, for example, performance improvement or defect correction. FIG. 11 shows the semiconductor integrated circuit before and after the correction. In this example, a part of the function A101 of the LSI 100 is changed to a function A′102 due to the function change. By changing the function A101 to the function A'102, when the inside of the LSI 100 called XBX is viewed, it becomes another LSI before and after the function change.

  However, in a system in which the LSI 100 called XBX is incorporated, the LSI 100 called XBX is not a completely different LSI. The operation of the LSI 100 required as a system means that, for example, if the reason for function change is performance improvement, the performance is improved, and if the reason for function change is defect correction, the operation becomes normal. When such a function change is performed, the name of the LSI called XBX is generally not changed before and after the function change.

  However, even if the LSI names are the same, it is necessary to distinguish between the LSI 100 before and after the function change. For example, if the reason for the function change is performance improvement, there is a performance variation in the system in which the LSI 100 is incorporated, and if the XBX with improved performance is essential in the higher version, the installed XBX is the function improvement version. It is necessary to confirm that it is XBX. Also, in the case where a function change has been made due to a defect correction, in order to avoid the problem, in the XBX-equipped system, the processing related to function A is suppressed in the XBX before the function change, and not suppressed in the XBX after the change. The operation of switching the above process by software or the like is performed.

  As a means for distinguishing LSIs having the same name and different functions, there is a method of retaining the LSI version number 103 in the LSI. The version number 103 can be referred to from the outside. In the example of FIG. 11, the version number 103 is defined as “0000” before the function change, and the version number 103 is set to “0001” after the function change. In this case, the XBX-equipped system refers to the version number 103 so that the version number is “0000”, that is, the XBX having the function A101, or the version number is “0001”, that is, the function A′102. Whether it is XBX can be determined, and the operation can be switched according to the version number. In this way, by holding the version number 103 in the LSI 100 and updating the version number 103 in accordance with the function change, LSIs having the same name and different functions can be distinguished.

  Next, a method for realizing the function change of the LSI by correcting the wiring layer will be described. FIG. 12 shows an example of the structure of the ASIC LSI. The LSI has a plurality of layers. These layers can be divided into two, a base layer and a wiring layer. In FIG. 12, Layer 0 is a base and Layers 1 to 4 are wiring layers. Actually, there are interlayer wirings connecting the layers, but this is omitted in the figure. In Layer 0, which is the base, there is a circuit that forms a logic called a function block. It is the wiring layers from Layers 1 to 4 that connect the wirings connecting these logic circuits. In the wiring layer, the direction in which the wiring is drawn is usually determined for each layer. In the example of FIG. 12, Layer1 and Layer3 are wiring layers for the X direction, and Layer2 and Layer4 are wiring layers for the Y direction. When the LSI is formed, wiring is performed by combining the layer for wiring in the X direction and the layer for wiring in the Y direction.

  An LSI is manufactured for each of a plurality of layers constituting the LSI. For each layer to be manufactured, there are manufacturing data and manufacturing equipment. For this reason, it is possible to modify the LSI without changing the manufacturing data and the equipment for manufacturing only for a specific layer and changing the other layers. In this method, the time and cost for designing and the time and cost for re-creating the manufacturing equipment can be reduced as compared with the case where the LSI is completely redesigned. In addition, for example, at the stage of creating up to the base layer before correction, by using the manufacturing equipment after the creation of the wiring layer, it is possible to use the LSI being manufactured before the correction for the LSI manufacturing after the correction There is.

  13 and 14 show a part of the circuit configuration of the LSI before and after the function correction. Hereinafter, an example in which the function of an LSI is changed by correcting a wiring layer will be described with reference to FIGS. This function change is a function change that changes a logical defect. The circuit shown in FIG. 13 is a circuit having a logical defect. The OR circuit 211 calculates the logical sum of the output of the register A201 and the output of the register B202. The logical sum output from the OR circuit 211 is set in the register D204. The AND circuit 212 calculates the logical product of the output of the register B202 and the output of the register C203. The result of the logical product output from the AND circuit 212 is set in the register E205.

  Assume that a logical failure is found after an LSI is manufactured with the logic shown in FIG. The content of the defect is that the data to be set in the register D204 is not the result of the logical sum of the output of the register A201 and the output of the register B202, but the result of the logical product of the output of the register B202 and the output of the register C203. The content is a logical sum with the output of the register A201. To correct the problem, an AND circuit that outputs a logical product of the output of the register B202 and the output of the register C203 is necessary. The circuit shown in FIG. 13 already has an AND circuit 212 that outputs a logical product of the output of the register B202 and the output of the register C203. In this case, the defect can be corrected only by correcting the wiring without adding an AND circuit to the base layer.

  FIG. 14 shows the circuit connection after the defect correction. 13 differs from the circuit shown in FIG. 13 in that the signal line connecting the register B 202 and the input of the OR circuit 211 is deleted, and a branch is provided in the output signal line of the AND circuit 212. The signal line which connects and is added. In the modification from the logic shown in FIG. 13 to the logic shown in FIG. 14, it is not necessary to increase the number of registers and logic circuits, and it is not necessary to change the underlying layer. Therefore, there is no need to redesign the underlayer and recreate production equipment. That is, the LSI substrate manufactured with the logic of FIG. 13 can be used as the substrate manufactured with the logic of FIG.

  When changing the function of a semiconductor integrated circuit, it is desirable to make corrections by a method that requires a smaller number of wiring layers to be corrected in consideration of the time and cost required for redesigning the wiring layers. In particular, in LSI design where the manufacturing process has been miniaturized in recent years, it takes a very large cost to create a reticle, which is the manufacturing equipment for each wiring layer. Directly connected to

  Here, in addition to the correction of the problem location that caused the correction, the problem is that the problem in realizing the change in the LSI function due to the correction of the wiring layer by changing the number of layers is as small as possible. It is necessary. For example, in the case where the function is changed by correcting the wiring in an LSI having four wiring layers as shown in FIG. 12, the problem that was the cause of the correction can be corrected in two layers of Layer 3 and Layer 4. Suppose. Even in this case, if the revision of Layer 1 and Layer 2 is required when updating the version number, the number of layers that need to be corrected becomes four, and the cost required for the correction increases.

  FIG. 15 shows the configuration of the version number information holding circuit in the related art. The version number is assumed to be “0” to “15”. The version number information holding circuit has HW revision bits 0 to 3 for holding 4-bit information. Each HW registration bit is configured by an F / F (flip-flop) and is connected to either the 0 clamp source 52 or the 1 clamp source 50. In FIG. 15, each HW revision bit is connected to the 0 clamp source 52, and the 4-bit information output by the HW revision bits 0 to 3 is “0000”. The HW revision output control unit 53 reads the values of the HW revision bits 0 to 3 and outputs a value corresponding to the read 4-bit information to the logic in the LSI or outside the LSI. In FIG. 15, since the 4-bit information is “0000”, the version number “0” is output.

  When updating the version number, the version number is set to “1”. That is, the value of the HW revision bit 3 is set to “1”, and the 4-bit information output from the HW revision bits 0 to 3 is set to “0001”. In order to set the value of the HW revision bit 3 to “1”, one clamp source that outputs “1” is required. In the current LSI design that synthesizes a circuit with a tool based on the source described in RTL, the clamp source is likely to exist in any part of the LSI. Often, one clamp source for logic can be used. In FIG. 15, since one clamp source 50 used by the other logic 51 exists in the vicinity of the circuit, this can be used.

  FIG. 16 shows a version number information holding circuit after the version number is updated. From the state shown in FIG. 15, the wiring that connects the 0 clamp source 52 and the HW revision bit 3 is deleted, and instead, the branch from the output signal wiring of the 1 clamp source 50 is connected to the HW revision bit 3. As a result, the 4-bit information read by the HW revision output control unit 53 becomes “0001”, and the HW revision output unit 53 outputs the version number “1”.

  In the above example, since the version number is updated from “0” to “1”, it is necessary to change the connection destination only for one bit of the HW revision bit 3 and the clamp source to be searched in the vicinity is 1 Only the clamp source. However, for example, considering an update from the version number “7” to “8”, in that case, it is necessary to update from “0111” to “1000”, and it is necessary to correct all of the HW revision bits. In FIG. 15, the output of the 0 clamp source 52 is commonly connected to each HW revision bit, but this is not necessarily the case, and all bits are connected to independent clamp sources. Sometimes. Therefore, in such a version number information holding circuit, there is no guarantee that the revision layer itself for version number update can be reduced even if an attempt is made to change the function of the LSI by correcting the wiring layer with as few layers as possible. Further, since the revision layer for version number update is determined according to the completed circuit, there is no guarantee that the version revision can be performed using the same layer as the revision layer for the function change that caused the version number to increase.

  Japanese Patent Application Laid-Open No. 2004-151867 describes version number information management that can update version number information by modifying a wiring layer that is the same layer as the wiring layer that is changed when the function is changed. FIG. 17 shows a version number information holding circuit described in Patent Document 1. This version number information holding circuit includes three version number information setting registers 54, a version number information encoding unit 56, and a version number information output unit 58. The version number information holding circuit includes a zero clamp source 52 and a one clamp source 50 corresponding to each version number information setting register 54. In the initial state, that is, in the state of the version number “0”, each version number information setting register 54 is connected to the 0 clamp source 52. The one clamp source 50 is connected to the input circuit 55 in advance.

  The version number information encoding unit 56 outputs 2-bit data (b0, b1) corresponding to the combination (r1, r2, r3) of the three version number information setting registers 54. FIG. 18 shows combinations of input data (r1, r2, r3) and output data (b0, b1) in the version number information encoding unit 56. In FIG. C. Represents Don't Care and indicates that it does not depend on the input value. In the initial state, since each version number information setting register 54 is connected to the 0 clamp source 52, the version number information encoding unit 56 outputs b0 = 0 and b1 = 0. The version number information output unit 58 receives the 2-bit data “00” output from the version number information encoding unit 56 via the version number information storage register 57 and receives the version number information “0” corresponding to “00”. Output.

  When the version number information is updated in accordance with the change in the function of the LSI, the connection destination of the version number information setting register 54 is changed from the 0 clamp source 52 to the 1 clamp source 50. When changing the function of an LSI by correcting the wiring layer, in order to realize the function change and update of the version number information with the smallest possible number of wiring layers, no matter which wiring layer is used for the function change, that layer It is necessary to ensure that the version information is updated at the same level. Therefore, the wiring between the 0 clamp source 52 and the version number information setting register 54 and the wiring between the 1 clamp source 50 and the input circuit 55 are parallel to each other and use all the wiring layers. And wire. In this way, the connection destination of the version number information setting register 54 can be switched from the 0 clamp source 52 to the 1 clamp source 50 in any layer.

  For example, when the number of wiring layers is four, the wiring is lifted from the 0 clamp source 52 to the fourth layer by the wiring of the first layer, the second layer, the third layer, and the fourth layer. The version number information setting register 54 is connected by wiring of the third layer, the second layer, and the first layer. Further, the wiring is lifted up to the fourth layer from the one clamp source 50 by the first layer, the second layer, the third layer, and the fourth layer, and then the third layer, the second layer, and the first layer are wired. Thus, the input circuit 55 is connected. At this time, in each layer, the wiring from the 0 clamp source 52 to the version number setting register 54 and the wiring from the 1 clamp source 50 to the input circuit 55 are wired in parallel.

  When the version number information is updated along with the modification of the function of the LSI, the wiring from the 0 clamp source 52 to the version number information setting register 54, and the 1 clamp source 50 to the input circuit 55 in an arbitrary wiring layer. The connection destination of the version number information setting register 54 is changed to the 1 clamp source 50 and the connection destination of the input circuit 55 is changed to the 0 clamp source 52 by cutting the wiring up to and changing the wiring in the wiring layer. . For example, the connection destination of the version number information setting register 54 corresponding to r1 is switched to one clamp source 50. In this case, the version number information encoding unit 56 outputs b0 = 0 and b1 = 1, and the version number information output unit 58 outputs version number information “1” corresponding to “01”. After that, when there is a further function modification of the LSI and the connection destination of the version number information setting register 54 corresponding to r2 is switched to 1 clamp source 50, the version number information encoding unit 56 sets b0 = 1 and b1 = 0. The version number information output unit 58 outputs the version number information “2” corresponding to “10”.

  In Patent Document 1, the wiring from the 0 clamp source 52 to the version number information setting register 54 and the wiring from the 1 clamp source 50 to the input circuit 55 are parallel to each other and all layers of the wiring layer are used. Wiring. Therefore, the connection destination of the version number information setting register 54 can be switched from the 0 clamp source 52 to the 1 clamp source 50 by correcting the wiring of any one wiring layer. Therefore, when the function of the LSI is changed by correcting the wiring layer, the version number information can be updated by using the wiring layer that needs to be corrected by the function change.

JP-A-2005-116902

  In Patent Document 1, the combination of the value of the version number information setting register 54 and the combination of the version number information (2-bit data b0, b1) is determined by the version number information encoding unit 56 formed in the base layer. . For this reason, version numbers other than the version number information created in the version number information encoding unit 56 cannot be generated, and versatility is low. For example, when a version number information holding circuit is mounted from an intermediate version, it is necessary to create the version number information encoding unit 56 according to the version. Therefore, for example, the version number information holding circuit having the version number information encoding unit 56 in which the version number “0” is set as the initial version number can be mounted only on the LSI having the version number “0”. Cannot be reused with a version of LSI.

  An object of the present invention is to provide a version number information holding circuit capable of changing the version number from an arbitrary initial version number, and a semiconductor integrated circuit having such a version number information holding circuit.

  In order to achieve the above object, a version number information holding circuit according to the present invention is a version number information holding circuit mounted on a semiconductor integrated circuit, and includes an initial version number information section for outputting an initial version number, and the initial version number. An adder that outputs a version number obtained by adding a predetermined number to the number, and outputs either the output of the initial version number information unit or the version number output by the adder according to the output of the condition setting unit that holds selection information And a version number output unit.

  A version number information holding circuit according to the present invention is a version number information holding circuit mounted on a semiconductor integrated circuit, wherein an initial version number information section for outputting an initial version number, and N is a natural number of 2 or more, the initial version In accordance with the outputs of the first to Nth adders for adding 1 to N to the numbers and the first to Nth condition setting units for holding the first to Nth selection information, respectively, the initial version number, or And a version number output unit for outputting any one of the outputs of the first to Nth adders.

The version number information holding circuit according to the present invention is a version number information holding circuit mounted on a semiconductor integrated circuit, wherein an initial version number information unit for outputting an initial version number, and N is a natural number of 2 or more, An adder that outputs a version number obtained by adding 1 to N to the initial version number in accordance with outputs of the first to Nth condition setting units that hold the 1st to Nth selection information. And

  A semiconductor integrated circuit according to the present invention has the version number information holding circuit according to the present invention.

  In the version number information holding circuit of the present invention, the version number can be changed from an arbitrary initial version number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a version number information holding circuit according to the first embodiment of the present invention. The version number information holding circuit includes 4-bit initial version number information (HW revision bits 0 to 3) 13, an adder 20, a selector 21, a selection condition holding FF 12, and an HW revision output control unit 22. In this embodiment, the version number output from the version number information holding circuit is assumed to be a value from “0” to “15”, and the number of bits of the HW revision input to the HW revision output control unit 22 is 4 bits. Yes. The version number information holding circuit is mounted on the semiconductor integrated circuit and outputs version number information.

  The initial version number information 13 has four HW revision bits 0 to 3 composed of FFs, and outputs the initial version number. Each HW revision bit of the initial version number information 13 is connected to the 0 clamp source 10 or the 1 clamp source 11. In FIG. 1, each HW revision bit is connected to the 0 clamp source 17 in order to set the initial version number output by the initial version number information 13 to “0” (binary notation “0000”). The initial version number is not limited to “0”, and an arbitrary value can be set. For example, if the initial version number is “7” (binary notation “0111”), connect HW revision bit 0 to 0 clamp source 17 and connect HW revision bits 1 to 3 to one nearby clamp source. That's fine.

  The adder 20 adds a predetermined number to the output value of the initial version number information 13 and outputs the result. Usually, in the update of the version number, the version number obtained by adding 1 to the version number before the update becomes the version number after the update, and therefore the predetermined number added by the adder 20 may be “1”. For example, when the output value of the initial version number information 13 is “0000” in binary notation, the adder 20 outputs “0001”. The selector 21 and the HW revision output control unit 22 constitute a version number output unit. The selector 21 inputs the output value of the initial version number information 13 and the output value of the adder 20 and selects and outputs either of them. The selection condition holding FF 12 is connected to the 0 clamp source 10 or the 1 clamp source 11. The selector 21 determines which of the two input values to select depending on whether the output of the selection condition holding FF 12 is “1” or “0”. The HW revision output control unit 22 converts the output value of the initial version number information 13 input via the selector 21 or the version number (HW revision) based on the output value of the adder 20 into a logic unit that uses the version number, And output to the outside of the semiconductor integrated circuit.

  In the example of FIG. 1, the selector 21 selects the output value of the initial version number information 13 when the output of the select condition holding FF 12 is “0”, and the adder when the output of the select condition holding FF 12 is “1”. Select 20 outputs. In an initial state in which the version number is not corrected, the select condition holding FF 12 is connected to the 0 clamp source 10 via the wiring 14 so that the selector 21 outputs the initial version number information 13. For one clamp source 11, only the output wiring 15 is provided and the connection destination is left open. In this state, the HW revision output control unit 22 outputs the version number “0” corresponding to the output value “0000” of the initial version number information 13.

  FIG. 2 shows a version number information holding circuit after the LSI version number information is updated by wiring correction. When updating the version number information, in order to set the output value of the select condition holding FF 12 to “1”, the wiring connecting the select condition holding FF 12 and the 0 clamp source 10 is cut, and the select condition holding FF 12 is set to 1 clamp. Connect to the output wiring of the source 11. For the 0 clamp source 10, the output wiring is open. When the output value of the selection condition holding FF 12 becomes “1”, the selector 21 outputs the output value “0001” of the adder 20 to the HW revision output control unit 22. The HW revision output control unit 22 outputs the version number “1” corresponding to “0001” input via the selector 21, thereby updating the version number.

  FIG. 3 shows the output wiring of the 0 clamp source 10 and the output wiring of the 1 clamp source 11 before the wiring correction. The output wiring 14 of the 0 clamp source 10 constitutes a wiring of a first wiring group in which wirings of a plurality of wiring layers are connected by via plugs, and the potential (first output) output from the 0 clamp source 10 to the selection condition holding FF 12. Potential). Similarly to the output wiring 14 of the 0 clamp source 10, the output wiring 15 of the 1 clamp source 11 constitutes a wiring of a second wiring group in which wirings of a plurality of wiring layers are connected by via plugs. Although the output potential (second potential) of the one clamp source 11 is applied to the output wiring 15 of the one clamp source 11, the output (connection destination) is open.

  The output wiring 14 of the 0 clamp source 10 and the output wiring 15 of the 1 clamp source 11 consider changing the connection destination of the selection condition holding FF 12 from the 0 clamp source 10 to the 1 clamp source 11 when correcting the version number. Then, they are arranged parallel to each other. In addition, when switching the connection destination of the selection condition holding FF 12, wiring is performed using all wiring layers so that connection switching is possible regardless of which wiring layer is used. Here, “all wiring layers” means all wiring layers (user wiring) that a user can arbitrarily draw wirings in designing a semiconductor integrated circuit. For a wiring layer that is used fixedly, such as a wiring layer that performs power supply wiring and a wiring layer that performs clock distribution, the output wiring 14 of the 0 clamp source 10 and the output wiring 15 of the 1 clamp source 11 are passed through the layers. There is no need.

  In FIG. 3, the number of wiring layers is four. Each wiring layer has a predetermined wiring direction. In FIG. 3, the first layer (Layer 1) and the third layer (Layer 3) are wiring layers wired in the Y direction, and the second layer (Layer 2) and the fourth layer (Layer 4) are wirings wired in the X direction. Is a layer. A dotted line (grid) shown in FIG. 3 indicates a position where wiring can be drawn in the layout design. The output wiring 14 of the 0 clamp source 10 and the output wiring 15 of the 1 clamp source arranged in parallel are arranged at least one place in each layer as shown by an ellipse in FIG. 3 in consideration of wiring correction. It has a portion wired with a wiring length crossing at least two dotted lines indicating possible positions.

  4 to 7 show the output wiring of the 0 clamp source 10 and the output wiring of the 1 clamp source 11 after the wiring correction, respectively. The connection destination of the selection condition holding FF 12 is switched in any one of the four wiring layers. FIG. 4 is an example in which wiring correction is performed in the first layer. In the wiring correction, the output wiring 15 (FIG. 3) of one clamp source 11 is divided into two wirings 15-1 and 15-2 in the first layer. Similarly, the output wiring 14 of the 0 clamp source 10 is divided into two in the first layer, that is, wiring 14-1 and wiring 14-2. The division of the wirings 14 and 15 in the first layer is performed at a portion wired with a wiring length considering wiring correction (a portion surrounded by an ellipse in FIG. 3).

  In the first layer, the wiring portions divided into two are connected to each other, the folded portion from the first wiring group to the second wiring group, and the folding from the second wiring group to the first wiring group. Forming part. More specifically, the wiring 15-1 connected to one clamp source 11 and the wiring 14-1 connected to the selection condition holding FF 12 are connected by the wiring 16-1 in the X direction to form a folded portion. To do. As a result, the one clamp source 11 and the select condition holding FF 12 are connected by the first-layer wirings 15-1, 16-1, and 14-1. Further, the remaining divided wiring 15-2 and wiring 14-2 are connected by a wiring 16-2 in the X direction. By doing in this way, the output wiring of the 0 clamp source 10 comprised by wiring 14-2, 16-2, 15-2 becomes open. The reason why the wiring 15-2 and the wiring 14-2 are connected by the wiring 16-2 is to prevent the wiring 15-2 from being in a floating state.

  FIG. 5 shows an example in which wiring correction is performed in the second layer. The difference from FIG. 4 is that in the second layer, the output wiring 14 of the 0 clamp source 10 and the output wiring 15 of the 1 clamp source 11 are divided into two, and the second layer wiring 16-1 extending in the Y direction, In 16-2, the wiring 14-1 and the wiring 15-1, and the wiring 14-2 and the wiring 15-2 are connected. FIG. 6 is an example in which wiring correction is performed in the third layer, and FIG. 7 is an example in which wiring correction is performed in the fourth layer. In any example, by changing only one specific layer, the selection condition holding FF 12 and the 1 clamp source 11 can be connected, and the output of the 0 clamp source 10 can be opened.

  In this embodiment, the selector 21 switches the value output by the initial version number information 13 and the value output by the adder 20 to the value output by the initial version number information 13 to the HW revision output control unit 22. Enter. The initial version number information 13 can be set to any value depending on the combination of the values of each HW revision bit. In this embodiment, the version number can be increased by one from any initial version number by switching the value of the selection condition holding FF 12 that determines the selection condition of the selector 21, and a versatile version number information holding circuit is provided. realizable. That is, by setting the initial version number information 13 to a desired version number, an update from the version number “0” to “1” and an update from the version number “7” to “8” can be supported. Therefore, it is possible to realize a versatile version number information holding circuit capable of changing the version number information regardless of the version number before correction.

  In this embodiment, in the initial state, the wiring from the selection condition holding FF 12 to the 0 clamp source 10 and the output wiring of the 1 clamp source 11 are wired in parallel to each other and using all wiring layers. ing. In this way, the connection destination of the selection condition holding FF 12 can be switched by correcting any one of the plurality of wiring layers. Therefore, when changing the LSI function by correcting the wiring in the wiring layer, the wiring layer used for updating the version number information is the same wiring layer as the wiring layer corrected by the LSI function change that caused the version number to be increased. The version number information can be updated at a low cost.

  FIG. 8 shows a version number information holding circuit according to the second embodiment of the present invention. In the first embodiment, it is assumed that the version number is updated once. In this embodiment, it is possible to cope with a plurality of version number updates. In addition to the configuration of the first embodiment, the version number information holding circuit of this embodiment includes an adder 20b that outputs “2” added to the output value of the initial version number information 13 and the output value of the selection condition holding FF 12b. The selector 21b for switching the output of the selector 21a and the output of the adder 20b in response to the output is provided. The wiring 14b between the selection condition holding FF 12b and the 0 clamp source 10b and the output wiring 15b of the 1 clamp source 11b are the wiring 14 between the selection condition holding FF 12 and the 0 clamp source 10 described in the first embodiment. And, like the output wiring 15 of the one clamp source 11, they are wired in parallel to each other and through all the wiring layers (FIG. 3).

  The selector 21b outputs the output of the selector 21a when the select condition holding FF 12b is connected to the 0 clamp source 10b, and outputs the output of the adder 20b when the select condition holding FF 12b is connected to the 1 clamp source 11b. Output. When the version number is updated to “2” due to the function correction of the LSI, the connection destination of the select condition holding FF 12b is switched from the 0 clamp source 10b to the 1 clamp source 11b. This switching is performed in the same manner as when the version number is updated from “0” to “1”. In any one layer in the wiring layer, the wiring from the 0 clamp source 10b to the selection condition holding FF 12b and the 1 clamp source 11b This can be realized by switching the output wiring.

  When the version number is updated to a value obtained by adding 2 to the output value of the initial version number information 13, that is, the version number is updated to "2", the connection destination of the select condition holding FF 12a is 1 even if the connection destination is the 0 clamp source 10a. The clamp source 11a may be used. This is because when the select condition holding FF 12b outputs “1”, the selector 21b outputs either the output of the initial version number information 13 or the output of the adder 20a from the selector 21b. This is because the output of Accordingly, even when the connection destination of the selection condition holding FF 12a is switched to the 1 clamp source 11a in the previous version number update, the version number is changed without returning the connection destination of the selection condition holding FF 12a to the 0 clamp source 10a. Can be updated to “2”. Here, it is assumed that the version number is increased by two, but it is also possible to increase the version number by three or more by increasing the number of the adder 20, the selector 21, and the selection condition holding FF12.

  FIG. 9 shows a version number information holding circuit according to the third embodiment of the present invention. In the present embodiment, the version number is updated using an adder that can change the addition value. The adder 23 adds any one of 0 to 4 to the output of the initial version number information 13 according to the combination of the values of the select condition holding FFs 12a to 12d and outputs the result. The wirings 14a to 14d between the selection condition holding FFs 12a to 12d and the 0 clamp sources 10a to 10d and the output wirings 15a to 15d of the 1 clamp sources 11a to 11d are the same as the selection condition holding FF 12 described in the first embodiment. Similar to the wiring 14 between the 0 clamp source 10 and the output wiring 15 of the 1 clamp source 11, the wiring is parallel to each other and passes through all wiring layers (FIG. 3).

  FIG. 10 shows the relationship between the combination of values of each selection condition holding FF and the added value. “*” In the figure indicates that the value does not depend on 0 or 1. When the outputs of the selection condition holding FFs 12a to 12d are all “0”, the adder 23 sets the added value to “0”, and the initial version number output by the initial version number information 13 is directly used as the HW revision output control unit 22. Output to. When only the output of the select condition holding FF 12a is “1” and the outputs of the other select condition holding FFs 12b to 12d are all “0”, the adder 23 sets the added value to “1” and sets the initial version number to 1. Is added to the HW revision output control unit 22. When the output of the selection condition holding FF 12b is “1” and the outputs of the selection condition holding FFs 12c and 12d are “0”, the addition value is “2”, and the value obtained by adding 2 to the initial version number is output as the HW revision. Output to the control unit 22.

  In the combination of the value to be added by the adder 23 and the values of the select condition holding FFs 12a to 12d, the select condition holding FF corresponding to the larger added value is prioritized. For example, when the value of the selection condition holding FF 12d is set to “1” so that the addition value is “4”, the addition value is the same regardless of the values of the other selection condition holding FFs 12a to 12c. “4”. In this way, when the correction is performed to change the connection destination of the selection condition holding FF so that the addition value becomes large by giving priority to the selection condition holding FF corresponding to the side with the larger addition value, the wiring already performed is performed. There is no need to revert the fix.

  In the initial state, the select condition holding FFs 12a to 12d are connected to the 0 clamp sources 10a to 10d, respectively. In this state, the adder 23 outputs “0” obtained by adding the conversion value “0” to the initial version number “0” output by the initial version number information 13. When the version number is increased by 1 to “1”, the connection destination of the selection condition holding FF 12a is switched to the one clamp source 11a. The switching of the connection destination can be realized in any one layer in the wiring layer as described in the first embodiment. The adder 23 sets the addition value to “1” and sets the initial version number “0” to 1 when the output of the selection condition holding FF 12a is “1” and the outputs of the selection condition holding FFs 12b to 12d are “0”. The added “1” (0001 in binary notation) is output to the HW revision output control unit 22. As a result, the version number is updated to “1”.

  Although the present invention has been described based on the preferred embodiments, the version number information holding circuit and the semiconductor integrated circuit of the present invention are not limited to the above embodiments, and the configuration of the above embodiments. To which various modifications and changes are made within the scope of the present invention.

1 is a block diagram showing a version number information holding circuit according to a first embodiment of the present invention. The block diagram which shows the version number information holding circuit after updating the version number information of LSI. The figure which shows the output wiring of 0 clamp source before wiring correction, and the output wiring of 1 clamp source. The figure which shows the output wiring of 0 clamp source after wiring correction, and the output wiring of 1 clamp source. The figure which shows the output wiring of 0 clamp source after wiring correction, and the output wiring of 1 clamp source. The figure which shows the output wiring of 0 clamp source after wiring correction, and the output wiring of 1 clamp source. The figure which shows the output wiring of 0 clamp source after wiring correction, and the output wiring of 1 clamp source. The block diagram which shows the version number information holding circuit of 2nd Embodiment of this invention. The block diagram which shows the version number information holding circuit of 3rd Embodiment of this invention. The table | surface which shows the relationship between the combination of the value of each selection condition holding FF, and an addition value. The block diagram which shows the semiconductor integrated circuit before and behind correction. The figure which shows the example of the structure of ASIC LSI. The block diagram which shows a part of circuit structure of LSI before function correction. The block diagram which shows a part of circuit structure of LSI after function correction. The block diagram which shows the structure of the version number information holding circuit in related technology. The block diagram which shows the version number information holding circuit after version number update. 2 is a block diagram showing a version number information holding circuit described in Patent Document 1. FIG. The table | surface which shows the combination of the input data in a version number information encoding part, and output data.

Explanation of symbols

10, 17: 0 Clamp source 11: 1 Clamp source 12: Select condition holding FF
13: initial version number information 14, 15: output wiring 16: wiring 20, 23: adder 21: selector 22: HW revision output control unit

Claims (7)

A version number information holding circuit mounted on a semiconductor integrated circuit,
An initial version information section for outputting the initial version number;
An adder for outputting a version number obtained by adding a predetermined number to the initial version number;
Version number information, comprising: a version number output unit that outputs either the output of the initial version number information unit or the version number output by the adder according to the output of the condition setting unit that holds selection information Holding circuit. A version number information holding circuit mounted on a semiconductor integrated circuit,
An initial version information section for outputting the initial version number;
First to Nth adders for adding 1 to N to the initial version number, where N is a natural number of 2 or more,
According to the output of the first to Nth condition setting units each holding the first to Nth selection information, either the initial version number or the output of the first to Nth adders A version number information holding circuit comprising: a version number output unit for outputting. The version number output unit includes first to Nth selectors;
The first selector outputs the initial version number or the output of the first adder according to the output of the first condition setting unit, and the i-th (i is an integer from 2 to N) selector. The version number information holding circuit according to claim 2, which outputs the output of the i th adder or the output of the (i−1) th selector in accordance with the output of the i th condition setting unit. A version number information holding circuit mounted on a semiconductor integrated circuit,
An initial version information section for outputting the initial version number;
A version number obtained by adding 1 to N to the initial version number according to the output of the first to Nth condition setting units each holding the first to Nth selection information, where N is a natural number of 2 or more A version number information holding circuit comprising: an adder that outputs The condition setting unit
Each is composed of first and second wiring groups including wiring of a plurality of wiring layers, and in each wiring group, wirings of adjacent wiring layers are sequentially connected by via plugs,
The wirings in the first wiring group and the wirings in the second wiring group extend substantially parallel to each other in each wiring layer, and one end of the wiring in the first wiring group has a first potential. And the other end constitutes an output end, one end of the wiring in the second wiring group is fixed to the second potential, and the other end is open,
5. The version number information holding circuit according to claim 1, wherein the first potential is output from the output terminal. The condition setting unit
Each is composed of first and second wiring groups including wiring of a plurality of wiring layers, and in each wiring group, wirings of adjacent wiring layers are sequentially connected by via plugs,
The wirings in the first wiring group and the wirings in the second wiring group extend substantially parallel to each other in each wiring layer, and one end of the wiring in the first wiring group has a first potential. And the other end constitutes an output end, one end of the wiring in the second wiring group is fixed to the second potential, and the other end is open,
In one of the plurality of wiring layers, the wiring in each wiring group is divided into two, and each divided end of the divided wiring in the first wiring group and the second wiring group are divided. The corresponding divided ends of the connected wirings are connected to each other, and a folded portion that folds back from the first wiring group to the second wiring group, and a folded portion that folds back from the second wiring group to the first wiring group. Formed,
5. The version number information holding circuit according to claim 1, wherein the second potential is output from the output terminal.   A semiconductor integrated circuit comprising the version number information holding circuit according to claim 1.

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