JP2002134615A - System for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an effective correction only by the change of a wiring layer even if a circuit is to be changed after making a mask in a standard cell design method. SOLUTION: In a circuit change method determining means 102, on the basis of a logic correction indication 112 for indicating the logic to be corrected and a correcting cell library 113, the circuit change for the logic correction and a method for executing a connection change of terminals influenced by a delay characteristic due to the change is determined, and in a circuit connection changing means 103, circuit connection information, where the logic is corrected, is made. By making a pattern design using this configuration, without using spare cells, the logic correction after making the mask can be made only by the change of the wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design apparatus for designing and modifying a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art When designing a semiconductor integrated circuit, it is often the case that an already designed circuit is changed for a logical modification due to a change in system specifications or the like. Although a mask is created and used, when a circuit is changed after the mask is created, the cost and time required for the correction increase as the number of masks to be corrected increases.

As a method for easily or inexpensively changing the circuit after making such a mask, in a standard cell design method, a spare cell which is not used at the time of layout design is inserted in advance, and the spare cell is used. There is a method of making a circuit change using such a method. For example, Japanese Patent Application Laid-Open No. 2-191
361, JP-A-5-243378, JP-A-6-232260, and the like,
There is a method in which a spare cell to which a wiring is not connected is inserted into a vacant area to easily perform circuit correction by correcting a wiring layer mask.

As a method for facilitating the correction of a mask in a wiring layer or the correction of a wiring by a focused ion beam or the like, as disclosed in Japanese Patent Application Laid-Open No. 5-190816, Wiring is performed to the uppermost wiring layer with as little as possible to facilitate processing of wiring by a focused ion beam or the like.
By laying out spare cells at both ends of a cell row as disclosed in Japanese Patent No. 5955, wiring at the time of circuit correction can be facilitated, or wiring can be minimized as disclosed in Japanese Patent Application Laid-Open No. 11-274311. There is a method of easily performing wiring correction by passing through an upper wiring layer.

Further, in the standard cell design method,
A desired circuit is designed by a combination of function cells, and it is also possible to manually modify the pattern design using signals of internal nodes of the function cells that are not used in normal pattern design.

[0006]

However, in the standard cell design method, when wiring is performed on an internal node of a functional cell, there is a problem that the delay characteristic of the cell changes due to the load capacitance of the wiring. Further, there is a problem that the cell area increases if the buffer logic is formed so as not to affect the delay characteristics between other pins.

In addition, if wiring is pulled up to the uppermost wiring layer or spare cells at both ends of the cell column are wired to facilitate the mask correction in the wiring layer, extra wiring is generated, so that the wiring efficiency is reduced. There is a problem that it decreases. Conversely, if the spare cell is unwired or the terminals are not drawn out too short, it is difficult to connect the spare cells to the terminals due to the existing wiring, so that the number of wiring layers required for repair increases. There are issues.

According to the present invention, in order to solve the above-mentioned problems, it is possible to modify a circuit with a minimum necessary pattern change and modify a delay characteristic registered in a function cell library. It is an object of the present invention to provide a device for designing a semiconductor integrated circuit capable of changing a circuit without any change.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit designing apparatus according to a first aspect of the present invention, wherein a delay characteristic is changed by changing a circuit connection in accordance with a predetermined logical correction instruction for circuit connection information before correction. Circuit change determining means for determining a circuit change method so as not to affect circuit connection, and circuit connection change means for changing connections between element elements of circuit connection information according to the circuit change method and outputting corrected circuit connection information The configuration is provided with. According to this configuration, even if the logic is modified after the mask is created, it is possible to respond to the delay characteristics without affecting the delay characteristics and by using a relatively small wiring layer change without using many spare cells. Becomes

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit designing apparatus which, based on the cell arrangement information indicated in the circuit connection information before correction, determines whether a cell has sufficient free space on one or both sides of the cell. A replacement cell determining means for determining a circuit change method for replacing a cell including a logic correction element, and changing the connection between the element elements of the circuit connection information according to the circuit change method, and outputting the corrected circuit connection information. It is configured to include a circuit connection changing unit. With this configuration, if an appropriate cell is replaced with a cell including a logic correction element, logic correction after mask design can be relatively easily performed only on the wiring layer.

Further, in the semiconductor integrated circuit designing apparatus according to the present invention, an arrangement limiting means for setting an area near the power supply wiring in the wiring layer as high as possible as an arrangement area, and spare cells are arranged in the restricted area. Arrangement correcting means, wiring limiting means for connecting the input terminal of the spare cell to the power supply wiring, and outputting a wiring limit so as to have a predetermined wiring length in a predetermined wiring layer; A configuration is provided that includes wiring correction means for correcting wiring to be connected in accordance with wiring restrictions. With this configuration, when the logical correction after the mask is created is performed using spare cells, the correction can be performed using only the wiring layers, and the number of wiring layers to be changed can be suppressed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
This will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a circuit correction device according to a first embodiment of the present invention.

The circuit correction apparatus 101 receives circuit connection information 111 before correction, a logic correction instruction 112 and a cell library 113 for correction as inputs, and outputs a circuit change instruction 114. Connection information 1
11 and a circuit connection changing unit 103 that receives the circuit change instruction 114 as input and outputs the corrected circuit connection information 115 as output. As shown in FIG. 3, the correction cell library 113 describes a cell name 301, an internal node logic 302, and an output terminal 303 that affects delay characteristics.

Next, the process of circuit correction will be described with reference to FIG. FIG. 2A is a circuit diagram showing the circuit connection information 111 before correction, and FIG. 2B is a circuit diagram showing the circuit connection information 11 after correction.
FIG. The cell name of the cell 211 is NAND
2, the instance name is I1, and the cell name of cell 213 is AN
In D2, the instance name is I3. The terminal 221 is an output terminal of the cell 211, and the output terminal 222 is an output terminal of the cell 213. The output terminal 222 is connected to the wiring 241.

As shown in FIG. 4, a signal name 401 to be corrected and a correction logic 402 are described in the circuit correction instruction 112. As can be seen from FIG.
Since no NAND2 is registered in No. 3, the circuit change method determining means 102 changes the cell 211 to the spare cell 215 included in the circuit connection information 111 before correction.

Cell 21 having output terminal 222 corresponding to signal 413 to be modified described in circuit modification instruction 112
3 is the cell 311 registered in the correction cell library 113, the correction logic 414 is compared with the internal node logic 312, and the correction logic 414 is not affected by the internal node of the cell 311 without affecting the delay characteristic. Can be realized,
The wiring 241 connected to the output terminal 222 is connected to the internal node 231 so that the output terminal 222 that affects the delay characteristics is connected.
To release. In this example, the modification logic 414 can be realized by the internal node logic 312.
When the modification logic 402 cannot be realized by the internal node logic 302 even in the cell registered in the circuit 13, the cell 401 corresponds to the signal 401 to be modified described in the circuit modification instruction 112, as in the previous example. The correction is realized by replacing the cell with a spare cell included in the circuit connection information 111 before the correction.

The circuit change instruction 114 determined by the circuit change method determining means 102 describes a change from the cell 211 to the cell 215 and a change in the connection of the cell 213. The circuit connection changing means 103 changes the connection described in the circuit change instruction 114, and outputs the corrected circuit connection information 115.

As described above, according to the semiconductor integrated circuit design apparatus of the first embodiment, the number of spare cells used can be reduced as compared with the circuit modification in which all modifications are made using spare cells. In the cell in which is changed, only the connection change in the same cell is required, so that the change of the wiring layer can be reduced. Also, even when wiring is connected to internal nodes,
Since terminals that affect the delay characteristics are not used, it is possible to avoid changing the delay characteristics registered in the cell library. (Embodiment 2) FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to a second embodiment of the present invention.

The circuit correction device 501 receives circuit connection information 511 before correction, cell arrangement information 512, and a cell library for correction 513 as inputs, and outputs replacement cell instructions 514. The replacement cell instruction 514 is input, and the corrected circuit connection information 515 is input.
And a circuit connection changing means 503 for outputting the same.
In the correction cell library 513, a cell name 601 before replacement, a cell name 602 after replacement, and an increased area 603 are described as shown in FIG.

Next, the process of circuit correction will be described with reference to FIG. FIG. 7A is a circuit diagram showing the circuit connection information 511 before correction, and FIG. 7B is a circuit diagram showing the circuit connection information 51 after correction.
FIG. FIG. 8A shows the cell arrangement of the circuit before correction, and FIG. 8B shows the cell arrangement of the circuit after correction. Cells 711, 712, 713, 714, 716
Are 811, 812, 813, 814, and 816, respectively.
Corresponding to

The replacement cell determination means 502 checks the free area on one or both sides of the cell before correction from the cell arrangement information 512, and if the increased area of the cell described in the corrected cell library 513 is smaller than the free area, It outputs to the replacement cell instruction 514 as a replacement cell.

The cell 711 has a free area 821 having an area of 2. The cell 611 corresponding to the cell 711 has an increased area 613 of 1 when the cell 611 is replaced with the cell 612.
11 is replaced with a cell 716 which is a cell 612. Cell 7
12, 713 and 714 are not described because they are not described in the corrected cell library 513. Further, even if the cell is described in the corrected cell library 513, if there is no free area with the increased area 603 or more on one side or both sides of the cell, the cell is not replaced.

The circuit change determined by the replacement cell determination means 502 is described in a replacement cell instruction 514. The circuit connection changing unit 503 changes the connection described in the replacement cell instruction 514, and outputs the corrected circuit connection information 515.

At the time of layout design before mask creation, the semiconductor integrated circuit designing apparatus according to the second embodiment is used to replace the cells with cells containing logic correction elements. The circuit is changed using the semiconductor integrated circuit design device of the first embodiment.

A case where the semiconductor integrated circuit designing apparatus of the first embodiment is used will be described with reference to FIG. Embodiment 1
FIG. 7B shows a circuit before the circuit correction is performed.

As shown in FIG. 4, the circuit correction instruction 112 describes the signal name to be corrected and the logic to be corrected. Cell 7
Since both cells 16 and 713 are cells registered in the correction cell library 113, they connect internal nodes and open terminals that affect the delay characteristics. The circuit shown in FIG. 7C is output as the corrected circuit connection information 115.

As described above, if the circuit is changed using the semiconductor integrated circuit designing apparatus of the second embodiment in the design before the mask is formed, the number of spare cells used in the circuit change after the mask is formed can be reduced. The effect that it can be obtained is obtained. (Embodiment 3) FIG. 9 is a block diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to a third embodiment of the present invention.

The layout design apparatus 901 receives the power supply wiring information 911 as input, and outputs arrangement restriction information 912 for restricting the arrangement position of spare cells.
A placement correction unit 903 that receives the placement restriction information 912 and the placement information 913 to place a spare cell and outputs the spare cell placement information 914, a minimum wiring designation 915 and a wiring amount information 916, and inputs the spare cell. Wiring restriction means 9 for outputting wiring restriction information 917 for restricting the wiring of input terminals
And wiring correction means 905 for inputting the input terminal of the spare cell using the wiring restriction information 917 and the wiring information 918 as input and outputting the wiring information 919 after the spare cell wiring.

In the arrangement limiting means 902, the power supply wiring information 9
The placement restriction information 912 is created so that a spare cell is placed near the location 11. The wiring limiting unit 904 connects the wiring connected to the input terminal of the spare cell to the power supply wiring of the upper layer as much as possible, and selects the wiring layer having the smallest total wiring amount from the wiring amount information 916, Minimum wiring designation 915
The wiring restriction information 917 having a wiring length equal to or longer than the length specified in the above is created.

Next, with reference to FIG.
2. An implementation process of the arrangement correcting unit 903 will be described. FIG.
FIG. 1A is a layout diagram before a spare cell is arranged, and FIG.
0 (B) is a layout diagram after a spare cell is arranged. The power supply wiring information 911 describes the power supply wiring information obtained from FIG. The placement limiting unit 902 creates information of the area 1001 where a spare cell can be placed near the power supply wiring 1003 from the power supply wiring information 911. The arrangement correcting unit 903 arranges the spare cell 1002 in the area 1001 where the spare cell can be arranged. As a result, the layout is performed as shown in FIG.

Next, referring to FIG.
4. An implementation process of the wiring correction means 905 will be described. FIG.
FIG. 11A is a layout diagram of a spare cell before wiring, and FIG. 11B is a layout diagram of a spare cell after wiring. The wiring 1103 is a power supply wiring and is a wiring of a fourth wiring layer of the uppermost layer.

FIG. 12 shows the wiring amount information 916,
01 and the amount of wiring 1202 in each wiring layer is described, indicating that the third wiring layer has the least amount of wiring. The minimum wiring designation 915 describes the minimum required wiring length when changing the wiring. Wiring limiting means 904
Then, the input terminal 1102 of the spare cell 1101 and the power supply wiring 1103 wired in the fourth wiring layer, which is the nearest uppermost layer, are connected by the third wiring layer having the smallest wiring amount to the minimum necessary. The wiring restriction information 917 is created so as to perform wiring satisfying a proper wiring length. The wiring correction means 905 corrects the wiring so as to satisfy the restriction specified in the wiring restriction information 917.

The wiring method will be described with reference to FIG. The input terminal 1102 of the spare cell 1101 is assumed to be a first wiring layer. A second wiring layer at via 1104,
It is connected to the third wiring layer. Wiring 110 of third wiring layer
Reference numeral 5 satisfies the minimum required wiring length specified by the wiring restriction information 917, is connected to the fourth wiring layer by the via 1106, and is connected to the power supply wiring 1103 by the wiring 1107 of the fourth wiring layer.

When the circuit is modified after the mask is formed, the wiring 1105 in the third wiring layer is cut off to disconnect the connection to the power supply, and the terminal 110 of the spare cell 1101 is disconnected in the third wiring layer.
2. A predetermined connection change is performed.

As described above, according to the semiconductor integrated circuit designing apparatus of the third embodiment, in the circuit modification after the mask is created,
The change can be easily made only by the wiring layer. Moreover,
Since the terminals of the spare cells are connected to the power supply through a wiring layer having a sufficient length and a small amount of wiring, it is possible to perform correction by changing only a single wiring layer. In addition, since the spare cell is arranged near the power supply wiring, it is possible to shorten the wiring of the terminal of the spare cell to the power supply.

[0036]

As described above, the semiconductor integrated circuit designing apparatus of the present invention can be used to perform a logical correction after a mask is created.
By connecting wiring to the internal nodes of the cell and opening the terminals that affect the delay characteristics, the number of spare cells used can be reduced, and without changing the delay characteristics of the cell library, only changing the wiring layer There is an effect that the circuit can be changed.
Also, at the design stage before the mask design, by replacing cells having empty areas on one or both sides of the cells with cells added with elements that can be used for logic correction, when performing logic correction after mask creation, This has the effect of reducing the number of spare cells used. In addition, the spare cell can be placed as close as possible to the power supply wiring of the upper layer, and the wiring of the input terminal of the spare cell can be connected to the power supply wiring, and the wiring can be cut to a predetermined wiring layer at the time of the wiring By performing the shortest wiring, there is an effect that the correction can be performed only by changing a single wiring layer when performing the logical correction after the mask is created.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a circuit correction device in a semiconductor integrated circuit design device according to claim 1.

FIG. 2 is a circuit connection diagram before and after correction in the semiconductor integrated circuit design apparatus according to claim 1.

FIG. 3 is a diagram showing a correction cell library in the semiconductor integrated circuit design apparatus according to claim 1;

FIG. 4 is a diagram showing a logic correction instruction in the semiconductor integrated circuit designing apparatus according to claim 1;

FIG. 5 is a configuration diagram of a circuit correction device in the semiconductor integrated circuit design device according to claim 2.

FIG. 6 is a diagram showing a correction cell library in the semiconductor integrated circuit design apparatus according to claim 2;

FIG. 7 is a circuit connection diagram before and after correction in the semiconductor integrated circuit design apparatus according to claim 2.

FIG. 8 is a cell layout diagram in the semiconductor integrated circuit designing apparatus according to claim 2;

FIG. 9 is a configuration diagram of a circuit correction device in the semiconductor integrated circuit design device according to claim 3.

FIG. 10 is a cell layout diagram in the semiconductor integrated circuit designing apparatus according to claim 3.

FIG. 11 is a wiring diagram in the semiconductor integrated circuit designing apparatus according to claim 3.

FIG. 12 is a diagram showing wiring amount information in the semiconductor integrated circuit designing apparatus according to claim 3;

DESCRIPTION OF SYMBOLS 101 Circuit correction device 102 Circuit change method determination means 103 Circuit connection change means 111 Circuit connection information before correction 112 Logic correction instruction 113 Cell library for correction 114 Circuit change instruction 115 Circuit connection information after correction 211 Cell 212 Cell 213 cell 214 cell 215 cell 221 output terminal 222 output terminal 231 internal node 241 wiring 301 cell name 302 internal node logic 303 output terminal 311 cell 312 internal node logic 401 signal name 402 correction logic 413 signal 414 correction logic 501 circuit correction device 502 Replacement cell determination means 503 Circuit connection change means 511 Circuit connection information before correction 512 Cell arrangement information 513 Cell library for correction 514 Replacement cell instruction 515 Circuit connection information after correction 601 Cell name before replacement 02 Replaced cell name 603 Increased area 611 Cell 612 Cell 613 Increased area 711 Cell 712 Cell 713 Cell 714 Cell 716 Cell 811 Cell 812 Cell 813 Cell 814 Cell 816 Cell 821 Free area 901 Layout design unit 902 Restriction layout unit 902 904 wiring restriction means 905 wiring correction means 911 power supply wiring information 912 placement restriction information 913 placement information 914 spare cell placement information 915 minimum wiring designation 916 wiring amount information 917 wiring limit information 918 wiring information 919 preliminary cell wiring information 1001 Spare cell placement area 1002 Spare cell 1003 Power supply wiring 1101 Spare cell 1102 Input terminal 1103 Power supply wiring 1104 Via 1105 Wiring of third wiring layer 1106 1107 The fourth wiring 1201 wiring layer 1202 lines of wiring layers

Claims (3)

[Claims] 1. A circuit change determining means for determining a circuit change method in accordance with a predetermined logical correction instruction for circuit connection information before correction so that a change in circuit connection does not affect delay characteristics. A semiconductor integrated circuit designing apparatus comprising: a circuit connection changing unit configured to change a connection between element elements of the circuit connection information and output the corrected circuit connection information. 2. If there is a sufficient free area on one or both sides of the cell based on the cell arrangement information indicated in the circuit connection information before correction, the cell is replaced with a cell including a logic correction element. A semiconductor device, comprising: a replacement cell determining means for determining a circuit change method to be performed; and a circuit connection changing means for changing a connection between element elements of the circuit connection information according to the circuit change method and outputting corrected circuit connection information. Integrated circuit design equipment. 3. An arrangement limiting means for setting an area as close as possible to a power supply wiring in a wiring layer as high as possible, an arrangement correcting means for arranging a spare cell in the limited area, and an input of the spare cell. A wiring limiting means for connecting a terminal to the power supply wiring, and outputting a wiring limit so as to have a predetermined wiring length in a predetermined wiring layer; and a wiring connecting to an input terminal of the spare cell according to the wiring restriction. A semiconductor integrated circuit design device having a wiring correction means for correcting.