JP2005116902A - Method for mounting version-number information managing circuit to semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost associated with a method for mounting a version-number information managing circuit to a semiconductor integrated circuit. <P>SOLUTION: In the case of no correction, the connection of a version-number information setting register 2 with a low-voltage holding circuit 8 is completed and the connection of a high-voltage holding circuit 5 with an input circuit 12 is completed, for example, by forming a first layer wiring L<SB>1a</SB>, a first layer wiring L<SB>1c</SB>, a first layer wiring L<SB>1b</SB>, and a first layer wiring L<SB>1d</SB>; by forming in the upside layer of the first layer wiring a second layer wiring L<SB>2a</SB>, a second layer wiring L<SB>2c</SB>, a second layer wiring L<SB>2b</SB>, and a second layer wiring L<SB>2d</SB>; by forming in the upside layer of the second layer wiring a third layer wiring L<SB>3a</SB>, a third layer wiring L<SB>3c</SB>, a third layer wiring L<SB>3b</SB>, and a third layer wiring L<SB>3d</SB>; and by forming in the upside layer of the third layer wiring a fourth layer wiring L<SB>4e</SB>, and a fourth layer wiring L<SB>4f</SB>. Also, when there is a correction, and for example, when alteration is performed in the first wiring layers L<SB>1a</SB>, L<SB>1c</SB>, the information held by the version-number information setting register 2 is so altered from "0" into "1" as to increase the version number, by so deleting the intermediate portions of the first layer wiring L<SB>1a</SB>and the first layer wiring L<SB>1c</SB>, and so connecting with each other their portions which are present in the side of the version-number information setting register 2 as to connect with each other the register 2 and the high-voltage holding circuit 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of mounting a version number information management circuit on a semiconductor integrated circuit, for example, a version number for identifying a semiconductor integrated circuit that is mounted on a semiconductor integrated circuit such as an LSI and whose function has been changed for the same product type. The present invention relates to a method of mounting a version number information management circuit on a semiconductor integrated circuit that holds and manages information.

Semiconductor integrated circuits such as large-scale integrated circuits (LSIs), ultra-large scale integrated circuits (VLSI), or ultra-large scale integrated circuits (ULSI) have recently become more and more highly integrated and more dense. What consists of more than 10,000 transistors can be realized.
A system in which a central processing unit (CPU), a storage device (ROM, RAM), a buffer, and a plurality of peripheral devices that perform various signal processing are connected via a bus, signal line, etc. One example is a system LSI incorporated in a chip.

For example, when a logical error is detected in such a system LSI, it may be possible to correct the logical error by simply changing the wiring without re-creating the LSI.
For example, as shown in FIG. 10, registers 101, 102, 103 as an instance, an OR circuit 104, an AND circuit 105, and registers 106, 107 are formed in a predetermined area on the substrate, and the registers 101, 102 and the OR circuit are formed. 104, the registers 102 and 103 and the input side of the AND circuit 105 are connected, the output side of the OR circuit 104 and the register 106 are connected, and the output side of the AND circuit 105 and the register 107 are connected. It shall be connected.
The data stored in the register 106 is the result of ORing the outputs of the registers 101 and 102 by the OR circuit 104, and the data stored in the register 107 is the AND of the outputs of the registers 102 and 103 by the AND circuit 105. It is a result.

Here, it is assumed that there is a logical error. That is, the AND circuit 105 must be connected so that the operation result of the OR circuit 104 and the output of the register 103 are input as shown in FIG. 11 instead of the outputs of the registers 102 and 103. Shall be.
In this case, as shown in the figure, the connection between the register 102 and the input side of the AND circuit 105 is cut off, and the connection between the output side of the OR circuit 104 and the input side of the AND circuit 105 is added. Correct errors can be corrected.

By the way, the LSI has a multilayer wiring structure. For example, as shown in FIG. 12, a terminal forming layer M ₀ in which input / output terminals of functional blocks such as circuit elements and macro cells constituting the LSI are formed; A first wiring layer M ₁ , a second wiring layer M ₂ , a third wiring layer M ₃ , and a fourth wiring layer M ₄ are provided for wiring for connecting the input / output terminals.
For example, as shown in the figure, when arbitrary circuit elements 108 and 109 are connected to each other, the output terminal 108b of the circuit element 108 and the input terminal 108a of the circuit element 109 are connected to the first wiring layer M ₁ and the second wiring. Wiring is performed using the layer M ₂ , the third wiring layer M ₃ , and the fourth wiring layer M ₄ .
Here, for example, on the first wiring layer M ₁ , second wiring layer M ₂ , and third wiring layer M ₃ above the circuit elements 108 and 109, other wirings (indicated by thick broken lines in the figure), respectively. Is formed, the wiring is routed through the first wiring layer M ₁ , the second wiring layer M ₂ , the third wiring layer M ₃ , and the fourth wiring layer M ₄ in order to avoid these wirings. Do.

The circuit shown in the circuit diagram of FIG. 10 is actually provided with a register 102, an OR circuit 104, an AND circuit 105, a register 106, etc. as circuit elements on a substrate 111 as shown in FIG. In each wiring layer M ₁ (M ₂ , M ₃ , M ₄ ), a wiring is formed and connected to it.
The connection relationship between each circuit element before correction will be described. As shown in the figure, the register 102 and the OR circuit 104, the wiring _{N 1a} of the first on the wiring layer _{M 1,} wiring _{N 2a} on the second wiring layer _{M 2,} third on the wiring layer _{M 3} wiring N _3a , wiring N _4a on the fourth wiring layer M ₄ , wiring N _3b on the third wiring layer M ₃ , wiring N _2b on the second wiring layer M ₂ , wiring N _1b on the first wiring layer M ₁ Connected via.

The register 102 and the AND circuit 105, a first wiring _{N 1a} on the wiring layers _{M 1,} the second wiring layer _{M 2} on the wiring _{N 2a,} the third wiring layer _{M 3} on the wiring _{N 3a,} the fourth wiring The wiring N _4a on the layer M ₄ , the wiring N _3c on the third wiring layer M ₃ , the wiring N _2c on the second wiring layer M ₂ , and the wiring N _1c on the first wiring layer M ₁ are connected. ing.
The OR circuit 104 and the register 106 include a wiring N _1d on the first wiring layer M ₁ , a wiring N _2d on the second wiring layer M ₂ , a wiring N _3d on the third wiring layer M ₃ , and a fourth wiring. The wiring N _4b on the layer M ₄ , the wiring N _3e on the third wiring layer M ₃ , the wiring N _2e on the second wiring layer M ₂ , and the wiring N _1e on the first wiring layer M ₁ are connected. ing.

Connections between each circuit element after correction, as shown in FIG. 14, the fourth remove part of the wiring on the wiring layer M _4, in which part instead is added.
That is, as shown in the figure, the register 102 and the input side of the AND circuit 105 are configured such that the partial wiring N _4am (see FIG. 13) of the wiring N _4a on the fourth wiring layer M ₄ is deleted. The connection is broken.
Further, the input side of the output side and the AND circuit 105 of the OR circuit 104, by some lines _{N 4bm} wiring _{N 4b} on the fourth interconnection layer _{M 4} is added, which is newly connected.
Further, the connection relationship between the register 102 and the OR circuit 104 and the connection relationship between the OR circuit 104 and the register 106 are not changed.

Thus, by changing the fourth wiring layer M ₄ wiring of the uppermost layer, it is possible to correct the logical errors.
As described above, in order not only to avoid other wirings but also to facilitate correction, a technique has been proposed in which the arrangement positions of circuit elements and wirings are devised in advance.
For example, in a place (area) where it is predicted that correction or change is likely to occur, circuit elements to be connected are arranged adjacent to each other, wiring is routed through as many wiring layers as possible, and a predetermined distance from each other is provided. The maintained wiring pair is formed in each wiring layer.
As a result, it is possible to reduce the cost because, for example, the uppermost layer wiring is slightly changed without re-creating an LSI in which a logical error is detected, and the already formed portion is not wasted. Can do.

By the way, the above-mentioned LSI has version number information for identifying an LSI whose function has been changed for the same product type when, for example, correction of wiring errors between circuit elements or correction that slightly changes the function is performed. Is provided with a version number information management circuit (see, for example, Patent Document 1 and Patent Document 2).
As shown in FIGS. 15 and 16, the version number information management circuit 112 includes a high potential holding circuit 113, a low potential holding circuit 114, version number information storage registers 115 and 116, and a version number information output unit 117. Have.

The high potential holding circuit 113 is a circuit that is connected to a power source and applies a high potential to the version number information storage registers 115 and 116. For example, the high potential holding circuit 113 is connected to a predetermined circuit element 118 and, if necessary, a plate The number information storage registers 115 and 116 are connected.
The low potential holding circuit 114 is connected to the ground and applies a low potential to the version number information storage registers 115 and 116. In the initial state, the low potential holding circuit 114 is connected to the version number information storage registers 115 and 116.

The version number information storage registers 115 and 116 are connected to the high potential holding circuit 113 or the low potential holding circuit 114 and hold 1-bit data of “0” or “1”.
The version number information output unit 117 is a circuit that reads 1-bit data from the version number information storage registers 115 and 116 and outputs it as version number information.
The version number is expressed by a combination of the output values b ₀ and b ₁ of the version number information storage registers 115 and 116. For example, if the output values b ₀ and b ₁ are “0” and “0”, respectively, the version number is “0” (initial state), the version is revised, and the output values b ₀ and b ₁ are “0” and “0”, respectively. In the case of “1”, the version number is “1”, and the output values b ₀ and b ₁ are “1” and “0”, respectively, the version number is “2” and the output values b ₀ and b ₁ are respectively In the case of “1” and “1”, the version number is “3”.

The circuit as shown in the circuit diagram of FIG. 15 actually has a high potential holding circuit 113 as a circuit element, a low potential holding circuit 114, and a version number information storage register on a substrate 111 as shown in FIG. 115, 116, etc. are arranged, and for example, wirings are formed in the wiring layers M ₁ and M ₂ and connected to each other.
The connection relationship between each circuit element before correction will be described. As shown in the figure, the low potential holding circuit 114 and the version information storage register 115, the first wiring layer _{M 1} on the wiring _{P 1a,} the second wiring layer _{M 2} on the wiring _{P 2a,} the first wiring layer They are connected via a wiring P _1b on M ₁ .

Also, the low potential holding circuit 114 and the version information storage register 116, a first wiring _P 1a on the wiring layers _{M 1, P 1c,} the second wiring layer _{M 2} on the wiring _{P 2b,} the first wiring layer _{M 1} It is connected via the upper wiring _P1d .
Also, the high potential hold circuit 113 and the circuit element 118, first wiring layer _{M 1} on the wiring _{P 1e,} the second wiring layer _{M 2} on the wiring _{P 2c,} the first wiring _{P 1f} on the wiring layers _{M 1} Connected via.
As a result, the output values b ₀ and b ₁ of the version number information storage registers 115 and 116 become “0” and “0”, respectively, and the version number is “0”.

For example, when it is necessary to change the connection relationship between predetermined circuit elements constituting a macro cell, the version number is changed from “0” in the initial state to “1” after revision as shown in FIG. as such, a portion of the first wiring layer M ₁ on the wiring is removed, add part instead, it changes the connection relation between the circuit elements constituting the version information management circuit 112.
That is, as shown in the figure, the connection between the low potential holding circuit 114 and the version number information storage register 116 is cut off by deleting the wiring P _1c (see FIG. 17) on the first wiring layer M ₁ . I'm leaning.

Further, the high potential holding circuit 113 and the version number information storage register 116 are newly connected by the addition of the wiring P _1g on the first wiring layer M ₁ .
Further, the connection relationship between the low potential holding circuit 114 and the version number information storage register 115 and the connection relationship between the high potential holding circuit 113 and the circuit element 118 are not changed.
As a result, the output values b ₀ and b ₁ of the version number information storage registers 115 and 116 become “0” and “1”, respectively, and the version number is “1”.
Thus, by changing the first wiring layer M ₁ lines, changing the version information that indicates the revision is made.
JP-A-2-266430 Japanese Patent Laid-Open No. 3-88361

  The problem to be solved is that, in the above prior art, a part of the wiring layer of the version number information management circuit is changed as a part of a predetermined wiring layer of an LSI, for example, a macro cell is changed (added or deleted). When changing, both wiring layers are different, so it is necessary to create mask data for changing each wiring layer and to create a photomask, which increases costs It is.

  In order to solve the above problems, the invention described in claim 1 is a version number for managing version number information for identifying a semiconductor integrated circuit whose function has been changed in the same product type or a functional block constituting the semiconductor integrated circuit. According to a method for mounting an information management circuit, an input / output terminal of a circuit element or a functional block constituting a semiconductor integrated circuit body is formed on a semiconductor chip, and the version number information management circuit is configured to store the version number information. A plurality of registers, a first potential holding circuit for holding a predetermined register among the plurality of registers at a first potential, and the predetermined register lower than the first potential A first step of forming a second potential holding circuit for holding at a second potential; a wiring layer having a multilayer structure; and a connection between the input / output terminals; and That is, the predetermined register is connected to the first potential holding circuit or the second potential holding circuit so that a combination of information stored in each predetermined register represents the version number information. In the second step, among all the wiring layers of the multilayer structure, the predetermined wiring layer included in the wiring path for performing the connection between the input / output terminals, The register is connected to the first potential holding circuit or the second potential holding circuit.

  According to a second aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to the first aspect. In the second step, wiring for connecting the input / output terminals is performed. When changing the connection relation between the input / output terminals in the predetermined wiring layer included in the path, at the same time, in the predetermined wiring layer, the predetermined register and the first potential holding circuit or the The version number information is revised by changing the connection with the second potential holding circuit.

  According to a third aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to the first or second aspect. In the second step, the predetermined register and the first Connection between the potential holding circuit or the second potential holding circuit is performed through all wiring layers of the multilayer structure.

  According to a fourth aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to the first, second, or third aspect. In the second step, between the predetermined input / output terminals. The connection is performed through all the wiring layers of the multilayer structure.

  According to a fifth aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to any one of the first to fourth aspects, wherein the wiring for connecting the input / output terminals is provided. The predetermined wiring layer included in the route is set in advance as a wiring layer that may be a place where the connection relation between the input / output terminals is changed.

  According to a sixth aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to any one of the first to fifth aspects. The dedicated first potential holding circuit and the second potential holding circuit are arranged in association with each other.

  A seventh aspect of the invention relates to a method of mounting a version number information management circuit on a semiconductor integrated circuit according to the sixth aspect, wherein in the first step, the register and the first potential holding circuit or When the second potential holding circuit is arranged adjacent to each other and the connection relation between the input / output terminals is not changed in the second step, the register and the second potential holding circuit are provided. A circuit or the first potential holding circuit is connected by a first wiring along a first wiring path, and a second wiring is connected to the first potential holding circuit or the second potential holding circuit. Connecting the second wirings along the path, the first and second wirings are routed through all the wiring layers of the multilayer structure and arranged adjacent to each other while maintaining a predetermined separation; A change in the connection relationship between the input / output terminals is performed according to a predetermined wiring layer. When performing, the first wiring connected to the predetermined register and the corresponding second wiring are cut by the predetermined wiring layer, and then the first and second wirings are formed on the register side. The wiring is connected to the register and the first potential holding circuit or the second potential holding circuit.

  According to an eighth aspect of the present invention, there is provided a method for mounting a version number information management circuit on a semiconductor integrated circuit according to any one of the first to seventh aspects, wherein the plurality of registers have at least a preset maximum value. A number corresponding to the version number is provided, and when a predetermined register of the plurality of registers is connected to the first potential holding circuit, the corresponding version number information is represented.

  A ninth aspect of the invention relates to a method of mounting a version number information management circuit on a semiconductor integrated circuit according to any one of the first to eighth aspects, wherein each register stores 1-bit information. It is characterized by that.

  According to the configuration of the present invention, a part of the wiring of the version number information management circuit is changed when a part of the predetermined wiring of the semiconductor integrated circuit body is changed (added or deleted). Since the wiring layer of the place can be made the same layer, for example, it is not necessary to create mask data for change separately, and the same photomask can be used, so that the cost can be reduced. it can.

  The change of the semiconductor integrated circuit main body and the corresponding change of the version information management circuit can be executed in the same wiring layer, thereby realizing the purpose of reducing the cost.

  FIG. 1 is an explanatory diagram for explaining a method of forming a version number information management circuit in a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of the version number information management circuit. FIG. 3 is a diagram showing the relationship between the output of each version number information setting register constituting the version number information management circuit and the output of the version number information encoding unit, and FIG. 4 shows the configuration of the semiconductor integrated circuit. FIG. 5 is an explanatory diagram for explaining a method of forming a version number information management circuit in the semiconductor integrated circuit. FIG. 6 is a block diagram showing a configuration of the version number information management circuit. 7 to 9 are explanatory views for explaining a method of forming a version number information management circuit in the semiconductor integrated circuit.

First, a method for forming a version number information management circuit for managing version number information (HW Ware Revision information) when correction is not performed (that is, version number 0 (initial state)) is shown in FIG. This will be described with reference to FIG. 1 and FIG.
In this example, four wiring layers are formed, and verification is performed each time a wiring layer of each layer is formed. For example, when a logical error is detected, between circuit elements constituting a macro cell (functional block) or the like The connection relation is corrected by the wirings constituting the version information management circuit in the same layer.
In FIG. 1, the dotted line groups arranged in a lattice pattern are auxiliary lines for coordinate display drawn to show the positions of circuit elements and wirings on the substrate, and are not actually formed.

As shown in FIGS. 1 and 2, on the substrate 1, the version number information setting registers 2, 3, and 4 and the high potential holding circuit corresponding to each version number information setting register 2 (3, 4) (first (Potential holding circuit) 5 (6, 7), low potential holding circuit (second potential holding circuit) 8 (9, 11), input circuits 12, 13, 14, version number information encoding unit 15, version number The information storage registers 16 and 17 and the version number information output unit 18 are formed.
In this example, as shown in FIG. 1, the version number setting register 2 and the high potential holding circuit 5 are arranged on the substrate 1 so as to be adjacent to each other along the direction indicated by the arrow x. Further, the low potential holding circuit 8 and the input circuit 12 are arranged adjacent to each other along a direction indicated by an arrow x at a predetermined distance from the version number information setting register 2 and the high potential holding circuit 5. . The same applies to the version number information setting registers 3 and 4.

The version number information setting register 2 (3, 4) is connected to the high potential holding circuit 5 (6, 7) or the low potential holding circuit 8 (9, 11), and is 1-bit data “0” or “1”. Is a register that holds
The high potential holding circuit 5 (6, 7) is a circuit that is connected to a power source and applies a high potential to the version number information setting register 2 (3, 4). 11) is a circuit which is connected to the ground and applies a low potential to the version number setting register 2 (3, 4). The input circuit 12 (13, 14) is a circuit that receives an output from the high potential holding circuit 5 (6, 7) or the low potential holding circuit 8 (9, 11).

The version number information encoding unit 15 is a circuit that receives 1-bit data from each version number information setting register 2 (3, 4) and outputs corresponding 2-bit data indicating the version number.
The version number information recording registers 16 and 17 are registers that receive and hold 1-bit data of the output value b ₀ and the output value b ₁ , respectively, among the data output from the version number information encoding unit 15.
The version number information output unit 18 is a circuit that reads out 1-bit data from the version number information storage registers (registers) 16 and 17 and outputs it as version number information.
Note that the input / output terminals of the unit circuits such as the version number information setting registers 2, 3, 4, the high potential holding circuits 5, 6, 7 and the low potential holding circuits 8, 9, 11 are formed in the same layer. Shall.

Next, as shown in FIG. 1, first layer wirings L _1a and L _1b constituting a connection path between the version number information setting register 2 and the low potential holding circuit 8 are formed, and the high potential holding circuit 5 and the input are formed. First-layer wirings L _1c and L _1d for forming a connection path with the circuit 12 are formed.
That is, the first-layer wiring _L1a is connected to the input / output terminal of the version number information setting register 2 via a via contact (interlayer wiring) along the direction indicated by the arrow y in the figure. The version number information setting register is formed along the direction indicated by the arrow y so that the first-layer wiring _L1b is connected to the input / output terminal of the low potential holding circuit 8 via the via contact. Form towards 2.

Further, the first layer wiring _L1c is formed toward the input circuit 12 along the direction indicated by the arrow y so as to be connected to the input / output terminal of the high potential holding circuit 5 through the via contact, and the input First-layer wiring _L1d is formed toward high potential holding circuit 5 along the direction indicated by arrow y so as to be connected to the input / output terminal of circuit 12 via a via contact.
Here, the first layer wiring L _1a and the first layer wiring L _1c are arranged in parallel to each other while maintaining a predetermined separation. Similarly, the first layer wiring L _1b and the first layer wiring L _1d are arranged in parallel with each other while maintaining a predetermined separation.

Next, the second layer wiring constituting the connection path between the version number information setting register 2 and the low potential holding circuit 8 via the insulating layer on the first layer wirings L _1a , L _1b , L _1c , L _1d L _2a and L _2b are formed, and second layer wirings L _2c and L _2d that form a connection path between the high potential holding circuit 5 and the input circuit 12 are formed.
That is, the second layer wiring L _2a is formed toward the low potential holding circuit 8 along the direction indicated by the arrow x in the figure so as to be connected to the end portion of the first layer wiring L _1a through the via contact. In addition, the second layer wiring L _2b is formed toward the version number information setting register 2 along the direction indicated by the arrow x so as to be connected to the end portion of the first layer wiring L _1a through the via contact. To do.

Further, the second layer wiring L _2c is formed toward the input circuit 12 along the direction indicated by the arrow x so as to be connected to the end portion of the first layer wiring L _1c through the via contact. The second layer wiring L _2d is formed toward the high potential holding circuit 5 along the direction indicated by the arrow x so as to be connected to the end portion of the first layer wiring L _1d through a via contact.
Here, the second layer wiring L _2a and the second layer wiring L _2c are arranged in parallel with each other while maintaining a predetermined separation. Similarly, the second layer wiring L _2b and the second layer wiring L _2d are arranged in parallel with each other while maintaining a predetermined separation.

Next, the third layer wiring constituting the connection path between the version number information setting register 2 and the low potential holding circuit 8 via the insulating layer on the second layer wirings L _2a , L _2b , L _2c , L _2d L _3a and L _3b are formed, and third layer wirings L _3c and L _3d that form a connection path between the high potential holding circuit 5 and the input circuit 12 are formed.
That is, the third layer wiring L _3a is formed toward the low potential holding circuit 8 along the direction indicated by the arrow y in the figure so as to be connected to the end of the second layer wiring L _2a through the via contact. In addition, the third layer wiring L _3b is formed toward the version number information setting register 2 along the direction indicated by the arrow y so as to be connected to the end of the second layer wiring L _2a through the via contact. To do.

Further, the third layer wiring L _3c is formed toward the input circuit 12 along the direction indicated by the arrow y so as to be connected to the end portion of the second layer wiring L _2c through the via contact, The third layer wiring L _3d is formed toward the high potential holding circuit 5 along the direction indicated by the arrow y so as to be connected to the end of the second layer wiring L _3d through a via contact.
Here, the third layer wiring L _3a and the third layer wiring L _3c are arranged in parallel with each other while maintaining a predetermined separation. Similarly, the third layer wiring L _3b and the third layer wiring L _3d are also arranged in parallel with each other while maintaining a predetermined separation.

Next, the fourth layer wiring constituting the connection path between the version number information setting register 2 and the low potential holding circuit 8 via the insulating layer on the third layer wiring L _3a , L _3b , L _3c , L _3d L _4e is formed to complete the connection between the version number information setting register 2 and the low potential holding circuit 8, and the third layer wiring L _4f constituting the connection path between the high potential holding circuit 5 and the input circuit 12 is provided. Then, the connection between the high potential holding circuit 5 and the input circuit 12 is completed.
That is, the fourth layer wiring L _4e is formed along the direction indicated by the arrow x in the drawing so as to be connected to the end portions of the third layer wirings L _3a and L _3b via via contacts, The fourth layer wiring L _4f is formed along the direction indicated by the arrow x so as to be connected to the end portions of the layer wirings L _3c and L _3d via via contacts.
Here, the fourth layer wiring L _4e and the fourth layer wiring L _4f are arranged in parallel with each other while maintaining a predetermined separation.
In this way, the version number information setting register 2 and the low potential holding circuit 8, and the high potential holding circuit 5 and the input circuit 12 both pass through all the layer wirings and constitute their connection paths. The wirings are formed so as to be arranged in parallel adjacent to each other while maintaining a predetermined distance from each other.

Similarly, the version number information setting register 3 (4) and the low potential holding circuit 9 (11), and the high potential holding circuit 6 (7) and the input circuit 13 (14) are also connected using four layers of wiring. Is made.
Further, the version number information setting registers 2, 3, 4 and the version number information encoding unit 15, the version number information encoding unit 15 and the version number information storage registers 16 and 17, the version number information storage registers 16 and 17 and the version number information output unit 18 is also connected, and a version number information management circuit 19 is formed.
The version number information management circuit 19 formed in this way includes the version number information setting registers 2, 3, and 4 and the high potential holding circuit 5 (6, 6) corresponding to each version number information setting register 2 (3, 4). 7) and the low potential holding circuit 8 (9, 11), the input circuits 12, 13, and 14, the version number information encoding unit 15, the version number information storage registers 16 and 17, and the version number information output unit 18. Have.

In the version number information encoding unit 15, as shown in FIG. 3, the output values r ₁ , r ₂ , r ₃ of the version number information setting registers 2, 3, 4 are “0”, “0”, “0”, respectively. The version number information encoding unit 15 output values b ₀ and b ₁ are “0” and “0”, respectively, indicating the version number “0” (initial state).
When the output values r ₁ , r ₂ , r _{3 of} the version number information setting registers 2, 3, 4 are “1”, “0”, “0”, respectively, the output value of the version number information encoding unit 15 b ₀ and b ₁ are “0” and “1”, respectively, indicating the version number “1”.

When the output values r ₂ and r _{3 of} the version number information setting registers 3 and 4 are “1” and “0”, respectively, the output values b ₀ and b _{1 of} the version number information encoding unit 15 are “ “1” and “0” indicate the version number “2”.
Here, even if the output value r ₁ of the version number setting register 2 is “0” or “1”, the combination of the output values b ₀ and b ₁ does not change. In the figure, “DC (Don't Care)” indicates that the combination of the output values b ₀ and b ₁ of the version number information encoding unit 15 is the output value of the version number information setting register 2 (3, 4). This means that it is not related to r ₁ (r ₂ , r ₃ ).

When the output value r _{3 of} the version number information setting register 4 is “1”, the output values b ₀ and b _{1 of} the version number information encoding unit 15 are “1” and “1”, and the version number “ 3 ". Here, the output values r ₁ and r ₂ of the version number information setting registers 2 and 3 are “0” or “1”, and the combination of the output values b ₀ and b ₁ is It does not change.
Here, each version number information setting register 2 (3, 4) is connected to the low potential holding circuit 8 (9, 11), all data “0” is held, and the output value b of the version number information encoding unit 15 is stored. Both ₀ and b ₁ are “0”, and the version number information output unit 18 outputs the version number “0”.

At the same time as the version number information management circuit 19 is formed, a macro cell and the like are also formed, and the semiconductor integrated circuit 21 is manufactured.
As shown in FIG. 4, the semiconductor integrated circuit 21 of this example is a semiconductor chip such as a system LSI, for example, and is disposed in the core region 22 on the substrate 1 and has a plurality of macrocells having specific functions such as SRAM and DRAM. .., Interface circuits 25, 25,... Arranged in the peripheral region 24 on the substrate 1, and a version number information management circuit 19 that holds version number information of the semiconductor integrated circuit body. Yes.

A shield portion (not shown) is formed around each macro cell 23 so as to surround the macro cell 23.
In addition, this example semiconductor integrated circuit 21 has a multilayer wiring structure, and in the same manner as the technology described in the background section, among the circuit elements constituting the macro cell 23 and the interface circuit 25, the predetermined circuit elements are arranged. The connection path for connecting is formed so as to pass through all the layer wirings.
Correspondingly, the version number information setting register 2 (3, 4) constituting the version number information management circuit 19 and the high potential holding circuit 5 (6, 7) or the low potential holding circuit 8 (9, 11) As described above, the connection path for connecting the two is formed so as to pass through all the four layer wirings.

Next, for example, when the connection relationship between the circuit elements constituting the macro cell is corrected, the revision is performed by correcting the connection relationship in the layer wiring constituting the version information management circuit of the same layer (that is, A method of forming a version number information management circuit (in the case of version number 1 or later) will be described with reference to FIGS.
First, as in the case where correction is not performed, as shown in FIGS. 5 and 6, the version number information setting registers 2, 3, 4 and the version number information setting registers 2 (3, 4) are provided on the substrate 1. ) Corresponding to the high potential holding circuit 5 (6, 7) and the low potential holding circuit 8 (9, 11), the input circuits 12, 13, and 14, the version number information encoding unit 15, and the version number information storage register 16 , 17 and the version number information output unit 18.

Next, as shown in FIG. 5, first layer wirings L _1a and L _1b that form a connection path between the version number setting register 2 and the low potential holding circuit 8 are formed, and the high potential holding circuit 5 and the input are formed. First layer wirings L _1c and L _1d for forming a connection path with the circuit 12 are formed, and wiring for the second and subsequent layers is performed in the same manner. Here, simultaneously with the formation of the version number information management circuit 19, a macro cell and the like are formed.
As a result of the verification, for example, in a macro cell, a logical error was found at a location where a connection path for connecting circuit elements was formed so as to pass through all the layer wirings, and was described in the background section. As described above, when the connection relationship between circuit elements constituting the macro cell is corrected in the first layer, the connection relationship is corrected in the first layer wiring constituting the version information management circuit in the same layer. Go and do a revision.

For example, as shown in the figure, the intermediate portions of the first layer wirings L _1a and L _1b are respectively removed to leave the first layer wirings L _1e , L _1f , L _1g and L _1h , and the first layer wirings L _1e and the first layer wiring L _1f are connected by the first layer wiring L _1p , and the first layer wiring L _1e and the first layer wiring L _1h are connected by the first layer wiring L _1q .
As a result, the version number information setting register 2 is connected to the high potential holding circuit 5 as shown in FIG. 6, and the output values r ₁ , r ₂ , r ₃ of the version number information setting register 2.3.4 are “1”, “0”, and “0” are output, and the output values b ₀ and b ₁ are “0” and “1”, respectively, and the version number output unit 18 outputs the version number “1”. Will be.
As a result, the input circuit 12 and the low potential holding circuit 8 are connected. In this way, when the connection relationship is corrected only in the first layer wiring, the version number output unit 18 outputs the version number “1”.

In addition, for example, in a macro cell, when a connection path for connecting circuit elements is formed so as to pass through all layer wirings, a logical error is found, and connection between circuit elements constituting the macro cell is established. When the relationship is corrected in the second layer, the revision is performed by correcting the connection relationship in the second layer wiring constituting the version number information management circuit in the same layer.
That is, as shown in FIG. 7, the intermediate portions of the second layer wirings L _2a and L _2b are respectively removed to leave the second layer wirings L _2e , L _2f , L _2g and L _2h , and the second layer wirings L _2e and the second layer wiring L _2f are connected by the second layer wiring L _2p , and the second layer wiring L _2e and the second layer wiring L _2h are connected by the second layer wiring L _2q .
As a result, the version number information setting register 2 is connected to the high potential holding circuit 5 as shown in FIG. 6, and the output values r ₁ , r ₂ , r ₃ of the version number information setting register 2.3.4 are “1”, “0”, and “0” are output, and the output values b ₀ and b ₁ are “0” and “1”, respectively, and the version number output unit 18 outputs the version number “1”. Will be.

In addition, for example, in a macro cell, when a connection path for connecting circuit elements is formed so as to pass through all layer wirings, a logical error is found, and connection between circuit elements constituting the macro cell is established. When the relationship is corrected in the third layer, the revision is performed by correcting the connection relationship in the third layer wiring constituting the version number information management circuit in the same layer.
That is, as shown in FIG. 8, the middle portions of the third layer wirings L _3a and L _3b are respectively removed to leave the third layer wirings L _3e , L _3f , L _3h and L _2h , and the third layer wirings L _3e and the third layer wiring L _3f are connected by the third layer wiring L _3p , and the third layer wiring L _3e and the third layer wiring L _3h are connected by the third layer wiring L _3q .
As a result, the version number information setting register 2 is connected to the high potential holding circuit 5 as shown in FIG. 6, and the output values r ₁ , r ₂ , r ₃ of the version number information setting register 2.3.4 are “1”, “0”, and “0” are output, and the output values b ₀ and b ₁ are “0” and “1”, respectively, and the version number output unit 18 outputs the version number “1”. Will be.

In addition, for example, in a macro cell, when a connection path for connecting circuit elements is formed so as to pass through all layer wirings, a logical error is found, and connection between circuit elements constituting the macro cell is established. When the relationship is corrected in the fourth layer, the revision is performed by correcting the connection relationship in the fourth layer wiring constituting the version number information management circuit of the same layer.
That is, as shown in FIG. 9, the intermediate portions of the fourth layer wirings L _4e and L _4f are removed accordingly, leaving the fourth layer wirings L _4g , L _4h , L _4p and L _4q , and the fourth layer wirings. L _4g and the fourth layer wiring L _4h are connected by the fourth layer wiring L _4r , and the fourth layer wiring L _4p and the fourth layer wiring L _4q are connected by the fourth layer wiring L _4s .
As a result, the version number information setting register 2 is connected to the high potential holding circuit 5 as shown in FIG. 6, and the output values r ₁ , r ₂ , r ₃ of the version number information setting registers 2, 3, 4 are “1”, “0”, and “0” are output, and the output values b ₀ and b ₁ are “0” and “1”, respectively, and the version number output unit 18 outputs the version number “1”. Will be.

When the second correction is performed by correcting the layer wiring, the version number information setting register 3 is connected to the high potential holding circuit 6, and the output value r _{2 of the} version number information setting register 3 is “ 1 and the output values b ₀ and b ₁ are “1” and “0”, and the version number output unit 18 outputs the version number “2”.
Further, when the third correction is performed by correcting the layer wiring, the version number information setting register 4 is connected to the high potential holding circuit 7, and the output value r _{3 of the} version number information setting register 4 is “ 1 and the output values b ₀ and b ₁ are “1” and “1”, and the version number output unit 18 outputs the version number “3”.

Thus, according to the configuration of this example, when a part of the layer wiring of the version information management circuit is changed along with a part of the predetermined layer wiring of the semiconductor integrated circuit, Since the wiring layer on which the layer wiring is formed can be the same layer, it is not necessary to create mask data separately for each wiring layer, and the same photomask can be used, thereby reducing costs. be able to.
Further, when correction is made in a plurality of wiring layers, it is only necessary to change the connection for a single version number information setting register, so that the version number can be easily revised.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Are also included in the present invention.
For example, in the above-described embodiments, the case where the wiring of the version number information management circuit is routed through all wiring layers has been described. However, the wiring of the version number information management circuit does not necessarily have to be routed through all wiring layers. For example, the uppermost layer may always be routed, and the wiring between the terminals of the macro cell may be necessarily routed through the uppermost layer for a predetermined wire.
In addition, although the case where the dedicated high potential holding circuit and the low potential holding circuit are arranged in association with each register has been described, they may be shared.
Moreover, although the case where the wiring layer is four layers has been described, it may be five layers or more, or three layers or less.
Further, the case where the number of registers is three has been described, but four or more registers may be used.
Further, although a case has been described in which a part of the output value of the register is made irrelevant to the expression of the version number by a combination, it is possible to eliminate this and increase the expressible version number.
The input circuit may also be used as another circuit element.
The macro cells arranged in the core region may include, for example, a macro cell of a CPU and a macro cell of a graphic display controller in addition to a macro cell of a memory such as an SRAM.
Further, the present invention is not limited to the revision of the version information of the entire semiconductor integrated circuit, and the version number of, for example, a macro cell as a functional block constituting the semiconductor integrated circuit, even if the version information of the semiconductor integrated circuit is not changed. It can also be applied when information is revised. The version number information management circuit for this purpose may be formed in the macro cell, or may be formed in a peripheral region on the substrate, for example.

  The present invention can be applied to the case where verification is performed for each layer in addition to the case where verification is performed after the uppermost layer is formed.

It is explanatory drawing for demonstrating the formation method of the version number information management circuit to the semiconductor integrated circuit which is one Example of this invention. It is a block diagram which shows the structure of the same version number information management circuit. It is a figure which shows the relationship between the output of each version number information setting register which comprises the same version number information management circuit, and the output of a version number information encoding part. It is a block diagram which shows the structure of the same semiconductor integrated circuit. It is explanatory drawing for demonstrating the formation method of the version number information management circuit to the semiconductor integrated circuit. It is a block diagram which shows the structure of the same version number information management circuit. It is explanatory drawing for demonstrating the formation method of the version number information management circuit to the semiconductor integrated circuit. It is explanatory drawing for demonstrating the formation method of the version number information management circuit to the semiconductor integrated circuit. It is explanatory drawing for demonstrating the formation method of the version number information management circuit to the semiconductor integrated circuit. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art.

Explanation of symbols

1 Board 2, 3, 4 Version number setting register (register)
5, 6, 7 High potential holding circuit (first potential holding circuit)
8, 9, 11 Low potential holding circuit (second potential holding circuit)
15 Version Information Encoding Unit 16, 17 Version Information Storage Register 18 Version Information Output Unit 19 Version Information Management Circuit 21 Semiconductor Integrated Circuit 23 Macro Cell (Functional Block)
L _1a , L _1b , L _1c , L _1d first layer wiring L _2a , L _2b , L _2c , L _2d second layer wiring L _3a , L _3b , L _3c , L _3d third layer wiring L _4e , L _4f 4th layer wiring

Claims (9)

A method of mounting a version number information management circuit for managing version number information for identifying a semiconductor integrated circuit whose function has been changed in the same product or a functional block constituting the semiconductor integrated circuit,
A plurality of registers for forming the version number information management circuit and storing the version number information, and forming input / output terminals of circuit elements or functional blocks constituting the semiconductor integrated circuit main body on the semiconductor chip, Among the plurality of registers, a first potential holding circuit for holding the predetermined register at a first potential, and a second potential for holding the predetermined register at a second potential lower than the first potential A first step of forming a second potential holding circuit;
A wiring layer having a multilayer structure is formed to connect the input / output terminals, and among the plurality of registers, the predetermined register and the first potential holding circuit or the second potential holding circuit A second step of connecting such that a combination of information stored in each of the predetermined registers represents the version number information, and
In the second step, the register and the first potential are passed through a predetermined wiring layer included in a wiring path for connecting the input / output terminals among all the wiring layers of the multilayer structure. A method of mounting a version number information management circuit on a semiconductor integrated circuit, comprising: connecting a holding circuit or the second potential holding circuit.   In the second step, when the connection relationship between the input / output terminals is changed in the predetermined wiring layer included in the wiring path for performing the connection between the input / output terminals, In the wiring layer, the version number information is revised by changing connection between the predetermined register and the first potential holding circuit or the second potential holding circuit. A method for mounting a version number information management circuit on a semiconductor integrated circuit according to claim 1.   In the second step, the connection between the predetermined register and the first potential holding circuit or the second potential holding circuit is performed via all wiring layers of the multilayer structure. 3. A method for mounting a version number information management circuit on a semiconductor integrated circuit according to claim 1 or 2.   4. The semiconductor integrated circuit according to claim 1, wherein in the second step, the predetermined connection between the input and output terminals is performed through all wiring layers of the multilayer structure. How to implement version information management circuit.   The predetermined wiring layer included in the wiring path for performing the connection between the input / output terminals is set in advance as a wiring layer that may be used as a change location of the connection relation between the input / output terminals. 5. A method of mounting a version number information management circuit on a semiconductor integrated circuit according to claim 1, wherein the version number information management circuit is mounted on the semiconductor integrated circuit.   6. The first step according to claim 1, wherein the first potential holding circuit and the second potential holding circuit dedicated to each register are arranged in association with each other in the first step. A method of mounting a version number information management circuit on any one of the semiconductor integrated circuits. In the first step, the register and the first potential holding circuit or the second potential holding circuit are arranged adjacent to each other,
If the connection relationship between the input / output terminals is not changed in the second step, the register and the second potential holding circuit or the first potential holding circuit are connected to the first wiring. Connected by a first wiring along a path, and connected to the first potential holding circuit or the second potential holding circuit by a second wiring along a second wiring path;
The first and second wirings are arranged adjacent to each other while passing through all wiring layers of the multilayer structure and maintaining a predetermined separation,
When the connection relation between the input / output terminals is changed in the predetermined wiring layer, the first wiring connected to the predetermined register and the corresponding second wiring are connected to the predetermined wiring layer. After cutting at the wiring layer, the first and second wirings are connected on the register side, and the register is connected to the first potential holding circuit or the second potential holding circuit. A method for mounting a version number information management circuit on a semiconductor integrated circuit according to claim 6.   The plurality of registers are provided in a number corresponding to at least a preset maximum version number, and when a predetermined register of the plurality of registers is connected to the first potential holding circuit, it corresponds. 8. The method of mounting a version number information management circuit on a semiconductor integrated circuit according to claim 1, wherein the version number information is represented. 9. The method of mounting a version number information management circuit on a semiconductor integrated circuit according to claim 1, wherein each register stores 1-bit information.

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