JP2001284529A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To release restriction on the layout of memory macro in the phase region arrangement of a large scale memory macro hybrid semiconductor device provide with fuses. SOLUTION: A memory macro 100 is provided with a fuse circuit region 200 having a width 30 larger than the total value of the power supply wiring width, the power supply wiring interval and the fuse region width so that the fuse region can be provided between the power supply wirings thus releasing restriction on the layout of memory macro in the phase region arrangement. Since no power supply wiring is open circuited, power supply capacity for the memory macro can be sustained and a fuse wiring can be formed by connecting the fuse wiring terminals 10, 11 with 20, 21. Since the fuse wiring length is shortened and the additional capacity of the fuse wiring is reduced, erroneous function of a redundancy circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a memory macro structure of a memory macro hybrid type semiconductor integrated circuit device having a fuse in a redundancy circuit.

[0002]

2. Description of the Related Art In recent years, LSIs have become highly integrated, and large-scale logic circuits, arithmetic circuits, and even analog circuits composed of a megabit-class large-capacity memory and digital circuits have been integrated on a semiconductor chip. Is becoming possible.

On the other hand, since such a defect in a large-capacity memory macro leads to a defect in the entire chip, a spare memory cell is provided in advance in the memory cell in order to remedy the defect in the memory cell and to improve the yield of the chip. In addition, there is a redundancy circuit that switches to a spare memory cell when a memory cell is defective. For the redundancy circuit, a method of cutting a fuse formed of a polysilicon wiring or an aluminum wiring with a laser is widely adopted.

In a semiconductor integrated circuit device such as an embedded ASIC, a functional block is arranged in a predetermined layout area, and an automatic wiring device (C) is arranged based on connection information.
An AD device) is formed by connecting functional blocks.

The functional block is a NAND prepared in advance.
Primitive block such as / NOR, interface block such as input / output buffer, and DR
There is a memory macro such as AM / SRAM.

On the other hand, in recent years, the wiring layout has changed from the conventional wiring layout due to the realization of multilayer wiring due to the progress of the process. The top wiring layer is a wiring layer dedicated to power supply, and the wiring layout is being designed to cover the entire layout area with thick wiring. This power wiring is also wired in the internal area of the memory macro. It became so. By doing so, the resistance of the power supply wiring is reduced, and the electrical characteristics are improved.

Conventionally, when a memory macro having a fuse is mounted in such a wiring layout using the uppermost layer as a power supply wiring, a wiring prohibited area in which a fuse area in the memory macro cannot be wired in advance to prevent cutting other than the fuse wiring. It has been set as automatic wiring.

[0008]

In the above prior art,
When placing a memory macro after finishing the top power supply wiring, it must be placed so that there is no wiring other than the fuse wiring including the top power supply wiring in the fuse area in the memory macro. Was very large.

FIG. 8 is a diagram showing an example of a memory macro arrangement according to the above-mentioned prior art. The method of arranging the memory macros shown in FIG. 8 (referred to as a first prior art) has the following problems.

A first problem is that when a memory macro is arranged between power supply wirings in a layout area, the memory macro 100 having a built-in fuse area 250 must be
The fuses can be arranged only in the gaps between the power supply wirings 51, 52, 53, 54, 55, and 56. Note that reference numeral 200 in FIG. 8 indicates a fuse circuit area.

The memory macro 100 has a remarkably large size with respect to the primitive block and has a low degree of freedom in layout. Therefore, especially when a plurality of memory macros are mounted, the fuse region is arranged so that the entire fuse region is located in the gap between the power supply wirings. You will not be able to.

Since a large-scale memory macro usually has fuse circuits at a plurality of locations in the memory macro, as shown in FIG. 13, one of the fuse regions in the memory macro overlaps with the power supply wiring. There is a case where it cannot be avoided.

A second problem is to solve the above problem.
This is an increase in man-hours after memory macro arrangement, such as rearrangement of the memory macro or deletion of the uppermost power supply wiring overlapping with the fuse region.

FIG. 11 shows a layout and wiring flow of a conventional semiconductor integrated circuit equipped with a memory macro. First, after arranging a memory macro in a layout area (step S1) and performing internal power supply wiring (step S2), if the overlap between the power supply wiring and the fuse area in the memory macro can be eliminated by moving the memory macro, The macro is rearranged (step S3).

FIG. 14 is a layout diagram showing an example of memory macro rearrangement. As shown in FIG.
If the overlap between the power supply wiring 53 and the fuse regions 250 and 251 is not resolved only by performing the rearrangement of 00, the part of the power supply wiring 53 overlapping with the fuse regions 250 and 251 is peeled off in step S4. . Thereafter, the placement of primitive blocks (step S5), wiring (step S6), and verification of placement / wiring (step S5)
7) is performed to complete the process of arranging and wiring the semiconductor integrated circuit with the memory macro. In addition, in FIG.
9 is a power supply wiring, 200 to 203 are fuse circuit regions, 2
52 and 253 are fuse regions, and 270 is a power supply terminal.

A third problem of the first prior art is that part of the uppermost power supply line is deleted in order to eliminate the overlap between the fuse region in the memory macro and the uppermost power supply line. That is, there is no power supply to the memory macro. For example, as shown in FIG.
And power supply terminal 270 of the memory macro between 251
In some cases, the fuse regions 250 and 251 overlap the power supply wiring 53, and a part of the power supply wiring 53 is deleted, so that the power supply terminal 270 of the memory macro may not be connected to the power supply wiring.

A prior art for resolving the memory macro arrangement restriction is disclosed in Japanese Patent Application Laid-Open No. H11-134870 (hereinafter referred to as a second prior art).

In this technique, as shown in FIG. 10, the fuse circuit portion is a functional block (fuse block 300) different from the memory macro. By doing this,
As shown in FIG. 9, the fuse block 300 can be arranged independently of the memory macro 100, and the arrangement restriction of the memory macro can be eliminated. The fuse block 300 independent of the memory macro 100 is arranged after the power supply wiring of the uppermost layer is completed. Wiring between the fuse block 300 and the memory macro 100 is performed by an automatic wiring device based on the connection information. It should be noted that reference numerals 10, 11, 20, and 21 in FIG.
Denotes a fuse wiring terminal.

However, in the second prior art, as shown in FIG. 9, since the fuse wirings 40 and 41 are provided in an internal region outside the memory macro 100, the connection wiring between the primitive blocks is provided. However, there is a problem that the wiring property of the internal region is deteriorated.

Further, the second prior art has a problem that if the length of the fuse wiring is long, the redundancy circuit on which the fuse is mounted malfunctions. For example, in FIG. 9, the wiring length of the wirings 40 and 41 between the memory macro 100 and the fuse block 300 may be long, and there is a problem that the redundancy circuit malfunctions.

FIG. 16 shows an example of a redundancy circuit equipped with a fuse. Reference numeral 200 denotes a fuse circuit area, 30
0 and 301 are fuse blocks, 250 and 251 are fuse regions, and 281 to 288 are nodes. As for the fuse of the redundancy circuit, the fuse corresponding to the address of the defective memory cell is cut by a laser. In FIG. 16, when there is no defective address, all the fuses 230, 231,
232 and 233 are not disconnected, and the address signals 271 and
When 72, 273, and 274 are input, the nodes 281 and 282 become Low level, and the output signal 289 becomes Hi.
gh level is output.

When there is a defective memory cell, for example, if the address signal 273 is a defective address, the fuse 232 is cut. When the fuse 232 is cut, the node 28
Node 2 due to reduced ability to pull 2 to LOW level
82 is held at a high level, and the output signal 289 goes to a low level indicating that a spare memory cell is used.

In the example of the redundancy circuit shown in FIG.
The wirings corresponding to the fuse wirings 40 and 41 are the nodes 2
83 and 284. When the wiring length of nodes 283 and 284 is increased, even if fuses 230 and 231 are not cut, the ability to pull node 281 to a low level is reduced due to the additional capacitance of nodes 283 and 284, and node 281 is held at a high level. , Output signal 289
Becomes a low level, and it is determined that a spare memory cell is used even when there is no defective address.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a memory macro structure of a memory macro hybrid type semiconductor integrated circuit device having a fuse in a redundancy circuit and solving the above-mentioned problems of the prior art.

[0025]

SUMMARY OF THE INVENTION The present invention relates to a memory macro having a fuse and having a power supply terminal for receiving a power supply required for a circuit function, and a signal terminal for inputting and outputting a signal performing the circuit function. And at least one functional block having a different function are arranged in a predetermined layout area, and the power supply terminal and the signal terminal of the memory macro and the functional block are connected based on predetermined connection information. In the semiconductor integrated circuit device formed by the above, the memory macro has a fuse circuit area, and is orthogonal to a power supply wiring connecting between the power supply terminals arranged in parallel in the memory macro in the fuse circuit area. The width in the direction in which the fuse is formed is larger than the sum of the width and interval of the power supply wiring and the width of the fuse formation region. .

In the above structure, the fuse circuit area includes the power supply wiring, which is a gap area larger than the fuse formation area, and the fuse formation area is connected to the power supply wiring without cutting the power supply wiring in this area. It is provided between them.

The memory macro may be provided with at least one fuse wiring terminal adjacent to both ends of the fuse circuit area in a direction orthogonal to the power supply wiring.

Opposite fuse wiring terminals at both ends of the fuse circuit area can be connected by fuse wiring, and the fuse wiring terminals at both ends of the fuse circuit area share one of them. It can also be connected.

By providing a wiring prohibition region other than the fuse wiring in the memory macro so as to surround the formation region of the fuse, it is possible to prevent other wirings from entering the fuse formation region.

According to the present invention, the fuse wiring terminals in the memory macro are connected by the above-described configuration to generate a fuse region, whereby the fuse region is generated between the power supply lines according to the result of the highest power supply wiring. Can be.

[0031]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a memory macro having a fuse of the semiconductor integrated circuit device according to the first embodiment of the present invention. In the figure, reference numeral 100 denotes a memory macro, 200 denotes a fuse circuit area, 10, 11, 20, and 21 denote fuse wiring terminals, and 30 denotes a fuse circuit area width.

As shown in FIG. 1, a memory macro according to the present embodiment is a large-scale memory macro embedded AS having a fuse.
In a memory macro of a semiconductor integrated circuit device such as an IC,
The memory macro 100 has a fuse circuit region 200 having a width larger than the sum of the power supply line width, the power supply line interval, and the fuse region width so that a fuse region is generated in the gap between the uppermost power supply lines.

The width of the fuse circuit area 200 in the memory macro 100 (indicated by the fuse circuit area width 30) is the same as that of the fuse wiring terminal 10 provided in a direction orthogonal to the power supply wiring arranged in parallel. , 11 and the fuse wiring terminals 20, 21. That is, the fuse wiring terminals 10, 11 and 20, 21 are provided at both ends of the fuse circuit area in a direction orthogonal to the power supply wiring. In FIG. 1, two fuse wiring terminals are provided at both ends of the fuse circuit region so as to face each other.
The number of fuse wiring terminals provided at both ends of the fuse circuit region may be one or more.

FIG. 3 is a diagram in which the memory macro of FIG. 1 is arranged in a layout area and then subjected to fuse wiring. Reference numeral 50 in the figure
0 indicates a layout area, 51 to 56 indicate power supply lines, 61 indicates a power supply line width, and 62 indicates a power supply line interval. Reference numeral 60 denotes a fuse region width, and reference numeral 250 denotes a fuse region. As shown in FIG. 3, the fuse wirings 40,
41 is generated by arranging the memory macro 100 in the layout area 500 and then connecting the opposing fuse wiring terminals 10 and 20 and the fuse wiring terminals 11 and 21 respectively.

After the power supply wiring is performed in the fuse region 250, a fuse region is generated in accordance with the relationship between the fuse wiring terminals 10, 11, 20, and 21 and the power supply wiring.

FIG. 6 is a diagram showing an example of connection of fuse wiring terminals and generation of a fuse region. As shown in FIG. 6, the fuse wiring terminals 10 and 11 and the fuse wiring terminals 20 and 21 are connected by fuse wirings 40 and 41.
Aluminum wiring is used as the fuse wiring.
When the fuse wirings 40 and 41 are generated, the fuse wiring terminals 10, 11, 20, 21 and the power supply wirings 50, 51,
In accordance with the relationship 52, the fuse region 250 and the fuse region 25 are defined as regions where wiring other than the fuse wiring cannot be routed.
A wiring prohibited area 260 surrounding 0 is generated. The fuse circuit region width 30 of the fuse circuit region 200 is determined by the power supply line width 61, the power supply line interval 62, and the fuse region width 6.
The size is larger than the total value of 0. At this time, the power supply wiring interval 62 has a size that allows the fuse region 250 to be arranged.

Next, a flow of arrangement and wiring of the semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to FIG.

First, a memory macro is arranged in the layout area (step 81). Next, the uppermost power supply wiring is performed (step 82). Next, the size of the wiring layer and the fuse region used for the fuse wiring, the fuse wiring interval,
Fuse structure information such as a wiring prohibited area width generated around the fuse area is read (step 83). As the wiring layer of the fuse wiring, when the fuse wiring is formed of a single wiring layer, this wiring layer is specified, and in the case of a fuse wiring configuration in which a fuse cut portion is a through hole, a through hole is specified. The width of the fuse wiring is determined by the terminal size of the fuse wiring terminal.

Next, in steps 84 to 85, the coordinate relationship between the fuse wiring terminal and the power supply wiring is determined.

As shown in FIG. 6, the fuse circuit region 20
If the fuse circuit area width 30 of 0 is configured to have a size larger than the sum of the power supply wiring width 61, the power supply wiring interval 62, and the fuse area width 60, the coordinate relationship between the fuse wiring terminal and the power supply wiring is as shown in FIG. 86, 87, and 88 are three combinations. In step 84, the relation between the fuse wiring terminal and the power supply wiring is determined in the above states 86, 87, 88.
Judge which of the following is true.

In a state 86, both ends of the fuse wiring terminal do not overlap with the power supply wiring.
0 and 20 do not overlap with any of the power supply wirings 50, 51, 52, 53.

In a state 87, one of the fuse wiring terminals overlaps the power supply wiring and the other does not overlap the power supply wiring. The fuse wiring terminal 11 overlaps the power supply wiring 50.
The terminal for fuse wiring 21 is arranged in a gap between the power supply wirings 51 and 52.

The state 88 is a case where both ends of the fuse wiring terminal overlap the power supply wiring, and the fuse wiring terminal 12 overlaps the power supply wiring 50 and the fuse wiring terminal 22
Overlap with the power supply wiring 52.

In any state, a gap region of the power supply wiring is larger than the fuse region between the fuse wiring terminals, and the fuse region can be generated in this region without cutting the power supply wiring.

In steps 86, 87, and 88 in FIG. 4, the coordinates for arranging the fuse area and the generation of the fuse area for each of the states 86, 87, and 88 in FIG. 5 are performed. In step 86, since both ends of the fuse wiring terminal are in the gap of the power supply wiring, as shown in FIG. 5, the fuse region is formed in the gap area between the two power supply wirings 51 and 52 existing between the fuse wiring terminals. Can be generated. The center coordinates of the fuse area are the center coordinates of the gap area of the power wiring.

In step 87, since one of the fuse wiring terminals overlaps with the power supply wiring, as shown in FIG. 5, a fuse region is formed in a gap region between the two power supply wirings 50 and 51 existing between the fuse wiring terminals. Can be generated. The center coordinates of the fuse area are the center coordinates of the gap area of the power wiring.

In step 88, since both ends of the fuse wiring terminal overlap the power supply wiring, as shown in FIG. 5, three power supply wirings are sandwiched between the fuse wiring terminals, so that the gap region of the power supply wiring is two. The center coordinates of the gap region of the power supply wiring which is closer to the origin of the memory macro among them exists as the center coordinates of the fuse coordinates. Note that reference numerals 260 to 262 in FIG.

Next, in step 89 of FIG. 4, a fuse wiring is formed. As shown in FIG. 6, the fuse wiring connects the terminals for the fuse wiring with a straight line. Step 83
When a wiring layer is specified as the wiring layer used for the fuse wiring in the above, the connection is made with the specified wiring layer. If a through hole is specified in the wiring layer used for the fuse wiring in step 83, the through hole is arranged at the center coordinates of the fuse region calculated in steps 86, 87, and 88, and the fuse wiring terminal and the through hole are arranged. Is directly connected.

If the fuse wiring terminal and the wiring layer used for the fuse wiring specified in step 83 do not match, the fuse layer is switched to the wiring layer used for the fuse wiring on the fuse wiring terminal.

Next, in step 90, a wiring prohibited area is generated on the outer periphery of the fuse area. The placement prohibited area is generated by performing an OR process on the fuse areas generated in steps 86, 87, and 88, and generating a wiring prohibited area on the outer periphery of the figure with the wiring prohibited area width read in step 83. However, the definition of the wiring prohibition in the fuse wiring layer is not made at the intersection of the fuse wiring and the wiring prohibition region.

The wiring prohibited area can prevent intrusion of wiring other than the fuse into the fuse area.

Thereafter, similar to steps S5 to S7 in FIGS. 11 and 12, the arrangement of primitive blocks in the layout area other than the memory macros (step 91), between the primitive blocks and between the memory macros and the primitives are performed. Wiring between blocks is performed (step 92). Finally, connection and wiring connection verification is performed (step 93).

FIG. 15 is a diagram showing an example of a memory macro arrangement of the semiconductor integrated circuit device according to the first embodiment of the present invention. In the figure, reference numerals 40 to 47 indicate fuse wirings, 10 to 1
Reference numerals 7 and 20 to 27 denote fuse wiring terminals.

Next, the structure of a memory macro having a fuse in a semiconductor integrated circuit device according to a second embodiment of the present invention will be described. FIG. 2 is a configuration diagram of a memory macro having a fuse of the semiconductor integrated circuit device according to the second embodiment of the present invention.

The basic configuration of the memory macro of this embodiment is the same as that of the first embodiment. However, as shown in FIG. 2, one fuse wiring terminal is provided at one end of the fuse circuit area. In this case, two fuses (terminals 20 and 21 for fuse wiring) are formed at the other end (fuse wiring terminal 10) and a fuse circuit sharing one of the fuse wiring terminals 10 is formed. In this case, as shown in FIG. 7, the fuse wiring terminal 10 is connected to the fuse wiring terminals 20 and 21 by the fuse wirings 40 and 41. The placement and routing method using the memory macro of the present embodiment can be performed by the same operation as the placement and routing flow of FIG. 4 described in the first embodiment. In addition,
The fuse circuit (FIG. 7) in the present embodiment can also be obtained by connecting three of the fuse wiring terminals 10, 11 and 21 of the configuration of FIG. 1, and also by connecting the fuse wiring terminals 10 and 20. it can.

[0057]

As described above, the semiconductor integrated circuit device of the present invention has the following effects. (1) By providing a fuse circuit having a size larger than the sum of the power supply line width, the power supply line interval, and the fuse region width in the memory macro, all the fuse regions in the memory macro must be arranged in the gap between the uppermost power supply lines. That is, it is possible to eliminate the restriction on the layout arrangement of the memory macro, which is caused by the necessity. (2) Therefore, since the layout restriction of the memory macro described in (1) can be eliminated, the number of steps after the memory macro is disposed can be reduced. (3) The layout restrictions of the memory macro can be eliminated,
Since there is no power supply line to be disconnected, power supply capability to the memory macro can be maintained. (4) Since the fuse wiring is provided in the memory macro, the length of the fuse wiring can be reduced, and the additional capacitance of the fuse wiring can be reduced, so that malfunction of the redundancy circuit can be prevented. (5) Due to the fuse wiring in the memory macro, it is possible to prevent the layout area other than the memory macro from affecting the wiring properties.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory macro having a fuse in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory macro having a fuse in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing fuse wiring after arranging the memory macro of FIG. 1 in a layout area.

FIG. 4 is a layout wiring flow of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a coordinate relationship between a fuse wiring terminal and a power supply wiring of the semiconductor integrated circuit device of the present invention.

FIG. 6 is a diagram illustrating an example of connection of fuse wiring terminals and generation of a fuse region in the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a diagram illustrating an example of connection of fuse wiring terminals and generation of a fuse region in a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 8 is a diagram showing an example of a memory macro arrangement according to the first prior art;

FIG. 9 is a diagram showing an example of a memory macro arrangement according to a second prior art;

FIG. 10 is an enlarged view of the fuse block shown in FIG. 9;

FIG. 11 is an arrangement / wiring flow of the semiconductor integrated circuit device of the first related art.

FIG. 12 is a layout and wiring flow of a semiconductor integrated circuit device according to a second conventional technique.

FIG. 13 is a diagram showing an example of a conventional fuse region arrangement.

FIG. 14 is a diagram illustrating an example of rearrangement of a memory macro in the first related art.

FIG. 15 is a diagram showing an example of a memory macro arrangement of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 16 is a diagram illustrating an example of a redundancy circuit in which a fuse is mounted.

[Explanation of symbols]

 10 to 17, 20 to 27 Fuse wiring terminal 30 Fuse circuit area width 40 to 47 Fuse wiring 50 to 59 Power supply wiring 60 Fuse area width 61 Power supply wiring width 62 Power supply wiring interval 81 to 93 Step 100 Memory macro 200 to 203 Fuse circuit Area 230 to 233 Fuse 250 to 253 Fuse area 260 to 262 No wiring area 270 Power supply terminal 271 to 274 Address signal 281 to 288 Node 289 Output signal 300 Fuse block 500 Layout area

Claims (9)

[Claims] 1. A memory macro having a fuse, comprising: a power supply terminal for receiving a power supply required for a circuit function; and a signal terminal for inputting and outputting a signal performing the circuit function. And a semiconductor integrated circuit formed by arranging two functional blocks in a predetermined layout area and connecting the memory macro and the power terminals and the signal terminals of the functional blocks based on predetermined connection information. In the circuit device, the memory macro has a fuse circuit region, and a width of the fuse circuit region in a direction orthogonal to a power supply line connecting the power supply terminals arranged in parallel in the memory macro is equal to the power supply line. A semiconductor integrated circuit device, which is larger than the sum of the width and interval of the wiring and the width of the fuse forming region. 2. The semiconductor integrated circuit device according to claim 1, wherein said formation region of said fuse is provided between said power supply wirings. 3. A memory macro having at least one fuse wiring terminal adjacent to both ends of the fuse circuit area in a direction orthogonal to the power supply wiring. 3. The semiconductor integrated circuit device according to 1 or 2. 4. The semiconductor integrated circuit device according to claim 3, wherein opposite fuse wiring terminals at both ends of said fuse circuit region are connected by fuse wiring. 5. The semiconductor integrated circuit device according to claim 3, wherein opposite fuse wiring terminals at both ends of said fuse circuit region are connected by fuse wiring so as to share one terminal. 6. The semiconductor integrated circuit device according to claim 1, wherein said memory macro has a wiring prohibition region other than a fuse wiring so as to surround said formation region of said fuse. 7. The semiconductor device according to claim 3, wherein each of said fuse wiring terminals disposed adjacent to both ends of said fuse circuit region has a memory macro disposed so as to overlap said power supply wiring. 5. The semiconductor integrated circuit device according to claim 4, wherein 8. The memory macro according to claim 3, wherein said fuse wiring terminals arranged at both ends of said fuse circuit region have memory macros arranged so as not to overlap with any of said power supply wirings. Any one of the semiconductor integrated circuit devices. 9. A memory macro according to claim 3, wherein one of said fuse wiring terminals disposed at both ends of said fuse circuit region has a memory macro arranged so as to overlap said power supply wiring. Any one of the semiconductor integrated circuit devices.