JP2910734B2 - Layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit automatic layout system for automatically generating an automatic layout pattern of a semiconductor integrated circuit using a computer, and more particularly to an automatic wiring method having a hard macro.

[0002]

2. Description of the Related Art Conventionally, in an automatic layout system, an ASIC (Applicat
In an ion specific integrated circuit, layout is often performed without a hierarchy. In this case, if there is a portion where the wiring is locally congested, a portion that is not congested is affected in order to alleviate the congestion in the portion, and the degree of integration is reduced. For this reason, the degree of integration has been increased by using the part as a hard macro.

FIG. 4 is a flowchart showing a processing flow of a conventional automatic layout system. As shown in FIG. 4, the operator displays a hard macro by inputting circuit connection information 401, a cell library 402, a hard macro terminal, wiring prohibition, and a hard macro library 403 including an outline into the automatic layout system. It was arranged interactively via the terminal (step 404), and then another cell was automatically arranged. That is, after the placement of the hard macro, power supply wiring (step 405), automatic placement of cells according to the circuit connection information (step 406), schematic wiring (step 40)
7) The layout result 409 is output by the detailed wiring step (step 408).

FIG. 5 is a layout plan view of a conventional hard macro terminal portion. As shown in FIG.
The hard macro has a pad and is connected to the internal primitive cell 51 so that the hard macro terminal 53 can be easily connected to an external cell regardless of where it is placed on the chip. This connection is made by the wiring pattern 54 (that is, the hard macro has internal primitive cells, terminals, and wiring).

FIG. 6 is a layout plan view of another conventional hard macro terminal portion. As shown in FIG. 6, the wiring pattern 64 is also connected to the internal primitive cell 61 as the hard macro terminal 63. Usually, the wiring pattern 64 is wired with a minimum wiring width.

[0006]

However, when the above-mentioned hard macro is arranged on a chip and the chip power supply and the power supply wiring patterns 52 and 62 of the hard macro are connected,
There is a problem that the connection wiring becomes redundant or cannot be connected depending on the positions of the hard macro terminals 53 and 63 as the terminals of the external cells.

In the case where the hard macros are rotated, the hard macro terminals 53 and 63 are connected in any direction. For example, in the case of a two-layer layout, the first aluminum wiring layer is used. And the terminal of the second aluminum wiring layer must be provided.

However, since the connection to the hard macro terminals 53 and 63 is made on one layer (layer), a useless through-hole is provided on the layout, an extra wiring load capacitance is generated, and the speed is reduced. It also has the problem of being slow.

As described above, a conventional automatic layout system for a semiconductor integrated circuit using a hard macro has the following problems.

(1) The first problem is that the hard macro recognizes only the outer shape, the wiring prohibited area, and the terminal as a box, so that wiring is impossible and redundant wiring is generated due to the chip power supply wiring pattern. , May reduce the degree of integration,
That's what it means.

The reason is that the pads of the hard macro terminals are formed with a width of at least twice the minimum wiring width so that connection can be made in all directions. In addition, since a through hole is formed in the wiring pattern in the hard macro, the wiring in that portion cannot be changed.

(2) A second problem is that the load capacity of the terminal is increased, so that the speed is reduced.

The reason is that hard macro terminals that are not connected remain on the layout as they are.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a layout method which eliminates redundant wiring patterns, increases the degree of integration of an integrated circuit, and increases the speed. Is to do.

[0015]

In order to achieve the above object, the present invention relates to an automatic layout system for a semiconductor integrated circuit, comprising: a hard macro terminal; an internal primitive cell terminal connected to the hard macro terminal; and the hard macro terminal. In the hard macro library having at least the layout pattern information between the internal primitive cell terminals, the hard macro terminal and the layout pattern are deleted, and the internal primitive cell terminals are generated as the hard macro terminals, and the wiring layout is performed. It is characterized by.

SUMMARY OF THE INVENTION According to the present invention, in an automatic layout system for calculating a wiring pattern and automatically performing wiring, circuit connection information and its cell library and hard macro library are input to the automatic layout system.
Obtain or automatically arrange a hard macro or the like.

Next, the terminal of the internal primitive cell connected to the hard macro terminal is recognized from the hard macro library, and the hard macro terminal and the wiring layout pattern connected to the hard macro terminal are deleted.

Next, an internal primitive cell terminal is generated as a hard macro terminal, and a hard macro library is changed.

Next, all cells are automatically arranged based on the circuit connection information, schematic wiring and detailed wiring are performed, and a layout pattern having an actual wiring layer and wiring width is generated.

[0020]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart for explaining the processing flow of the embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention relates to a system for automatically arranging and wiring via a display terminal in an automatic layout system for semiconductor integrated circuits. A hard macro library 103 having at least a layout pattern information between a primitive cell terminal and a hard macro terminal and an internal primitive cell terminal, a circuit connection information 101, and a cell library 102 are provided, and these pieces of information are input. Then, the hard macro terminals and the wiring layout pattern are deleted, the internal primitive cell terminals are generated as the hard macro terminals, and the wiring layout is performed.

FIG. 1 shows the operation of the embodiment of the present invention.
This will be described in detail with reference to FIG.

Line connection information 101 and cell library 102 for determining a wiring route in the automatic layout system
And the hard macro library 103, and arranges a prebuffer, a hard macro, and a grouping area.

Next, the automatic layout system analyzes the terminal, wiring, and prohibition information of the hard macro library 103, and deletes the terminal and wiring information connected from the hard macro terminal to the hard macro internal primitive cell (step 105). ), A wiring region is created, and a terminal portion of the internal primitive cell is generated as a hard macro terminal (step 106).

Next, the chip power supply and the hard macro power supply are connected (step 107), and all cells are arranged according to the circuit connection information (step 108). Next, general wiring is performed (step 109), and a wiring pattern is created in the detailed wiring (step 110).

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; Referring to FIG. 1, an embodiment of the present invention relates to a system in which layout and wiring can be performed interactively in an automatic layout system for a semiconductor integrated circuit, wherein a hard macro terminal and an internal primitive cell terminal connected to the hard macro terminal, and A hard macro library 103 having at least layout pattern information between hard macro terminals and internal primitive cell terminals, circuit connection information 101 and a cell library 102 are input, the hard macro terminals and wiring layout patterns are deleted, and the internal primitive cell terminals are hardened. Generate as macro terminals and lay out wiring.

As shown in FIG. 1, circuit connection information 101, a cell library 102, and a hard macro library 103 for determining a wiring route are input to an automatic layout system.

ASI such as gate array and cell base
In the hard macro C, as shown in FIG. 2, the power supply wiring pattern 22 circulates around the hard macro for connection to the chip power supply, and the hard macro terminal 23 is arranged inside the power supply wiring pattern 22. .

The hard macro terminal 23 is connected to the terminal of the internal primitive cell 21, and the wiring pattern 2
4 is wired. This information is contained in the hard macro library.

Next, a hard macro is arranged (step 1).
04), by deleting the hard macro terminal 23 and the wiring pattern 24 from the information of the hard macro library 103 (step 105), the wiring area 35 can be created as shown in FIG.

Further, referring to FIG. 3, a hard macro terminal 33 is generated in the internal primitive cell 31 (step 106) and added to the hard macro prohibition information of the information source that cannot be wired from the hard macro terminal 33 to the external cell terminal. .

Next, the chip power supply and the hard macro power supply pattern 32 are connected (step 107).

Next, when performing general wiring and detailed wiring, the wiring area 35 is used for connection between external cell terminals and hard macro terminals and connection between external cell terminals according to the circuit connection information 101.

[0034]

As described above, according to the present invention,
Regardless of the position and direction of the hard macro, the hard macro terminal and its wiring pattern are deleted to create a new wiring area, so that redundant wiring can be removed and the degree of integration can be improved. effective.

Further, according to the present invention, terminals and the like are deleted,
Since a new hard macro terminal is newly generated and wired, only one layer of the hard macro terminal is connected, and the wiring load capacity of an unused layer can be reduced, thereby increasing the circuit speed. Can be.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow of a layout method according to an embodiment of the present invention.

FIG. 2 is a layout plan view of a hard macro terminal portion in one embodiment of the present invention.

FIG. 3 is a layout plan view after a hard macro terminal portion is generated in one embodiment of the present invention.

FIG. 4 is a flowchart showing a processing flow of a conventional layout method.

FIG. 5 is a layout plan view (part 1) of a conventional hard macro terminal portion.

FIG. 6 is a layout plan view (part 2) of a conventional hard macro terminal portion.

[Explanation of symbols]

 21, 31, 51, 61 Internal primitive cell 22, 32, 52, 62 Power supply wiring pattern 23, 33, 53, 63 Hard macro terminal 24, 54 Wiring pattern 35 Wiring area

Claims (2)

(57) [Claims] An automatic layout system for a semiconductor integrated circuit device, comprising: a hard macro terminal; an internal primitive cell terminal connected to the hard macro terminal; and wiring layout pattern information between the hard macro terminal and the internal primitive cell terminal. A hard macro library having at least the hard macro terminal, the hard macro terminal and the wiring layout pattern are deleted, the internal primitive cell terminal is generated as a hard macro terminal, and a wiring layout is performed. Layout method to do. 2. An automatic layout system for a semiconductor integrated circuit device, comprising: (a) a hard macro terminal, an internal primitive cell terminal connected to the hard macro terminal, and a wiring pattern between the hard macro terminal and the internal primitive cell terminal. (B) After arranging the hard macro, the terminal of the internal primitive cell connected to the hard macro terminal from the hard macro library is input. And (c) generating a hard macro terminal at a terminal portion of the internal primitive cell, and (d) a chip power supply and a hard disk. (E) connecting the macro power supply pattern; Performs placement of all cells, creating a wiring pattern by detailed wiring perform global routing, layout wherein the according information.