JPH03241762A - Designing method for wiring of integrated circuit - Google Patents
Designing method for wiring of integrated circuitInfo
- Publication number
- JPH03241762A JPH03241762A JP2038937A JP3893790A JPH03241762A JP H03241762 A JPH03241762 A JP H03241762A JP 2038937 A JP2038937 A JP 2038937A JP 3893790 A JP3893790 A JP 3893790A JP H03241762 A JPH03241762 A JP H03241762A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wide
- terminal
- automatic
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は複数種類の幅の配線を必要とする集積回路の配
線設計法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring design method for an integrated circuit that requires wiring of a plurality of widths.
集積回路の配線設計においては、配線の占有面積を最小
にするため配線の輻は設計規則で許される最小線幅に設
定することが通常である。ただし、特に配線遅延を小さ
くすることが要求される信号線や大電流が流れる電源配
線などには最小線幅よりも太い配線を用いる必要がある
。しかし、複数の線幅の配線を扱うことは配線処理を複
雑化するため、自動配線の実現はきわめて困難である。In the wiring design of integrated circuits, in order to minimize the area occupied by the wiring, the convergence of the wiring is usually set to the minimum line width allowed by design rules. However, it is necessary to use wiring thicker than the minimum line width especially for signal lines that are required to reduce wiring delay, power supply wiring through which a large current flows, and the like. However, handling wiring with multiple line widths complicates wiring processing, making it extremely difficult to realize automatic wiring.
そのため通常の自動配線手法では配線処理を高速に行う
ために配線の線幅は一種類のみしか許しておらず、その
ため配線に複数の線幅を用いる必要がある場合には、太
い線幅を必要とする配線は先に人手で配線し、自動配線
ではその太幅配線を配線禁止領域として認識し残りの信
号線を最小線幅を用いて配線することが通常であった。For this reason, normal automatic wiring methods only allow one type of line width for wiring in order to speed up the wiring process, so if multiple line widths need to be used for wiring, thicker line widths are required. Conventionally, the wiring for this purpose is first manually routed, and then automatic wiring recognizes the thick wiring as a wiring prohibited area and routes the remaining signal lines using the minimum line width.
上述した従来の設計方法は、人手の介入により設計期間
が長くなると共に、配線誤りか混入しやすいという欠点
を有する。特に、太幅配線を用いた信号線は端子位置か
ら端子位置まで完全に人手で配線しなければならない上
、その配線経路は各回路ごとに決定しなければならない
ためこの欠点が顕著に表れる。The above-described conventional design method has the drawbacks that the design period becomes longer due to manual intervention, and wiring errors are more likely to occur. In particular, signal lines using thick wiring must be wired completely manually from terminal position to terminal position, and the wiring route must be determined for each circuit, so this drawback is noticeable.
本発明の目的は、このような欠点を除き、太幅配線を含
んだブロックを配置することで即座に太幅の配線が実現
され、残りの回路固有の接続はすべて自動配線で行なわ
れるため、ブロック設計の段階で配線誤りがないことを
確認すればよく、また、自動配線はブロック内の太幅配
線全体を端子として認識し接続すべき素子から最短距離
で接続できる位置まで配線を行なうため、冗長な配線経
路を発生しないようにした集積回路を配線設計法を提供
することにある。The purpose of the present invention is to eliminate such drawbacks, to immediately realize thick wiring by arranging blocks containing wide wiring, and to perform all remaining circuit-specific connections by automatic wiring. You only need to confirm that there are no wiring errors at the block design stage, and automatic wiring recognizes all wide wiring within a block as terminals and routes the wiring from the element to be connected to the position where it can be connected at the shortest distance. An object of the present invention is to provide a wiring design method for an integrated circuit in which redundant wiring paths are not generated.
本発明の構成は、複数種類の幅の配線を必要とする半導
体集積回路の配線設計法において、太幅の配線で接続す
る必要がある能動素子と、この機能素子に接続する太幅
の配線とを一緒に機能ブロック内に配置し、その機能ブ
ロック内の前記太幅の配線全体を端子として認識する配
線幅一種の自3
動配線手法により太幅の配線を実現することを特徴とす
る。In a wiring design method for a semiconductor integrated circuit that requires wiring of multiple widths, the configuration of the present invention is to connect an active element that needs to be connected with a wide wiring and a wide wiring that connects to this functional element. The present invention is characterized in that the wide wiring is realized by a type of automatic wiring method in which the wide wiring is placed together in a functional block and the entire wide wiring in the functional block is recognized as a terminal.
次に本発明について図面により詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第1図は本発明の一実施例を説明するレイアウト図であ
る。予め機能ブロック2内に太幅の配線8を機能素子3
に接続するように配置した形でブロックを設計し、この
太幅配線8そのものをブロック2の端子として定義する
。個々の回路の配線設計においては、機能素子3と接続
すべき他の機能素子4.5からは最小幅の配線6.7を
用いてこの端子8と接続する。配線6.7は配線幅一種
の自動配線手法によって配線可能である。これにより素
子4.5から素子3まで一部太幅の配線8が実現される
。素子4から配線8までの配線において、自動配線は太
幅配線全体を端子として扱い配線8上で素子4から最短
距離にある点まで配線を行なう。FIG. 1 is a layout diagram illustrating an embodiment of the present invention. In advance, thick wiring 8 is connected to the functional element 3 in the functional block 2.
The block is designed in such a way that it is connected to the block 2, and the wide wiring 8 itself is defined as the terminal of the block 2. In the wiring design of each circuit, the other functional element 4.5 to be connected to the functional element 3 is connected to this terminal 8 using a wiring 6.7 having the minimum width. The wiring 6.7 can be wired by an automatic wiring method with a type of wiring width. As a result, a partially wide wiring 8 from the element 4.5 to the element 3 is realized. In the wiring from the element 4 to the wiring 8, automatic wiring treats the entire wide wiring as a terminal and performs wiring to the point on the wiring 8 that is the shortest distance from the element 4.
この配線法は、素子4と素子3の間の信号伝ばん遅延と
素子5と素子3の間の信号伝ばん遅延の4
差を小さくしたい場合に有効である。それは、配線8と
配線6の接続点から配線8と配線7の接続点までの配線
長が長い場合、素子4と素子3の間の信号伝ばん遅延と
素子5と素子3の間の信号伝ばん遅延の差は主にこの間
の配線遅延によって生じるが、この間は太幅の配線8で
実現されているため、抵抗が少なく配線による遅延が小
さくなる。This wiring method is effective when it is desired to reduce the difference in signal propagation delay between elements 4 and 3 and between elements 5 and 3. When the wiring length from the connection point of wiring 8 and wiring 6 to the connection point of wiring 8 and wiring 7 is long, the delay in signal transmission between elements 4 and 3 and the signal transmission delay between elements 5 and 3 are The difference in delay is mainly caused by the wiring delay during this period, but since this period is realized by the wide wiring 8, the resistance is low and the delay due to the wiring is small.
第2図は本発明の第2の実施例を説明するレイアウト図
である。この配線手法における自動配線手法は、太幅配
線を端子として定義する別の方法を説明する図であり、
端子として最小線幅の配線しか扱うことができないもの
でも可能である。このような自動配線手法に対しては、
実際にはブロック内に2本の配線格子を占有する配線が
配置されているのに対し、端子定義では配線9、lOの
ように最小線幅の配線2本が端子であるかのように定義
する。これによって自動配線は端子としても最小線幅の
配線のみを扱えばよいにも関わらず、第1図の場合と同
じ効果が得られる。FIG. 2 is a layout diagram illustrating a second embodiment of the present invention. The automatic wiring method in this wiring method is a diagram illustrating another method of defining thick wires as terminals.
It is also possible to use terminals that can only handle wiring with a minimum line width. For such automatic wiring methods,
In reality, wires that occupy two wire grids are placed in a block, but in the terminal definition, the two wires with the minimum line width are defined as if they were terminals, such as wires 9 and 10. do. As a result, the same effect as in the case of FIG. 1 can be obtained even though automatic wiring only needs to handle wiring with the minimum line width as a terminal.
以上説明したように本発明は、太幅配線を含んだブロッ
クを配置することで即座に太幅の配線を実現し、残りの
回路固有の接続はすべて自動配線で行うことにより、ブ
ロック設計の段階で配線誤りがないことを確認しておけ
ば個々の回路の配線設計においては誤りなく太幅配線を
実現できるという効果を有する。さらに、ブロック内の
太幅配線全体を端子として扱うことにより、端子位置を
一点に設定する方法と比べて冗長な配線経路は発生され
ないという効果を有する。As explained above, the present invention instantly realizes thick wiring by arranging blocks containing thick wiring, and performs all remaining circuit-specific connections through automatic wiring. If it is confirmed that there are no wiring errors, it is possible to realize thick wiring without errors in the wiring design of each circuit. Furthermore, by treating the entire wide wiring within a block as a terminal, there is an effect that redundant wiring paths are not generated compared to a method in which the terminal position is set at one point.
第1図は本発明の一実施例を説明するレイアウト図、第
2図は本発明の第2の実施例を説明するレイアウト図で
ある。
1・・・・・・チップ、2・・・・・・機能ブロック、
3.4゜5・・・・・・機能素子、6. 7. 9.1
0・・・・・・配線(最小線幅)、8・・・・・・太幅
配線。FIG. 1 is a layout diagram for explaining one embodiment of the present invention, and FIG. 2 is a layout diagram for explaining a second embodiment of the present invention. 1... Chip, 2... Functional block,
3.4゜5...Functional element, 6. 7. 9.1
0... Wiring (minimum line width), 8... Thick wiring.
Claims (1)
線設計法において、太幅の配線で接続する必要がある能
動素子と、この機能素子に接続する太幅の配線とを一緒
に機能ブロック内に配置し、その機能ブロック内の前記
太幅の配線全体を端子として認識する配線幅一種の自動
配線手法により太幅の配線を実現することを特徴とする
集積回路の配線設計法。In a wiring design method for semiconductor integrated circuits that requires wiring of multiple widths, active elements that need to be connected with wide wiring and wide wiring that connects to this functional element are placed together in a functional block. A wiring design method for an integrated circuit, characterized in that the wide wiring is realized by a type of automatic wiring method in which the entire wide wiring in the functional block is recognized as a terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2038937A JPH03241762A (en) | 1990-02-19 | 1990-02-19 | Designing method for wiring of integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2038937A JPH03241762A (en) | 1990-02-19 | 1990-02-19 | Designing method for wiring of integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03241762A true JPH03241762A (en) | 1991-10-28 |
Family
ID=12539139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2038937A Pending JPH03241762A (en) | 1990-02-19 | 1990-02-19 | Designing method for wiring of integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03241762A (en) |
-
1990
- 1990-02-19 JP JP2038937A patent/JPH03241762A/en active Pending
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