JP2874254B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device whose wiring is designed by a building block method or a gate array method.

[Conventional technology]

A semiconductor integrated circuit designed by the building block method or the gate array method is composed of several functional blocks, and the arrangement of each block and the wiring between the blocks are all performed by an automatic placement and routing program using CAD. Will be The functional block serving as the basic unit usually has an input terminal and an output terminal, and is defined on a program database. The wiring and layout of this integrated circuit are designed by connecting the terminals with automatic wiring in accordance with connection information between blocks, that is, circuit connection information. In such an automatic placement and routing system, the wiring between each functional block is performed faithfully according to the items described in the circuit connection information given in advance,
Wiring nets that are not in that information will never be generated, and the generated wiring artwork patterns are often redundant and irrational. This is very unfavorable for the layout of analog circuits that handle analog signals. FIG. 5 is a circuit diagram of a 3 × 3 (3-input, 3-output) cross-point switch omitting a decoder circuit, and FIG. 6 (a) is 6 × 6 (6-input, 6-output).
FIG. 3 is a layout diagram illustrating an example of a cross point switch circuit. In the circuit of the 3 × 3 (3 input 3 output) cross point, as shown in FIG. 3, the terminal definition is defined by a conventional method. That is, one signal line is defined as either the input terminal or the output terminal. That is, 1 to 3 are analog input terminals, 4 to 6 are analog output terminals, and 7 to 15 are control input terminals of switches 1601 to 1609. When this 3 × 3 cross point switch is defined as a block, and a 6 × 6 (6 input 6 output) cross point switch is laid out by automatic placement and routing, a layout as shown in FIG. 6A is obtained.

In FIG. 6 (a) of this 6 × 6 cross point switch, 7a, 7b, 7c, 7d are the blocks of the 3 × 3 cross point switch shown in FIG. 5, and are a building block type or gate array type semiconductor integrated circuit. The circuit layout in the block has already been completed as one functional block. 1a, 2a, 3a are analog input terminals, 1, 2, and
3, 4a, 5a, and 6a are analog output terminals.
Equivalent to 5,6. Also, 1b-6b, 1c-6c, 1d-6d,
This corresponds to 1 to 6 in FIG. Further, reference numerals 18 to 23 denote electrode pads and serve as analog input terminals of a 6 × 6 cross point switch. 24 to 29 are electrode pads, and 6
This is the anolog output terminal of the × 6 crosspoint switch. The problem with this layout is the redundant wiring net of the analog signal path. For example, in a wiring net connecting the terminals 1a and 1b and the electrode pad 18, the pad 18 and the terminal
The wiring pattern connecting 1b can be shortened by connecting the terminals 1a and 1b. However, many automatic wiring programs do not make such reasonable wiring. Occasionally, a short wiring pattern may be generated as seen in the net of the pad 20 and the terminals 3a and 3b. However, it is usually impossible to predict at all whether the wiring pattern will be shaped like an automatic wiring process. In the case of an analog signal circuit having such a redundant wiring pattern, not only the impedance is increased but also the crosstalk characteristic between signal paths is deteriorated, which is very undesirable for a block having an analog circuit function. . In order to improve the wiring property, there is a method of providing two or more equivalent terminals for one signal terminal.
If this is used, let's examine what will be the redundancy of the wiring net.

FIG. 6B is a layout diagram showing another example of the circuit of the 6 × 6 (6 inputs, 6 outputs) cross point switch.
For example, regarding the terminal 1a, as shown in FIG.
And providing the equivalent terminal 1a ₁ to the opposite side of FIG. 6 (a) to the position shown. Then, the newly provided terminals 1a and 1b come closer to each other, and if a wiring pattern is generated therebetween, the terminals 1a and 1b will be connected in a very rational pattern. However, since there is only one wiring net connecting the pad 18 with the terminal 1a and the terminal 1b in the wiring program, a wiring pattern connecting the pad 18 and the terminal 1a as shown in FIG. 6A is not generated. Eventually, it becomes a wiring net as shown in FIG. 6 (b). Therefore, pad 18 and terminal
The interval between 1a becomes long and does not reach the point where the above-mentioned problem is solved.

[Problems to be solved by the invention]

In a block of a semiconductor integrated circuit automatically designed by the conventional gate array method or the building block method described above, according to the conventional terminal definition, the wiring pattern between blocks and the wiring pattern between the block and the electrode pad are redundant as described above. Therefore, there is a disadvantage that the impedance of the signal path increases and the crosstalk characteristic between the signal paths deteriorates.

An object of the present invention is to provide a semiconductor device with an automatic wiring design that solves such a problem.

[Means for solving the problem]

In a semiconductor integrated circuit device according to the present invention, a plurality of functional blocks are arranged on a semiconductor substrate, and each of the functional blocks is wired between the functional blocks and between the functional blocks and the electrode pads. Is characterized in that two identical terminals are provided for one signal line, and these two identical terminals are wired as input terminals and output terminals, respectively.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a 3 × 3 crosspoint switch without a decoder circuit according to an embodiment of the present invention. Here, 1 to 3 are analog input terminals, 4 to 6 are analog output terminals, and 7 to 15 are control input terminals of the switches 1601 to 1609. Reference numerals 101 to 103 denote analog output terminals added according to the present invention, which are electrically equivalent to the analog input terminals 1 to 3, respectively. Similarly, 104-106
An analog input terminal added according to the present invention, which is electrically equivalent to 4 to 6 analog output terminals.

FIG. 2 is a layout diagram when the 3 × 3 cross point switch of FIG. 1 is changed to a 6 × 6 cross point switch. FIG. 2 shows an example in which a 3 × 3 cross point switch having this added terminal is laid out as a 6 × 6 cross point switch using an automatic placement and routing apparatus. In FIG. 2, 107a, 107b, 107c and 107d are the first
It is a 3 × 3 cross point switch block shown in the figure. 1a, 2a, and 3a are analog input terminals, as shown in FIG.
3, 4a, 5a, and 6a are analog output terminals.
Equivalent to 5,6. Reference numerals 101a, 102a, and 103a denote analog output terminals, which correspond to 101, 102, and 103 in FIG.
Is an analog input terminal and corresponds to 104, 105, and 106 in FIG. Reference numerals 18 to 29 denote electrode pads and serve as analog input / output terminals of the 6 × 6 cross point switch. Reference numeral 30 denotes a first wiring metal, and 31 denotes a second wiring metal, both of which are formed in different layers.

In the layout of FIG. 2, it can be seen that the wiring pattern is very short and reasonable. For example, terminal 1
2 which are symmetrical to each other in a block like a, 101a
This is because the definition of the two equivalent terminals as the input terminal and the output terminal, respectively, has enabled the distribution of wires conventionally connected by one wiring net to a plurality of nets. This is because they were arranged very close.

Here, in FIG. 2, if the wiring length from the pad 18 to the terminal 1a is, for example, 0.3 mm and the wiring length from the terminal 101a to the terminal 1b is 0.2 mm, the total length of the wiring net from the pad 18 to the terminal 1b is 0.5 mm. On the other hand, in FIG. 4 (a), which is a conventional layout, when the wiring length from the pad 18 to the terminal 1b is 2 mm, when the calculation is made assuming that the wiring length is proportional to the resistance value, the resistance value according to the present invention is 1/4. It has been reduced to. Although the wiring length in the block is not taken into consideration, the layout is designed so that the wiring resistance in the block is sufficiently reduced.

FIG. 3 is a circuit diagram of an analog switch showing another embodiment of the present invention. Here, in the figure, 201 is an NMOS transistor, 202 is a PMOS transistor, and 203 and 204 are inverters. 205 is an analog input terminal, 206 is a control input terminal of the switch, and 207 is an analog output terminal. Reference numeral 305 denotes an analog output terminal added according to the present invention, and the terminal 205 is an electrically equivalent terminal.

FIG. 4 is a layout diagram showing an analog multiplexer circuit. FIG. 4 shows an example in which a 4-channel analog demultiplexer is laid out by an automatic placement and routing device using this analog switch. In FIG. 4, 306a to 306d are blocks of the analog switch shown in FIG. 205a to 205d are analog input terminals, and correspond to the terminal 205 shown in FIG. Also 207a-207d
Is an analog output terminal, which corresponds to the terminal 207 in FIG.
a to 305d are analog output terminals corresponding to the terminal 305 shown in FIG. Reference numerals 209 to 213 denote input / output terminals of a 4-channel demultiplexer.

Here, a comparison with a conventional circuit will be made for reference. FIG. 7 is a circuit diagram of a conventional analog switch, and FIG.
FIG. 3 is a layout diagram illustrating a circuit of a four-channel demultiplexer using the analog switch of FIG. When the circuit of the channel demultiplexer shown in FIG. 8 utilizing the analog switch circuit shown in FIG. 7 is designed by an automatic placement and routing apparatus, the result shown in FIG. 8 is obtained. It can be seen that the wiring net connecting the pad 209 in FIG. 8 and the input terminals 205a to 205d of each switch is more redundant than that in FIG.

More specifically, in FIG. 4, the wiring length between the pad 209 and the terminal 205a is 0.5 mm, and the wiring length is 305a.
Wiring length between 205b, 305b and 205c, and 305c and 205d, respectively.
If it is 1 mm, the total length of the wiring from the pad 209 to the terminal 205d is 0.8 mm. On the other hand, in FIG.
Assuming that the wiring length between the pad 205 and the terminal 205d is 3 mm, the resistance between the pad 209 and the terminal 205d is reduced to about 1/3 by the present invention. Further, since the redundancy of the wiring pattern is reduced, there is an advantage that horizontal running and crossing with other signal lines are reduced, leading to improvement in noise resistance and crosstalk characteristics.

〔The invention's effect〕

As described above, according to the present invention, in a functional block in a semiconductor integrated circuit automatically designed by a gate array system or a building block system, one signal terminal is provided with two equivalent terminals, each of which has an input terminal and an output terminal. By defining, there is an effect that the redundancy of the wiring pattern between blocks or the wiring pattern between the block and the electrode pad is reduced, and a reasonable wiring pattern can be obtained. And it is very advantageous, especially for analog function blocks. That is, there is an effect that the impedance of the analog signal path is reduced by making the wiring short and rational, the crosstalk characteristic between the signal paths is improved, and noise from the digital block is hardly received.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a 3 × 3 cross-point switch without a decoder circuit according to an embodiment of the present invention, and FIG.
FIG. 3 is a layout diagram when a 3 × 3 cross point switch is changed to a 6 × 6 cross point switch, FIG. 3 is a circuit diagram of an analog switch according to another embodiment of the present invention, and FIG. 4 is an analog switch of FIG. FIG. 5 is a circuit diagram showing a 3 × 3 cross point switch without a conventional decoder circuit, and FIG. 6 (a) is a 3 × 3 cross circuit shown in FIG. FIG. 6B is a layout diagram showing another example of the circuit of the 6 × 6 cross point switch using a point switch to form a 6 × 6 cross point switch, and FIG. 7 is a conventional analog circuit. FIG. 8 is a circuit diagram of a switch, and FIG. 8 is a layout diagram showing a circuit of a four-channel demultiplexer using the analog switch of FIG.

Claims (1)

(57) [Claims] In a semiconductor integrated circuit device in which a plurality of functional blocks are arranged on a semiconductor substrate and wired between the functional blocks and between the functional blocks and the electrode pads, one signal is assigned to each of the functional blocks. A semiconductor integrated circuit device, wherein two identical terminals are provided for each line, and the two identical terminals are defined as an input terminal and an output terminal, respectively, and wired.