JPS62261146A - Wiring of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the area of a chip, by forming metallic interconnection layers, which cross a part on a logic function block so that the direction of the interconnection, whose product of the crossing length and the number of the interconnecting wirings is small, is used as the first layer, and the direction of the interconnection, whose product is large is used as the second layer. CONSTITUTION:With respect to a logic function block A, the product of the number of interconnecting wirings 3 and the lengths of sides (a) and (b) is larger than the product of the number of interconnecting wirings 1 and the lengths of sides (c) and (d). Therefore, the interconnecting wirings 3 are used as second metallic wire interconnecting layer 2, and the interconnecting wirings 1 are used as a first metallic wiring interconnecting layer 1. With respect to a logic function block B, the product of the number of the interconnecting wirings 2 and the lengths of sides (g) and (h) is larger than the product of the number of the interconnecting wirings 3 and the lengths of sides (e) and (f). Therefore, the interconnecting wirings 2 are used as the second metallic wire interconnecting layer, and the interconnecting wirings 3 are used as the first metallic interconnection layer. Since the interconnecting wirings 3 are the different wire interconnecting wirings on the logic function blocks A and B, the interconnection layers are changed by way of through holes T between the logic function blocks A and B. The number of wires of each metallic interconnecting wirings can be any number. The point is the comparison of the products of the lengths of the sides of the logic function blocks and the number of the crossing interconnecting wires.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring system for semiconductor integrated circuits, and particularly to a two-layer metal wiring system. The present invention relates to a wiring method for a semiconductor integrated circuit having a structure.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional two-layer metal wiring system.

Conventionally, wiring between FI function blocks in a semiconductor integrated circuit with this kind of two-layer metal wiring structure is performed by setting up a horizontal wiring track and a vertical wiring rack. Two layers of metal wiring were used depending on the predetermined wiring direction, such as the second layer in the vertical direction.

[Problems to be Solved by the Invention] 1. In the wiring method of the semiconductor integrated circuit having the conventional two-layer metal wiring structure described above, it is difficult to determine which wiring is to be the 1Mth metal wiring and which wiring is to be the 2nd layer metal wiring. It has not been optimized. Since the elements in the logic function program are wired using the first layer metal wiring, the first layer metal wiring is connected to the logic function program.
- When inputting or passing through another area, a new wiring area must be created. However, as shown in Figure 2, the vertical wiring is the second layer metal wiring, and the horizontal wiring 4.
If metal wiring layers are determined and routed by direction, such as the first layer metal wiring 5 and 5, the increase in the wiring area due to the first layer metal wiring 4 that crosses the logic function block C is the number of wiring 4. and side 1 (and wire 6 compared to the product of the length of e)
Since the product of the number of wires and the lengths of sides i and j is large, wiring 4
Although it is smaller than when the wiring 6 is placed in the first layer and the wiring 6 is placed in the second layer metal wiring, the increase in the wiring area due to the first layer metal wiring 5 that crosses the logic function pro...ID becomes large. It has the disadvantage of being stored away.

[Means for solving problems]

The wiring method for a semiconductor integrated circuit of the present invention includes a plurality of logic function blocks formed on a semiconductor substrate each consisting of a plurality of transistors and two metal wiring layers, and input to or passing through the logic function blocks. A first wiring direction perpendicular to mutually parallel first and second sides of the logic function block and third and third perpendicular sides to the first and second sides of the logic function block are arranged so that the wiring area of the wiring is minimized. Compare the two metal wiring layers in the second wiring direction perpendicular to side 4, and calculate the product of the side lengths of the first and second sides and the number of wiring in the second wiring direction and the third and The larger wiring direction of the product of the length of the fourth side and the number of wires in the first wiring direction is used as the second layer metal wiring, and the smaller wiring direction is used as the first layer metal wiring. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment has logical function blocks A and B, a first layer metal wiring 1, a second layer metal wiring 2, a metal wiring 3 in a different wiring layer, and a through hole T.

Logic function block A has two sets of opposing sides a.

b, c, d, and the logical function block B has two sets of opposing sides e, f and g, f, respectively. The metal wiring 3 in different wiring layers is a logical function block A p %
Wiring is done in the second layer when cutting, and wiring is done in the first layer when crossing the logic function block B. The through hole T is for connecting the layers of the metal wiring 3 in different wiring layers.

In this embodiment configured as described above, regarding the logic function block A, the number of wires 1, sides C and d
Since the product of the number of wires 3 and the lengths of sides a and b is larger than the product of the lengths of Regarding logic function block B, the product of the number of wires 2 and the lengths of sides g and h is larger than the product of the number of wires 3 and the lengths of sides e and f, so wire 2 is Layer metal wiring, wiring 3 is the first
It is sufficient to use layered metal wiring. Since the wiring layer 3 is different between the logic function blocks A and B and h, the wiring layer is switched between the logic function blocks A and B using the through hole T.

In this embodiment, the number of first-layer metal wiring 1, second-layer metal wiring 2, and metal wiring 3 of different wiring layers is each four, but the number may be any number. The point is to compare the product of the length of the side of the logic function block and the number of wires crossing it.

〔Effect of the invention〕

As explained above, in the present invention, metal wiring layers that cross over a logic function block are arranged such that the wiring direction with the smaller product of the crossing length and the number of wires is placed in the first layer, and the wiring direction with the larger product is placed in the second layer. This allows you to maximize the second-layer metal wiring area that can pass over the element area and use it for inter-element wiring, and also minimize the first-layer metal wiring area that cannot pass over the element area. This can be minimized, which has the effect of reducing the chip area.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional two-layer metal wiring system. 1.4.5...First layer metal wiring, 2.6...Second layer
Layer metal wiring, 3...Metal wiring in different wiring layers, A. B, C, D...Logic function block, T...Through hole, knee 1. b, c, t: t, e, f, g, h, i
,j. k, e, rn, n, c, p・-side. Destruction 1 diagram

Claims (1)

[Claims] In a wiring system for a semiconductor integrated circuit that includes a plurality of logic function blocks each consisting of a plurality of transistors formed on a semiconductor substrate and two metal wiring layers, a wiring area of a wire that inputs or passes through the logic function block. in the first wiring direction perpendicular to the mutually parallel first and second sides of the logical function block and in the third and fourth sides perpendicular to the first and second sides so that Compare two metal wiring layers in orthogonal second wiring directions, and calculate the product of the side lengths of the first and second sides and the number of wirings in the second wiring direction and the third and fourth sides. The larger wiring direction of the product of the side length and the number of wires in the first wiring direction is used as the second layer metal wiring, and the smaller wiring direction is used as the first layer metal wiring. A wiring method for semiconductor integrated circuits.