JPS6034039A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to attain wiring of a semiconductor device having a little level difference by an automatic design system by a method wherein the multilayer wirings consisting of from the first layer up to the n-th layer are provided crossing at a right angle alternately, the interval between the n-th layer wirings is made to the integer times of the interval of the (n-2)-th layer wirings arranged in parallel with the former wirings, and moreover the n-th layer wirings are positioned between the (n-2)-th layer wirings. CONSTITUTION:When four layer wirings are to be formed on a semiconductor substrate 10, the first layer wirings 1 directly on the substrate 10 and the second layer wirings 2 of the plural number and arranged in parallel respectively are made to cross at a right angle. Moreover the second layer wirings 2 and the third layer wirings 3 are also made to cross at a right angle, and similarly the fourth layer wirings 4 are also made to cross at a right angle. Accordingly, the wirings 1, 3 and the wirings 2, 4 are arranged in parallel respectively, and moreover the interval between the wirings 1, 3 is made to two times of the interval of the wirings 1 of the plural number. When width of the wirings 1 is made to 4mum, the interval between the wirings 1 is to 7mum, width of the wirings 3 is to 6mum, and the interval between the wirings 3 is made to 14mum, for example, the level difference is reduced, and generation of disconnection is also reduced. Moreover, because the interval between the wiring layers is aligned with the integer times, wiring programing is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to semiconductor devices, and particularly to multilayer wiring structures.

伽）　Conventional technology and problems' Semiconductor devices rapidly progressed into ICs and LSIs.

VLSI has become extremely highly integrated. This is because the higher the degree of integration, the greater the advantage of improved characteristics such as faster circuit operation.

However, with such high integration, the number of built-in circuits increases and becomes complex, so automatic design systems (CAD systems) that utilize the power of electronic computers are used to manufacture and design ICs.
has begun to be adopted. Further, in order to produce highly integrated ICs in a wide variety of products and in small quantities, ICs are manufactured using a mask slicing method in which a versatile circuit is formed on a semiconductor substrate and only the wiring layer is changed.

On the other hand, as the integration becomes higher, the wiring layers become more congested and multiple wiring layers are provided on the semiconductor substrate, and the multilayer wiring has a structure with large step differences, increasing the risk of wire breakage.

(C1 Object of the Invention The present invention eliminates these problems and proposes a structure of a semiconductor device that allows wiring with fewer steps by an automatic design system.

(dl Structure of the Invention The purpose of the invention is to provide multilayer wiring layers from the first layer to the nth layer on a semiconductor substrate so as to be alternately orthogonal to each other, and to set the distance between the **th wiring layers to the This is achieved by a semiconductor device having a structure in which the spacing between the wiring layers of the (n-2) layer is an integral multiple and the **th wiring layer is located between the wiring layers of the (n-2) layer, and the semiconductor substrate Multilayer wiring layers from the first layer to the )
A connecting hole between the nth layer and the (n-1) layer and a connecting hole between the (n-1)th layer and the (n-2) layer are provided in different regions with a layer interposed therebetween. This is achieved by a semiconductor device having a structure.

(e) Embodiments of the invention Hereinafter, embodiments will be described in detail with reference to one drawing. FIG. 1 shows a semiconductor chip (semiconductor substrate>1) according to the present invention.
FIG.

The first N distribution 1 directly above the semiconductor chip 10 and the second layer wiring 2 are orthogonal to each other, and the second N arrangement 1i12 and the third layer wiring all! :
The third layer wiring 3 and the fourth layer wiring 4 are perpendicular to each other, so the first layer wiring 1 and the third layer wiring 3 are parallel to each other, and the second layer wiring 2 and the fourth layer wiring 4 are perpendicular to each other. The wiring structure is parallel to the layer wiring 4. In addition, the third layer wiring 3 is provided between the first layer wirings 1, and the spacing between the third layer wirings 3 is twice that of the first N cotton wiring 1. A third layer wiring 3 is provided at every other interval of the first layer wiring 1. Similarly, the relationship between the second layer wiring 2 and the fourth layer wiring 4, which are orthogonal to the 1N wiring and the third layer wiring, is also defined.

FIG. 2 shows a partial cross-sectional view of the structure in FIG. (up to the center line), the width of the first layer wiring 13 is 6 μm, and the interval of the third N wiring layer is 14 μm.
Set it to μm. With this kind of wiring structure, there are fewer steps (therefore, disconnections can be reduced), and the spacing between wiring layers is matched to an integral multiple (in the example above, twice), making it easy to program the wiring using an automatic design system. Created in

Note that in this example, the wiring layer width is 4 μm and 6 μm, which increases as the layer goes up, but this is also a measure to avoid disconnection and can be input into the automatic design system.

Next, FIG. 3 shows a plan view of a connection hole (through hole) between multilayer wiring layers in another embodiment of the present invention, and FIG. 4 is a partial sectional view thereof. 1) It is also possible to provide a connection hole by stacking the complex wiring 1 and the third layer wiring 3 at the same position via the second layer wiring 2, but this would result in a large step difference. The connecting hole 5 with the 2N and the connecting holes 6 with the second and third ends are provided in different areas, so that the upper surface is flattened.

In this way, the structure shown in Figures 3 and 4 is defined,
It is extremely easy to create a wiring program using an automatic design system by incorporating the structure regulations explained in FIG. 1 above.

Although the above embodiment has been explained using a multilayer interconnection made of 4N, the present invention applies similar regulations to all multilayer interconnections from the first layer to the nth layer.

(f) Effects of the Invention As can be seen from the above explanation, the present invention and the automatic design system can improve IC wiring block structure (which can be easily created and have a wiring structure with few disconnections).
is effective in improving reliability.

In particular, the present invention is effective for mask slicing type semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a plan view of the wiring (structure) of one embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3I is a plan view of a wiring structure of another embodiment of the present invention, and FIG. is a partial sectional view of the same. In the figure, 1 is the first M wiring, 2 is the second layer wiring, 3 is the third layer wiring, 4 is the 4th N wiring, 5 and 6 are connection holes. 10 is the semiconductor chip. Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) Multilayer wiring layers from the first layer to the **th layer are provided alternately orthogonally on six semiconductor substrates, and the wiring layer spacing of the nth layer is set to the (n-2)th layer parallel to the nth layer. 1. A semiconductor device having a structure in which the spacing between the wiring layers is an integral multiple of the wiring layer spacing between the layers, and an n-th wiring layer is located between the (n-2)-th wiring layers. (2), the connection between the **th wiring layer and the (n-2>th) wiring layer is made by interposing the (n-1)th layer, and
connection hole with the (n-1) layer and the (n-1)th layer with the (n-2)th layer.
2. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which the connection holes are provided in different regions.