JP2940045B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a large-scale master slice type semiconductor integrated circuit.

[Conventional technology]

Conventionally, in a master slice type semiconductor integrated circuit, in order to connect functional cells (or logical blocks) to each other, a virtual wiring grid is set for each wiring layer over a part or the whole area of a semiconductor chip, and then the wiring grid is set. This is realized by connecting the wires placed on the grid. The wiring grid set for each wiring layer has a pitch that satisfies an allowable interval according to the wiring width determined from the wiring material and the standard current of the circuit. The signal wiring other than the common wiring such as the power supply wiring is configured by a wiring having a standard width occupying one set grid.

FIG. 3 is a layout diagram showing an example of a conventional semiconductor integrated circuit.

As shown in FIG. 3, row lines 10, 11, 12, 13 provided in a horizontal direction on a semiconductor substrate and column lines 14, 15, 16, 1 provided in a vertical direction.
Wiring 21,2 according to the wiring grid configured by 7,18,19,20
5, 26, 27 are provided, and the clock signal supplied to the input end E at the intersection of the row line 11 and the column line 14 is supplied to the output end F of the wiring 25 branched at the intersection of the row line 10 and the column line 16; The output is distributed to the output end G of the wiring 26 branched at the intersection of the line 10 and the column line 18 and to the output end H of the wiring 27 connected to the intersection of the row line 10 and the column line 20.

The setting of such a wiring grid and the arrangement of the wiring placed on the wiring grid are designed by automatic wiring processing using a computer.

[Problems to be solved by the invention]

In the above-described clock signal distribution wiring formed in the conventional master slice type semiconductor integrated circuit, as shown in FIG. 4, the clock signal waveform input to the input terminal E has the clock signal output terminals F, G, There is a delay as each H is reached. This is generally called clock skew due to the time constant RC due to the impedance R and capacitance C of the wiring. The purpose of the clock signal input from the input terminal E is to operate the logic blocks (for example, flip-flops) connected to each of the output terminals F, G, and H at the same phase at the same time. However, such an operation cannot be expected and causes a malfunction. Therefore, the thicker the wiring, the lower the impedance of the wiring and the smaller the clock skew. However, if only the clock wiring is created thicker than the normal signal on the virtual wiring grid set according to the normal signal,
Since the grid spacing is set so that a normal signal wiring can pass adjacently, a wiring grid adjacent to this wiring cannot be used when a thick clock wiring passes. In addition, handling wirings having different wiring widths for one wiring layer imposes great complexity and load on automatic wiring. In addition, if the pitch of the virtual grid is set to be large in advance according to the thickness of the clock wiring, clock wiring and normal signals can be freely adjacent to each other, but this causes a problem that the size of the semiconductor chip increases. .

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention includes a semiconductor integrated circuit having a clock signal distribution line for distributing a clock signal, which is arranged on a line consisting of a row line virtually set on a semiconductor chip and a column line orthogonal to the row line. In the circuit, the clock signal distribution wiring is connected to an input terminal to which the clock signal is applied and a first wiring extending in the column direction;
A second wiring connected to a first output terminal and arranged at a first distance from the first wiring and extending in the column line direction; and a first wiring connected to a second output terminal. From the first
A third wiring that is arranged at a second distance that is longer than the distance and extends in the column line direction, and a plurality of wirings that connect between the first wiring and the second wiring. A fourth wiring extending in a row line direction, the second wiring and the third wiring;
A fifth wiring extending in the row line direction and having a smaller number of wirings than the number of the fourth wirings.
And the first to fifth wirings form a lattice shape.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

As shown in FIG. 1, row lines 10, 11, 1 provided in the horizontal direction
A virtual wiring grid is composed of 2,13 and column lines 14,15,16,17,18,19,20 provided in the vertical direction, and the wirings 21,22,23 arranged on the row lines 11,12,13 And wiring 24,2 arranged on column lines 14,16,18,20
5, 26 and 27 are provided, and a mesh-like wiring is formed by mutually connecting the wirings on the row lines and the wirings on the column lines at respective intersections.

Here, the clock signal supplied to the input terminal A of the wirings 21, 22, and 23 commonly connected by the wiring 24 is connected to the wirings 21, 22, and 23 at the respective intersections of the row lines 11, 12, and 13 and the column line 16. Output B of wiring 25
And the output end C of the wiring 26 connected to the wirings 21 and 22 at the respective intersections of the row lines 11 and 12 and the column line 18, and the wiring 21 at the intersection of the row lines 11 and the column lines 20.
Is output to each of the output terminals D of the wiring 27 connected to. Therefore, the signal input from the input terminal A is input to the wiring having a markedly lower impedance than the wiring using only one ordinary row line by the wirings 21, 22, 23 and the wiring 24 orthogonal thereto. After the signal propagates to the flip-flop circuit connected to the output terminal B, the number of flip-flop circuits to be operated is reduced by one.
The clock signal is propagated to the flip-flop circuit of the output terminal C using the book, and the clock signal is propagated to the flip-flop circuit of the output terminal D using the wirings 21 and 26.

As described above, since the load is the heaviest at the input terminal A to which the clock signal is input, that is, there are many wirings and flip-flop circuits connected earlier, the impedance must be lowest. Therefore, this is realized by connecting a number of parallel adjacent wirings in parallel. As the load becomes lighter, the number of wirings connected in parallel decreases, and the flip-flop circuit farthest from the clock input terminal is input by one wiring having the same impedance as usual.

The effect of this embodiment is shown in FIG. At the input end A of the clock signal shown in FIG. 1, the transmission delay time is inferior to that of the input end E of the conventional wiring shown in FIG. However, since the impedance of the wiring is low, the transmission delay time from the input terminal A to the output terminals B, C, D is reduced, and the clock skew can be reduced.

FIGS. 2 (a) and 2 (b) are a layout diagram and a sectional view taken along line XX 'showing a second embodiment of the present invention.

As shown in FIGS. 2 (a) and 2 (b), row lines 10, 11, 12, 13 and column lines 14, 15, 16, 13 are virtually formed on an insulating film 38 provided on a semiconductor substrate 37. 17, 18, 19, 20 are provided, wiring is provided on the row line 11, 31, 32, 33 are laminated via interlayer insulating films 34a, 34b, and through holes provided on the interlayer insulating films 34a, 34b on the column lines. Hall 35
a, 35b, 36a, 36b, 36c
The clock signal supplied to the input terminal A by being connected to the wirings 25, 26, 27 arranged on the 0 is distributed to each of the output terminals B, C, D.

In the second embodiment, there is an advantage that the wiring area can be effectively used by using a multilayer wiring.

〔The invention's effect〕

As described above, according to the present invention, a wiring for transmitting the same clock signal on a virtual wiring grid set assuming a normal signal wiring and a wiring adjacent to this wiring are connected in parallel, thereby reducing the wiring. This has the effect of reducing the impedance and reducing the clock skew.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are a layout diagram showing a second embodiment of the present invention, and a sectional view taken along line XX 'of FIG. FIG. 3 is a layout diagram showing an example of a conventional semiconductor integrated circuit, and FIG. 4 is a characteristic diagram showing a clock skew comparing the present invention with a conventional example. 10,11,12,13… Row line, 14,15,16,17,18,19,20… Column line, 21,
22,23,24,25,26,27,31,32,33 ... wiring, 34a, 34b ... interlayer insulation film, 35a, 35b, 36a, 36b, 36c ... through hole, 37 ... semiconductor substrate, 38 ... insulation film , A: Input terminals, B, C, D: Output terminals.

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit having a clock signal distribution line for distributing a clock signal, which is arranged on a wiring grid including a row line virtually set on a semiconductor chip and a column line orthogonal to the row line, The clock signal distribution line is connected to an input terminal to which the clock signal is applied and extends in the column line direction. The first line is connected to a first output terminal and a first line is connected to the first output terminal. A second wiring arranged at a distance and extending in the column line direction, and a second wiring connected to a second output end and separated from the first wiring by a second distance longer than the first distance; A third wiring extending in the column line direction, a plurality of wirings connecting between the first wiring and the second wiring, and a fourth wiring extending in the row line direction; A wiring connecting between the second wiring and the third wiring, A fifth wiring extending in the line direction and having a smaller number of wirings than the number of the fourth wirings, wherein the first wiring to the fifth wiring form a grid shape. Semiconductor integrated circuit.