CN111223439A - GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit - Google Patents
GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit Download PDFInfo
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- CN111223439A CN111223439A CN202010169540.8A CN202010169540A CN111223439A CN 111223439 A CN111223439 A CN 111223439A CN 202010169540 A CN202010169540 A CN 202010169540A CN 111223439 A CN111223439 A CN 111223439A
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- goa circuit
- array substrate
- area
- via holes
- insulating layer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention provides a GOA circuit applied to an array substrate, the array substrate and a manufacturing method of the GOA circuit. The GOA circuit applied to the array substrate comprises a GOA circuit area, a bus area and an insulating layer, wherein the bus area is formed by stacking the GOA circuit area and the GOA circuit area, the insulating layer is arranged between the GOA circuit area and the bus area in a clamping mode, through holes are formed in the insulating layer, and the GOA circuit area is communicated with the bus area through the through holes. Compared with the prior art, the GOA circuit applied to the array substrate and the array substrate provided by the invention have the advantages that the width of the whole frame is reduced, the purpose of ultra-narrow frame of the display panel is achieved, the cost is reduced, and the product competitiveness is improved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display devices, in particular to a GOA circuit applied to an array substrate, the array substrate and a manufacturing method of the GOA circuit.
[ background of the invention ]
The Array substrate line drive (GOA) technology is a technology that directly manufactures a Gate drive circuit On an Array substrate to realize a drive mode of scanning the Gate line by line so as to replace a drive chip manufactured by an external silicon chip. The GOA technology can realize narrow-frame or even no-frame design of products so as to increase the design selection of customers on the display panel process and expand the application field.
However, as shown in fig. 1, the GOA circuit disposed on the frame of the array substrate in the related art includes a GOA circuit region and a bus region horizontally disposed side by side with the GOA circuit region, wherein the ratio of the bus region in the total frame can reach 1/3 or even 1/2, which results in a wider overall frame of the GOA circuit, which does not meet the current trend of a super-narrow frame and does not have product competitiveness and price competitiveness.
Therefore, it is necessary to provide a new GOA circuit applied to an array substrate, an array substrate and a method for fabricating the GOA circuit to solve the above problems.
[ summary of the invention ]
The technical problem that the overall frame of a GOA circuit is wide and the product competitiveness is influenced due to the fact that a bus area and a GOA circuit area in a related technology are horizontally arranged side by side is solved. The invention provides a GOA circuit with a narrow frame and applied to an array substrate.
A GOA circuit applied to an array substrate comprises:
a GOA circuit area;
the bus area and the GOA circuit area are stacked mutually; and
the insulating layer is clamped between the GOA circuit area and the bus area, via holes are formed in the insulating layer, and the GOA circuit area and the bus area are conducted through the via holes.
Preferably, the GOA circuit area includes a plurality of cascaded GOA circuit units, the bus area includes a plurality of signal lines, the number of the via holes disposed on the insulating layer is plural, and the GOA circuit units are electrically connected to the corresponding signal lines through the corresponding via holes.
Preferably, the signal line includes a first signal line, a second signal line, a third signal line and a fourth signal line which are arranged at intervals, and the via holes include a first via hole corresponding to the first signal line, a second via hole corresponding to the second signal line, a third via hole corresponding to the third signal line and a fourth via hole corresponding to the fourth signal line.
Preferably, the first via holes, the second via holes, the third via holes and the fourth via holes are equal in number.
Preferably, the first via hole, the second via hole, the third via hole and the fourth via hole are respectively provided with a plurality of holes, the first via holes are the same in size, the second via holes are the same in size, the third via holes are the same in size, and the fourth via holes are the same in size.
Preferably, the via hole is manufactured by a laser drilling process.
Preferably, the via hole is manufactured by a chemical etching process.
An array substrate, comprising any one of the above-mentioned GOA circuits applied to the array substrate.
A manufacturing method of a GOA circuit applied to an array substrate comprises the following steps:
s1, providing a substrate;
s2, forming a bus area conducting layer on the substrate;
s3, forming an insulating layer covering the bus area conducting layer on the substrate;
s4, forming a via hole in the insulating layer;
and S5, forming a conductive layer of the GOA circuit area on the insulating layer.
A manufacturing method of a GOA circuit applied to an array substrate comprises the following steps:
s1, manufacturing a GOA circuit area;
s2, forming an insulating layer covering the GOA circuit area on the GOA circuit area;
s3, forming a via hole in the insulating layer;
and S4, forming a bus region conductive layer on the insulating layer.
Compared with the prior art, the GOA circuit applied to the array substrate provided by the invention has the advantages that the GOA circuit area and the bus area are mutually stacked, and the circuit conduction between the GOA circuit area and the bus area is realized through the via holes, so that the bus area can complete the original function, the whole width of the GOA circuit can be reduced, the purpose of ultra-narrow frame is achieved, the cost is reduced, and the product competitiveness is improved.
Correspondingly, the array substrate provided by the invention adopts the GOA circuit applied to the array substrate, so that the size of the frame of the array substrate can be greatly reduced, the purpose of ultra-narrow frame is achieved, and the competitiveness of the product is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic diagram illustrating a connection structure between a GOA circuit area and a bus area of a GOA circuit applied to an array substrate in the prior art;
fig. 2 is a schematic view of a connection structure in which a GOA circuit area and a bus area of a GOA circuit applied to an array substrate are stacked up and down according to an embodiment of the present invention;
fig. 3 is a schematic partial cross-sectional view of a GOA circuit applied to an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic partial view of a first step of a method for manufacturing a GOA circuit applied to an array substrate according to a second embodiment of the present invention;
fig. 5 is a schematic view of a partial pattern formed in a second step of the method for manufacturing a GOA circuit applied to an array substrate according to the second embodiment of the present disclosure;
fig. 6 is a schematic partial view of a third step of the second embodiment of the present invention, wherein the third step is performed to form a GOA circuit on an array substrate;
fig. 7 is a schematic partial view of a fourth step of the second embodiment of the present invention, which is implemented in the manufacturing method of the GOA circuit applied to the array substrate;
fig. 8 is a schematic partial view of a fifth step of the method for manufacturing a GOA circuit applied to an array substrate according to the second embodiment of the present invention;
fig. 9 is a schematic partial view of a first step of a method for manufacturing a GOA circuit applied to an array substrate according to a third embodiment of the present invention;
fig. 10 is a schematic view of a partial pattern formed in a second step of the method for manufacturing a GOA circuit applied to an array substrate according to the third embodiment of the present invention;
fig. 11 is a schematic partial view of a third step of the method for manufacturing a GOA circuit applied to an array substrate according to the third embodiment of the present invention;
fig. 12 is a schematic partial view of a fourth step of the method for manufacturing a GOA circuit applied to an array substrate according to the third embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Please refer to fig. 2 and fig. 3 in combination. The invention provides a GOA circuit 100 applied to an array substrate, which comprises a GOA circuit area 10 and a bus area 20, wherein the GOA circuit area 10 and the bus area 20 are arranged in a stacked mode. The bus area 20 and the GOA circuit area 10 are stacked, so that the whole frame of the GOA circuit 100 applied to the array substrate can be reduced, the design of the ultra-narrow frame of the display panel is realized, and the competitiveness of the product is effectively improved.
The GOA circuit 100 applied to the array substrate further includes an insulating layer 30 sandwiched between the GOA circuit area 10 and the bus area 20. A via hole 31 is formed in the insulating layer 30, and the GOA circuit area 10 and the bus area 20 are electrically connected through the via hole 31.
The GOA circuit region 10 includes a plurality of cascaded GOA circuit units 11, the bus region 20 includes a plurality of signal lines 21, the via holes 31 on the insulating layer 30 are provided with a plurality of, the GOA circuit units 11 are electrically connected with the corresponding signal lines 21 through the corresponding via holes 31, so as to transmit clock signals to the corresponding GOA circuit units 11, and the plurality of GOA circuit units 11 are used for generating corresponding gate driving signals to realize accurate control of each scanning line of the array substrate.
Specifically, the number of the clock signals is different for different driving capabilities of the GOA circuits 100 applied to the array substrate, and the higher the driving capability of the GOA circuits 100 applied to the array substrate is, the more the clock signals are. The GOA circuit 100 applied to the array substrate including 4 clock signals CK 1-CK 4 is only described as an example in this embodiment.
Since the number of the clock signals is 4, the number of the signal lines 21 is 4. Preferably, the signal lines 21 are all formed by a single metal layer, which is simple and feasible, and the thickness of the signal lines 21 can be reduced, so that the thickness of the GOA circuit 100 applied to the array substrate can be reduced.
The signal line 21 includes a first signal line 211, a second signal line 212, a third signal line 213, and a fourth signal line 214 that are arranged in parallel and at an interval. Correspondingly, the via holes 31 include a first via hole corresponding to the first signal line 211, a second via hole corresponding to the second signal line 212, a third via hole corresponding to the third signal line 213, and a fourth via hole corresponding to the fourth signal line 214. The first via hole, the second via hole, the third via hole, and the fourth via hole are respectively distributed at different positions of the insulating layer 30. Specifically, in an embodiment, 4 signal lines 21 and a plurality of GOA circuit units 11 are disposed in a staggered manner, so that the first via is located in an overlapping region of the first signal line 211 and a corresponding GOA circuit unit 11 on the insulating layer 30, the second via is located in an overlapping region of the second signal line 212 and a corresponding GOA circuit unit 11 on the insulating layer 30, the third via is located in an overlapping region of the third signal line 213 and a corresponding GOA circuit unit 11 on the insulating layer 30, and the fourth via is located in an overlapping region of the fourth signal line 214 and a corresponding GOA circuit unit 11 on the insulating layer 30.
The first signal line 211, the second signal line 212, the third signal line 213, and the fourth signal line 214 respectively transmit clock signals CK 1-CK 4 to the corresponding GOA circuit units 11 through the first via hole, the second via hole, the third via hole, and the fourth via hole.
Since the via hole 31 itself has a certain level of impedance, in order to make the impedance of each signal line 21 uniform, it is preferable that the number of the first, second, third, and fourth via holes be the same. It should be noted that, the number of the first via hole, the second via hole, the third via hole, and the fourth via hole is not limited in the present invention, and any number of the first via hole, the second via hole, the third via hole, and the fourth via hole may be opened according to actual needs. Similarly, since the via hole 31 has a certain impedance, in order to improve the consistency of the impedance of each signal line 21, when the first via hole, the second via hole, the third via hole and the fourth via hole are respectively provided with a plurality of impedance, it is preferable that the first via holes have the same size, the second via holes have the same size, the third via holes have the same size, and the fourth via holes have the same size. Further, the sizes of the first via hole, the second via hole, the third via hole and the fourth via hole may also be kept the same.
In order to ensure that the via hole 31 is formed in the insulating layer 30, the feasibility of the manufacturing process and the conductivity of the conductive wire passing through the via hole 31 are ensured. Preferably, the via hole 31 can be formed by a laser drilling or chemical etching process.
Meanwhile, the invention also provides an array substrate, which comprises a display area and a non-display area, wherein the non-display area is positioned outside the display area, and the non-display area comprises the GOA circuit 100 applied to the array substrate in the first embodiment. Because the GOA circuit area 10 and the bus area 20 in the GOA circuit 100 applied to the array substrate are stacked together, the overall frame of the GOA circuit 100 applied to the array substrate is reduced, and therefore, the frame size of the array substrate is greatly reduced, which is beneficial to realizing the narrow frame of the display panel.
Example two
Please refer to fig. 4-8. The invention provides a manufacturing method of a GOA circuit applied to an array substrate, which comprises the following steps:
s1, providing the substrate 110;
s2, forming a bus area conductive layer 120 on the substrate 110;
specifically, the bus area conductive layer 120 is formed on the substrate 110 by a physical vapor deposition process. In this embodiment, the bus area conductive layer 120 is provided with four signal lines arranged at intervals. Of course, in other embodiments, the number of the signal lines disposed on the bus area conductive layer 120 may be more or less, and the embodiment is described by taking only four signal lines as an example.
S3, forming an insulating layer 130 covering the bus area conductive layer 120 on the substrate 110;
s4, forming a via hole 140 in the insulating layer 130;
specifically, the via hole 140 may be formed by laser drilling or chemical etching. The signal lines of the bus area conductive layer 120 are exposed by opening the via holes 140. In this embodiment, the insulating layer 130 is provided with via holes 140 at positions corresponding to the four signal lines, the via holes 140 are corresponding to a first via hole, a second via hole, a third via hole and a fourth via hole, and the first via hole, the second via hole, the third via hole and the fourth via hole are isolated from each other and located at different positions of the insulating layer 130. Only one of the first vias is shown in the structure of fig. 7 where it is located in the insulating layer 130.
S5, forming a conductive layer 150 of the GOA circuit region on the insulating layer 130.
Specifically, the conductive layer 150 of the GOA circuit region can be electrically connected to the conductive layer 120 of the bus region through the via 140 on the insulating layer 130.
EXAMPLE III
Please refer to fig. 9-12. The invention provides a manufacturing method of a GOA circuit applied to an array substrate, which comprises the following steps:
s1, manufacturing a GOA circuit area 210;
specifically, the GOA circuit area 210 includes a plurality of GOA circuit units therein.
S2, forming an insulating layer 220 covering the GOA circuit area 210 on the GOA circuit area 210;
s3, forming a via hole 230 on the insulating layer 220;
specifically, the via hole 230 may be formed by laser drilling or chemical etching. The GOA circuit region 210 is exposed by opening the via hole 230, and the via hole 230 is opened at a position where a signal line needs to be connected to the GOA circuit unit.
S4, forming a bus region conductive layer 240 on the insulating layer 220.
Preferably, step S5 is further included, patterning the bus area conductive layer 240, so that the bus area conductive layer 240 forms a plurality of signal lines, and the signal lines are electrically connected to the corresponding GOA circuit units through the vias 230.
Compared with the prior art, the GOA circuit applied to the array substrate provided by the invention has the advantages that the GOA circuit area and the bus area are mutually stacked, and the circuit conduction between the GOA circuit area and the bus area is realized through the via holes, so that the bus area can complete the original function, the whole width of the GOA circuit can be reduced, the purpose of ultra-narrow frame is achieved, the cost is reduced, and the product competitiveness is improved.
Correspondingly, the array substrate provided by the invention adopts the GOA circuit applied to the array substrate, so that the size of the frame of the array substrate can be greatly reduced, the purpose of ultra-narrow frame is achieved, and the competitiveness of the product is improved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A GOA circuit applied to an array substrate comprises:
a GOA circuit area;
the bus area and the GOA circuit area are stacked mutually; and
the insulating layer is clamped between the GOA circuit area and the bus area, via holes are formed in the insulating layer, and the GOA circuit area and the bus area are conducted through the via holes.
2. The GOA circuit applied to the array substrate of claim 1, wherein the GOA circuit area comprises a plurality of cascaded GOA circuit units, the bus area comprises a plurality of signal lines, the number of the via holes formed in the insulating layer is multiple, and the GOA circuit units are electrically connected with the corresponding signal lines through the corresponding via holes.
3. The GOA circuit applied to the array substrate according to claim 2, wherein the signal lines comprise a first signal line, a second signal line, a third signal line and a fourth signal line which are arranged at intervals, and the vias comprise a first via corresponding to the first signal line, a second via corresponding to the second signal line, a third via corresponding to the third signal line and a fourth via corresponding to the fourth signal line.
4. The GOA circuit applied to the array substrate according to claim 3, wherein the first via holes, the second via holes, the third via holes and the fourth via holes are equal in number.
5. The GOA circuit applied to the array substrate according to claim 3, wherein a plurality of the first via holes, a plurality of the second via holes, a plurality of the third via holes and a plurality of the fourth via holes are respectively provided, the first via holes have the same size, the second via holes have the same size, the third via holes have the same size, and the fourth via holes have the same size.
6. The GOA circuit applied to the array substrate according to claim 1, wherein the via hole is formed by a laser drilling process.
7. A GOA circuit applied to an array substrate according to claim 1, wherein the via hole is formed by a chemical etching process.
8. An array substrate, comprising the GOA circuit applied to the array substrate of any one of claims 1 to 7.
9. A manufacturing method of a GOA circuit applied to an array substrate is characterized by comprising the following steps:
s1, providing a substrate;
s2, forming a bus area conducting layer on the substrate;
s3, forming an insulating layer covering the bus area conducting layer on the substrate;
s4, forming a via hole in the insulating layer;
and S5, forming a conductive layer of the GOA circuit area on the insulating layer.
10. A manufacturing method of a GOA circuit applied to an array substrate is characterized by comprising the following steps:
s1, manufacturing a GOA circuit area;
s2, forming an insulating layer covering the GOA circuit area on the GOA circuit area;
s3, forming a via hole in the insulating layer;
and S4, forming a bus region conductive layer on the insulating layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010169540.8A CN111223439A (en) | 2020-03-12 | 2020-03-12 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010169540.8A CN111223439A (en) | 2020-03-12 | 2020-03-12 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
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| CN111223439A true CN111223439A (en) | 2020-06-02 |
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| CN202010169540.8A Pending CN111223439A (en) | 2020-03-12 | 2020-03-12 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114446255A (en) * | 2022-01-20 | 2022-05-06 | Tcl华星光电技术有限公司 | Display panel and display device |
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