JPH05150263A - Active matrix type liquid crystal display element - Google Patents

Active matrix type liquid crystal display element

Info

Publication number
JPH05150263A
JPH05150263A JP31581591A JP31581591A JPH05150263A JP H05150263 A JPH05150263 A JP H05150263A JP 31581591 A JP31581591 A JP 31581591A JP 31581591 A JP31581591 A JP 31581591A JP H05150263 A JPH05150263 A JP H05150263A
Authority
JP
Japan
Prior art keywords
connection
liquid crystal
crystal display
wiring
type liquid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31581591A
Other languages
Japanese (ja)
Inventor
Yoshihiro Asai
義裕 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP31581591A priority Critical patent/JPH05150263A/en
Publication of JPH05150263A publication Critical patent/JPH05150263A/en
Withdrawn legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To provide the active matrix type liquid crystal display element which enables picture elements to be increased in density and number by narrowing down intervals of connection pads and electric conductors and is improved in manufacture yield. CONSTITUTION:Connection electric conductors 103 of signal lines in even columns are arranged in a 1st wiring layer and connection electric conductors 101 of signal lines in odd columns are arranged in a 2nd wiring layer. The 1st wiring layer and 2nd wiring layer are insulated by an insulation layer 108. Thus, the electric conductors are distributed and arranged in the two wiring layers, so the number of electric conductors arranged in each wiring layer is a half as large as the number of electric conductors which are arranged in only one layer as before and the electric conductor intervals d3 are doubled. Thus, the occurrence rate of a short-circuit defect and an open-circuit defect in the manufacture process of the connection electric conductors is decreased to greatly improve the manufacture yield.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はアクティブマトリックス
型液晶表示素子に関するもので、高精細な画素およびそ
の配線を有する場合において特に有効である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and is particularly effective in the case of having a high definition pixel and its wiring.

【0002】[0002]

【従来の技術】近年、液晶表示素子の分野において、高
精細なテレビ表示や大画面なグラフィックディスプレイ
等を実現すべく、アクティブマトリックス型液晶表示素
子の開発が盛んに行なわれ、一部では既に実用化された
ものもある。
2. Description of the Related Art In recent years, in the field of liquid crystal display elements, active matrix type liquid crystal display elements have been actively developed in order to realize high-definition television display and large-scale graphic display, and some of them are already in practical use. Some have been converted.

【0003】このアクティブマトリックス型液晶表示素
子には、各画素の駆動の制御を行なうための手段として
半導体からなるスイッチング素子を用いている。この半
導体スイッチング素子は、通常、各画素につき 1個ずつ
配設されており、外部駆動回路との接続のための走査線
および信号線が 1本ずつ配線される。
In this active matrix type liquid crystal display element, a switching element made of a semiconductor is used as a means for controlling the driving of each pixel. Usually, one semiconductor switching element is provided for each pixel, and one scanning line and one signal line for connecting to an external drive circuit are provided.

【0004】このようなスイッチング素子や走査線や信
号線などは、通常、透過型表示が可能で大面積化も容易
であるなどの理由から、スイッチング素子にはTFT
(薄膜トランジスタ)を、また走査線や信号線などの配
線にはITOなどの透明導電膜を用いて、ガラスなどの
透明絶縁基板上に成膜やエッチングなどフォトファブリ
ケーションによってパターン形成されて配設される。
Such switching elements, scanning lines, signal lines, etc. are usually TFTs for switching elements because of the fact that transmissive display is possible and the area can be easily increased.
(Thin film transistor) and wiring such as scanning lines and signal lines are formed by patterning by photofabrication such as film formation and etching on a transparent insulating substrate such as glass using a transparent conductive film such as ITO. It

【0005】上記のようなアクティブマトリックス型液
晶表示素子の構造を図4に示す。
FIG. 4 shows the structure of the above-mentioned active matrix type liquid crystal display device.

【0006】このアクティブマトリックス型液晶表示素
子は、透明絶縁基板401上にTFT402と透明導電
膜からなる画素電極403と走査線や信号線などの接続
配線404が配設されたアクティブ素子基板405と、
このアクティブ素子基板405に対向して設けられる透
明導電膜からなる対向電極406が全面に配設された対
向基板407と、液晶組成物408とを有し、アクティ
ブ素子基板405と対向基板407とを平行に対向させ
て配置しこれらの基板間に液晶組成物408を挟持さ
せ、この基板の周囲を封着剤409で封着して形成され
ている。
This active matrix type liquid crystal display element includes an active element substrate 405 in which a TFT 402, a pixel electrode 403 made of a transparent conductive film, and a connection wiring 404 such as a scanning line and a signal line are arranged on a transparent insulating substrate 401.
The active element substrate 405 and the counter substrate 407 are provided with a counter substrate 407 having a counter electrode 406 formed of a transparent conductive film provided opposite to the active element substrate 405, and a liquid crystal composition 408. The liquid crystal composition 408 is sandwiched between these substrates arranged in parallel to each other, and the periphery of these substrates is sealed with a sealing agent 409.

【0007】そして図5に示すように、前述の走査線や
信号線などの接続配線404は、画素領域外の周辺部分
に設けられ、その先端部に配設された接続パッド410
にて外部の液晶ドライバLSIのような駆動回路に接続
される。またアクティブ素子基板405の同図D−D´
における断面を図6に示す。
As shown in FIG. 5, the connection wirings 404 such as the above-mentioned scanning lines and signal lines are provided in the peripheral portion outside the pixel region, and the connection pads 410 are provided at the tips thereof.
Is connected to a drive circuit such as an external liquid crystal driver LSI. In addition, the active element substrate 405 shown in FIG.
The cross section at is shown in FIG.

【0008】画素領域501から引き出された接続配線
404とこれに連なる接続パッド410は、絶縁基板6
03のゲート絶縁膜602上に 1層に列設される。
The connection wiring 404 drawn from the pixel region 501 and the connection pad 410 connected to the connection wiring 404 are formed on the insulating substrate 6.
No. 03 gate insulating film 602 is arranged in a single layer.

【0009】しかしながら、このような液晶表示素子に
おいては、接続される駆動回路としての液晶ドライバL
SIにこの接続パッドを接続しなくてはならないため、
液晶ドライバLSIの 1個あたりの出力ピン数である 1
20本から 240本程度のパッドを 1グループにまとめ、ま
たこれらのパッド間の間隔およびこれに接続される接続
配線404の間隔d1 を、液晶ドライバLSIの出力ピ
ン間隔に合わせて画素領域内の信号線502の間隔d2
よりも狭く寄せて配設しなければならない。
However, in such a liquid crystal display element, a liquid crystal driver L as a drive circuit to be connected is used.
Since this connection pad must be connected to SI,
Number of output pins per LCD driver LSI 1
About 20 to 240 pads are grouped into one group, and the interval between these pads and the interval d1 of the connection wiring 404 connected thereto are matched with the output pin interval of the liquid crystal driver LSI to obtain the signal in the pixel area. Distance d2 between lines 502
Must be placed closer together.

【0010】そして近年、テレビやグラフィックディス
プレイ等の高精細な表示を実現するために液晶表示素子
の画素の高密度化や高画素数化が要請されており、これ
に対応するために駆動回路としての液晶ドライバLSI
の出力ピン数はますます増加し、またそのピン間隔は、
例えばTAB(テープオートメーテッドボンディング)
実装方式の液晶ドライバLSIでは 390μm程度、CO
B(チップオンボード)方式の液晶ドライバLSIでは
100μm程度というように、ますます狭小化する傾向に
ある。そしてそのような液晶ドライバLSIの出力ピン
に接続される接続パッド410およびこれに接続される
接続配線404の間隔d1 もますます狭小化されなけれ
ばならなくなっている。特に接続配線404は、接続パ
ッド410よりもかなり長くかつ線幅が細い。
In recent years, in order to realize high-definition display for televisions, graphic displays, etc., there has been a demand for higher density of pixels and a higher number of pixels of liquid crystal display elements. LCD driver LSI
The number of output pins of the
For example, TAB (Tape Automated Bonding)
The mounting type LCD driver LSI is about 390 μm, CO
In the B (chip on board) type LCD driver LSI
It tends to become narrower, such as around 100 μm. Further, the distance d1 between the connection pad 410 connected to the output pin of such a liquid crystal driver LSI and the connection wiring 404 connected thereto must be further narrowed. In particular, the connection wiring 404 is considerably longer and has a smaller line width than the connection pad 410.

【0011】しかしながら、このように接続パッド41
0の間隔およびこれに接続される配線404の間隔d1
の狭小化にともなって、アクティブ素子基板405を製
造するフォトファブリケーションの工程において、隣接
配線間での塵埃などに起因した短絡不良503や断線不
良504が特に接続配線404に多発するという問題が
顕著になってきた。そしてこれはアクティブ素子基板4
05の製造歩留まりの低下の大きな原因になっている。
However, as described above, the connection pad 41
The interval of 0 and the interval d1 of the wiring 404 connected thereto
In the photofabrication process of manufacturing the active element substrate 405, the short circuit defect 503 and the disconnection defect 504 caused by dust or the like between the adjacent wirings particularly frequently occur in the connection wiring 404 due to the narrowing of the active element substrate 405. Has become. And this is the active element substrate 4
This is a major cause of the decrease in the production yield of No. 05.

【0012】[0012]

【発明が解決しようとする課題】本発明はこのような問
題を解決するために成されたもので、その目的は、接続
パッドの間隔の狭小化にともなって発生する信号線や走
査線の接続配線における隣接配線間での短絡不良や断線
不良の問題を解消して、製造歩留まりの低下なくして接
続パッドの間隔を狭小化し画素の高密度化や高画素数化
を実現するアクティブマトリックス型液晶表示素子を提
供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to connect signal lines and scanning lines caused by the narrowing of the spacing between connection pads. Active matrix liquid crystal display that solves the problems of short-circuit defects and disconnection defects between adjacent wiring lines, narrows the spacing between connection pads without decreasing the manufacturing yield, and realizes high pixel density and high pixel count. It is to provide an element.

【0013】[0013]

【課題を解決するための手段】本発明のアクティブマト
リックス型液晶表示素子は、駆動回路接続用の接続パッ
ドと、マトリックス状に交差して配置され前記駆動回路
接続用の接続パッドに接続配線を介して接続する複数本
の走査線および複数本の信号線査線と、前記走査線およ
び前記信号線に接続するスイッチング素子と、前記スイ
ッチング素子に接続する画素電極とが配置されたアクテ
ィブ素子基板と、前記画素電極に対向する対向電極が配
設された対向基板と、前記アクティブ素子基板と前記対
向基板との間に挟持される液晶組成物とを有するアクテ
ィブマトリックス型液晶表示素子において、前記走査線
に接続される前記接続配線と前記信号線に接続される前
記接続配線のうち少なくとも一方を、一本ごとあるいは
複数本ごとに絶縁層を介して異なる層に配置してなるこ
とを特徴としている。
An active matrix type liquid crystal display element of the present invention is arranged so as to intersect with a connection pad for connecting a drive circuit in a matrix form, and a connection wiring is provided to the connection pad for connecting the drive circuit. An active element substrate on which a plurality of scanning lines and a plurality of signal line inspection lines connected to each other, a switching element connected to the scanning line and the signal line, and a pixel electrode connected to the switching element are arranged, In the active matrix type liquid crystal display device having a counter substrate on which a counter electrode facing the pixel electrode is provided, and a liquid crystal composition sandwiched between the active device substrate and the counter substrate, Insulate at least one of the connection wiring to be connected and the connection wiring to be connected to the signal line for each one or for every plurality It is characterized by being disposed in different layers through.

【0014】[0014]

【作用】複数本の走査線の接続配線および複数本の信号
線の接続配線が、それぞれ隣接する 2本の接続配線のう
ち一方は第1の配線層に、また他方は第2の配線層に配
設されている。たとえば偶数番目の走査線の接続配線が
第1の配線層に配設され、その上に絶縁層を介して第2
の配線層として奇数番目の走査線の接続配線が配設され
ている。そして第1の配線層と第2の配線層とは前述の
絶縁層で絶縁されている。このように、2層の配線層に
配線が分配されて配設されているので、一つの配線層あ
たりに配設された接続配線の配線間隔は、従来のように
一層だけに配設された接続配線の配線間隔と比べて 2倍
となる。
With the connection wiring of the plurality of scanning lines and the connection wiring of the plurality of signal lines, one of the two adjacent connection wirings is on the first wiring layer and the other is on the second wiring layer. It is arranged. For example, the connection wirings of the even-numbered scanning lines are arranged in the first wiring layer, and the second wirings are formed thereon with the insulating layer interposed therebetween.
Connection wirings of odd-numbered scanning lines are provided as the wiring layer of. The first wiring layer and the second wiring layer are insulated by the above-mentioned insulating layer. As described above, since the wirings are distributed and arranged in the two wiring layers, the wiring interval of the connection wirings arranged in one wiring layer is set to one layer as in the conventional case. It is twice as large as the wire spacing of the connecting wires.

【0015】このように従来よりも 2倍の接続配線の配
線間隔を有することによって、本発明のアクティブマト
リックス型液晶表示素子はそのアクティブ素子基板の接
続配線の製造工程における短絡不良や断線不良の発生率
を激減させて、製造歩留まりを大幅に向上させることが
できる。
As described above, since the connection wiring has a wiring distance twice as large as that of the conventional one, the active matrix type liquid crystal display device of the present invention causes short circuit failure and disconnection failure in the process of manufacturing the connection wiring of the active element substrate. The rate can be drastically reduced, and the manufacturing yield can be significantly improved.

【0016】[0016]

【実施例】以下、本発明のアクティブマトリックス型液
晶表示素子の一実施例を図面に基づいて詳細に説明す
る。ここでは特に本発明の要点であるアクティブ素子基
板に的を絞って説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an active matrix type liquid crystal display device of the present invention will be described in detail below with reference to the drawings. Here, the active element substrate, which is the main point of the present invention, will be mainly described.

【0017】図1は本発明のアクティブマトリックス型
液晶表示素子の信号線の接続配線およびこれに接続され
た接続パッドを示す平面図である。
FIG. 1 is a plan view showing a connection wiring of signal lines and a connection pad connected to the signal wiring of the active matrix type liquid crystal display element of the present invention.

【0018】また同図のA−A´、B−B´、C−C´
における断面をそれぞれ図2(a)、図2(b)、図2
(c)に示す。
Further, AA ', BB', CC 'in FIG.
2A, 2B and 2 respectively.
It shows in (c).

【0019】図1に示すように、本発明のアクティブマ
トリックス型液晶表示素子は、そのアクティブ素子基板
110上の周辺部、即ち画素領域の外部に、奇数列の信
号線の接続配線101とこれに接続する奇数列の接続パ
ッド102と、偶数列の信号線の接続配線103とこれ
に接続する偶数列の接続パッド104と、この偶数列の
信号線の接続配線103に画素領域111から外に伸び
る偶数列の信号線105を接続するスルーホール106
と、偶数列の接続パッド104を接続するスルーホール
107とを有している。
As shown in FIG. 1, in the active matrix type liquid crystal display device of the present invention, the connection wirings 101 of the odd-numbered signal lines are formed in the peripheral portion of the active element substrate 110, that is, outside the pixel region. The odd-numbered connection pads 102 connected, the even-numbered signal line connection wirings 103, the even-numbered connection pad 104 connected thereto, and the even-numbered signal line connection wirings 103 extend out from the pixel region 111. Through holes 106 for connecting the signal lines 105 in even columns
And through holes 107 for connecting the connection pads 104 in even columns.

【0020】そして図2(b)の断面図に示すように、
この偶数列の信号線の接続配線103が絶縁基板100
の表面上に第1の配線層として、また第1の配線層の上
層に絶縁層108を介して奇数列の信号線の接続配線1
01が第2の配線層として配設されている。
Then, as shown in the sectional view of FIG.
The connection wiring 103 of the signal lines in the even columns is the insulating substrate 100.
On the surface of the first wiring layer and on the upper layer of the first wiring layer through the insulating layer 108, the connection wiring 1 of the odd-numbered signal lines
01 is arranged as the second wiring layer.

【0021】偶数列の信号線の接続配線103は、この
ように絶縁基板100上に第1の配線層として配設され
ているが、これに接続されるべき画素領域から外に伸び
る偶数列の信号線105および偶数列の接続パッド10
4は第2の配線層に配設されている。そこでこれらを図
2(a)に示すようなスルーホール106および図2
(c)に示すようなスルーホール107を設けることで
絶縁層108を貫通して信号線の接続配線103に接続
している。
The connection wirings 103 of the signal lines in the even columns are arranged as the first wiring layer on the insulating substrate 100 as described above, and the connection wirings 103 in the even columns extending outward from the pixel region to be connected thereto. Signal line 105 and connection pad 10 in even columns
4 is arranged in the second wiring layer. Therefore, these are connected to the through hole 106 as shown in FIG.
By providing the through hole 107 as shown in (c), the insulating layer 108 is penetrated and connected to the connection wiring 103 of the signal line.

【0022】一方、走査線の接続配線もこの信号線と同
様に 2層に配線されている。
On the other hand, the connection wiring of the scanning line is also laid out in two layers like this signal line.

【0023】このように、本発明のアクティブマトリッ
クス型液晶表示素子の走査線や信号線の接続配線は 2層
に形成されていることで、各配線層における隣接する配
線の間隔が図1および図2(b)に示すd3 のようにな
り、従来技術の配線のような全配線が平面的に列設され
るときの間隔d1 と比べて約 2倍の幅となる。
As described above, since the connecting wirings of the scanning lines and the signal lines of the active matrix type liquid crystal display element of the present invention are formed in two layers, the distance between the adjacent wirings in each wiring layer is as shown in FIG. 1 and FIG. It becomes d3 shown in FIG. 2 (b), which is about twice as wide as the distance d1 when all the wires like the prior art wires are arranged in a plane.

【0024】このような構成により、本発明のアクティ
ブマトリックス型液晶表示素子はその接続配線の製造工
程における短絡不良の発生率が 1/2程度に減少し、その
製造歩留まりは大幅に向上する。
With such a structure, in the active matrix type liquid crystal display device of the present invention, the occurrence rate of short circuit defects in the manufacturing process of the connection wiring is reduced to about 1/2, and the manufacturing yield is greatly improved.

【0025】次に、本発明のアクティブマトリックス型
液晶表示素子の製造方法を、工程を追って説明する。
Next, a method of manufacturing the active matrix type liquid crystal display element of the present invention will be described step by step.

【0026】図3は本発明のアクティブマトリックス型
液晶表示素子のアクティブ素子基板の製造工程を示す図
である。
FIG. 3 is a diagram showing a manufacturing process of an active element substrate of an active matrix type liquid crystal display element of the present invention.

【0027】まず、図3の(1)に示すように、ガラス
のような絶縁材料からなる絶縁基板100上に第1の配
線層として偶数列の信号線の接続配線103を配設す
る。この偶数列の信号線の接続配線103の隣接配線ど
うしの間隔は前述したように従来の配線の間隔の 2倍に
なっているので、製造工程におけるその短絡不良の発生
する確率は 1/2程度となる。またこのとき画素領域内に
おいてはTFTのゲート電極201および走査線202
が配設される。
First, as shown in (1) of FIG. 3, on the insulating substrate 100 made of an insulating material such as glass, the connection wirings 103 of even-numbered columns of signal lines are provided as a first wiring layer. Since the spacing between adjacent wirings of the connection wiring 103 of the signal lines in the even-numbered columns is twice the spacing between the conventional wirings as described above, the probability of occurrence of short circuit failure in the manufacturing process is about 1/2. Becomes Further, at this time, in the pixel region, the gate electrode 201 of the TFT and the scanning line 202
Is provided.

【0028】次に図3の(2)に示すように、前述の偶
数列の信号線の接続配線103の上に絶縁層108を形
成する。
Next, as shown in FIG. 3B, the insulating layer 108 is formed on the connection wirings 103 of the signal lines in the even columns described above.

【0029】そしてこの絶縁層108の上に、画素領域
内においては図3の(3)、(4)に示すようにa−S
i(アモルファスシリコン)層などからなるTFTスイ
ッチング素子203、画素電極204を形成する。そし
て画素領域の外部、即ちアクティブ素子基板110の周
辺部においては、図2の(5)に示すように、前述の偶
数列の信号線の接続配線103の画素領域からの信号線
105との接続部分および偶数列の接続パッド104と
の接続部分の上の絶縁層にスルーホール106、107
を穿設する。このとき走査線側(図示省略)では、走査
線の接続配線に配設された接続パッド上の絶縁層に開口
が穿設され、走査線側の接続パッドがアクティブ素子基
板110の絶縁層の表面に露出して、外部の液晶駆動回
路の接続ピンと接続可能の状態になる。このような接続
パッド上の絶縁層に開口を穿設する工程は、既に従来技
術にも存在しているので、この開口の穿設と同じ工程内
でスルーホール106、107を穿設することができ
る。即ちこのようなスルーホール106、107を穿設
する工程を別に付加する必要はない。
Then, on the insulating layer 108, in the pixel region, as shown in (3) and (4) of FIG.
A TFT switching element 203 and a pixel electrode 204 composed of an i (amorphous silicon) layer or the like are formed. Then, outside the pixel region, that is, in the peripheral portion of the active element substrate 110, as shown in (5) of FIG. 2, the connection wiring 103 of the above-described even-numbered column signal line is connected to the signal line 105 from the pixel region. Through holes 106 and 107 in the insulating layer above the connection portions and the connection pads with the even-numbered columns of connection pads 104.
To drill. At this time, on the scanning line side (not shown), an opening is formed in the insulating layer on the connection pad arranged in the connection wiring of the scanning line, and the connection pad on the scanning line side is the surface of the insulating layer of the active element substrate 110. It is exposed to and can be connected to the connection pin of the external liquid crystal drive circuit. Since such a step of forming an opening in the insulating layer on the connection pad already exists in the prior art, it is possible to form the through holes 106 and 107 in the same step as the formation of this opening. it can. That is, it is not necessary to separately add a step of forming such through holes 106 and 107.

【0030】次に、図2の(6)に示すように、絶縁層
108の上に第2の配線層として画素領域内では信号線
205を、また画素領域外では奇数列の信号線の接続配
線101と、画素領域から伸びる偶数列の信号線105
と、偶数列の接続パッド104とを配設する。そしてこ
の画素領域から外に伸びた偶数列の信号線105はスル
ーホール106によって、また偶数列の接続パッド10
4はスルーホール107によって、偶数列の信号線の接
続配線103に接続するように配設する。
Next, as shown in (6) of FIG. 2, the signal line 205 is connected as a second wiring layer on the insulating layer 108 in the pixel region, and the signal lines in odd columns are connected outside the pixel region. The wiring 101 and the signal lines 105 in even columns extending from the pixel region
And even-numbered connection pads 104 are arranged. The even-numbered column signal lines 105 extending out from the pixel region are formed by the through holes 106, and the even-numbered column connection pads 10 are formed.
The through holes 107 are arranged so as to be connected to the connection wirings 103 of the signal lines in the even columns.

【0031】この第2の配線層に配設された奇数列の信
号線の接続配線101の隣接する接続配線どうしの間隔
は前述したように従来の接続配線の間隔の 2倍なので、
その短絡不良の発生の確率は 1/2程度となる。また断線
不良の発生の確率も大幅に減少する。
As described above, the distance between the adjacent connection wirings of the connection wirings 101 of the odd-numbered signal lines arranged in the second wiring layer is twice the distance between the conventional connection wirings.
The probability of occurrence of short circuit failure is about 1/2. In addition, the probability of occurrence of disconnection defects is greatly reduced.

【0032】このように、本発明のアクティブマトリッ
クス型液晶表示素子は、絶縁基板100上に第1の配線
層として偶数列の信号線の接続配線103を配設し、そ
の上に絶縁層108を介して第2の配線層として奇数列
の信号線の接続配線101を配設し、従来では絶縁基板
上に 1層に配設していた接続配線を上下 2層に分配して
配設することで、各層ごとの隣接する接続配線の間隔を
従来の 2倍にとることができる。
As described above, in the active matrix type liquid crystal display element of the present invention, the connection wirings 103 of the even-numbered columns of signal lines are arranged as the first wiring layer on the insulating substrate 100, and the insulating layer 108 is formed thereon. Connect the odd-numbered signal line connection wirings 101 as the second wiring layer, and distribute the connection wirings that were conventionally placed in one layer on the insulating substrate to the upper and lower two layers. Thus, the distance between adjacent connection wirings in each layer can be doubled from the conventional one.

【0033】一方、走査線側についても同様に、接続配
線を上下 2層に分配して配設して、その各層ごとの隣接
する接続配線の間隔を従来の 2倍にとることができる。
On the other hand, similarly, on the scanning line side, the connection wiring can be distributed in two layers, that is, upper and lower layers, and the distance between adjacent connection wirings in each layer can be doubled as compared with the conventional one.

【0034】これにより、その接続配線の製造工程にお
ける短絡不良や断線不良の発生率を大幅に減少させ製造
歩留まりを飛躍的に向上させることができる。
As a result, the rate of occurrence of short circuit defects and disconnection defects in the manufacturing process of the connection wiring can be greatly reduced, and the manufacturing yield can be dramatically improved.

【0035】しかも、信号線および走査線の、このよう
な 2層に形成された接続配線は、上述の説明からも判る
ように、画素領域内における信号線と走査線とを絶縁層
を介して上下 2層に配設するような従来技術に係る製造
方法を画素領域外にも応用して、その接続配線やスルー
ホールのパターン形態を変更するだけでよく、従来のフ
ォトファブリケーション技術による成膜やエッチングな
どによる製造工程をそのまま用いることができる。
Moreover, the connection wiring formed in such two layers of the signal line and the scanning line, as can be understood from the above description, connects the signal line and the scanning line in the pixel region through the insulating layer. Applying the manufacturing method according to the conventional technology, such as arranging in two layers above and below, also outside the pixel area, it is only necessary to change the pattern form of the connection wiring and through hole, and the film formation by the conventional photofabrication technology The manufacturing process such as etching or etching can be used as it is.

【0036】従って信号線および走査線の接続配線をこ
のように 2層に形成するための特別な工程を従来の工程
に付加することなく製造歩留まりが大幅に向上するの
で、製造コストは飛躍的に低廉化される。
Therefore, since the manufacturing yield is significantly improved without adding a special process for forming the connection wiring of the signal line and the scanning line in two layers in this way to the conventional process, the manufacturing cost is dramatically increased. It will be cheaper.

【0037】[0037]

【発明の効果】以上詳細に説明したように、本発明のア
クティブマトリックス型液晶表示素子は、信号線および
走査線の接続配線における隣接配線間での短絡不良や断
線不良の問題を解消して、接続パッドの間隔の狭小化を
実現しかつ製造歩留まりの向上を実現することにより、
液晶表示素子の画素の高密度化や高画素数化を実現しな
がら製造コストの飛躍的な低廉化をも実現したアクティ
ブマトリックス型液晶表示素子である。
As described in detail above, the active matrix type liquid crystal display device of the present invention solves the problems of short circuit and disconnection between adjacent wirings in the signal line and scanning line connection wirings. By realizing the narrowing of the connection pad spacing and the improvement of manufacturing yield,
It is an active matrix type liquid crystal display element that realizes a dramatic reduction in manufacturing cost while realizing high density and high number of pixels of the liquid crystal display element.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のアクティブマトリックス型液晶表示素
子の信号線の接続配線およびこれに接続された接続パッ
ドを示す平面図。
FIG. 1 is a plan view showing connection wirings of signal lines and connection pads connected to the connection wirings of an active matrix type liquid crystal display element of the present invention.

【図2】本発明のアクティブマトリックス型液晶表示素
子のアクティブ素子基板の断面図。
FIG. 2 is a sectional view of an active element substrate of an active matrix type liquid crystal display element of the present invention.

【図3】本発明のアクティブマトリックス型液晶表示素
子のアクティブ素子基板の製造工程を示す図。
FIG. 3 is a diagram showing a manufacturing process of an active element substrate of an active matrix type liquid crystal display element of the present invention.

【図4】従来のアクティブマトリックス型液晶表示素子
の構造を示す断面図。
FIG. 4 is a sectional view showing the structure of a conventional active matrix type liquid crystal display element.

【図5】従来のアクティブマトリックス型液晶表示素子
の信号線の接続配線およびこれに接続された接続パッド
を示す平面図。
FIG. 5 is a plan view showing connection wiring of signal lines and connection pads connected to the connection wiring of a conventional active matrix type liquid crystal display element.

【図6】本発明のアクティブマトリックス型液晶表示素
子のアクティブ素子基板の断面図。
FIG. 6 is a sectional view of an active element substrate of an active matrix type liquid crystal display element of the present invention.

【符号の説明】[Explanation of symbols]

100……………絶縁基板 101……………奇数列の信号線の接続配線 102……………奇数列の接続パッド 103……………偶数列の信号線の接続配線 104……………偶数列の接続パッド 105……………画素領域から外に伸びる偶数列の信号
線 106、107…スルーホール 108……………絶縁層 110……………アクティブ素子基板
100 ……………… Insulation substrate 101 ……………… Connection wiring for odd-numbered signal lines 102 ……………… Connection pad for odd-numbered rows 103 …………… Connection wiring for even-numbered signal lines 104 …… ………… Even-numbered row connection pads 105 ……………… Even-numbered row signal lines 106, 107 extending through the pixel region… Through holes 108 ………… Insulating layer 110 …………. Active element substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 駆動回路接続用の接続パッドと、マトリ
ックス状に交差して配置され前記駆動回路接続用の接続
パッドに接続配線を介して接続する複数本の走査線およ
び複数本の信号線査線と、前記走査線および前記信号線
に接続するスイッチング素子と、前記スイッチング素子
に接続する画素電極とが配置されたアクティブ素子基板
と、前記画素電極に対向する対向電極が配設された対向
基板と、前記アクティブ素子基板と前記対向基板との間
に挟持される液晶組成物とを有するアクティブマトリッ
クス型液晶表示素子において、 前記走査線に接続される前記接続配線と前記信号線に接
続される前記接続配線のうち少なくとも一方を、一本ご
とあるいは複数本ごとに絶縁層を介して異なる層に配置
してなることを特徴とするアクティブマトリックス型液
晶表示素子。
1. A plurality of scanning lines and a plurality of signal lines which are arranged so as to intersect with a connection pad for connecting a drive circuit in a matrix and are connected to the connection pad for connecting the drive circuit via a connection wiring. Line, a switching element connected to the scanning line and the signal line, an active element substrate on which a pixel electrode connected to the switching element is arranged, and an opposed substrate on which an opposed electrode opposed to the pixel electrode is arranged. And an active matrix type liquid crystal display element having a liquid crystal composition sandwiched between the active element substrate and the counter substrate, wherein the connection wiring connected to the scanning line and the signal line connected At least one of the connecting wires is arranged in a different layer for each one or for a plurality of wires through an insulating layer. Box-type liquid crystal display element.
JP31581591A 1991-11-29 1991-11-29 Active matrix type liquid crystal display element Withdrawn JPH05150263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31581591A JPH05150263A (en) 1991-11-29 1991-11-29 Active matrix type liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31581591A JPH05150263A (en) 1991-11-29 1991-11-29 Active matrix type liquid crystal display element

Publications (1)

Publication Number Publication Date
JPH05150263A true JPH05150263A (en) 1993-06-18

Family

ID=18069892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31581591A Withdrawn JPH05150263A (en) 1991-11-29 1991-11-29 Active matrix type liquid crystal display element

Country Status (1)

Country Link
JP (1) JPH05150263A (en)

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