JP2006209089A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can narrow a frame size and realize high density wiring without causing defects in a reliability test and without lowering its production yield. <P>SOLUTION: The display device includes an active area that is composed of a plurality of pixels and a plurality of signal supply wiring lines that supply driving signals to the pixels, a plurality of input sections that are disposed outside the active area and function to input the driving signals that are to be supplied to the signal supply wiring lines, and a plurality of connecting wiring lines that connect the signal supply wiring lines and the input sections. Mutually neighboring a first connection wiring line 51 and a second connection wiring line 52 of the connection wiring lines are disposed in different layers via an insulating layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a display device having wirings arranged at high density on the outer periphery of an active area.

  A display device such as a liquid crystal display device includes an active area composed of matrix pixels. The active area is arranged in the vicinity of a plurality of scanning lines extending along the pixel row direction, a plurality of signal lines extending along the pixel column direction, and an intersection between the scanning lines and the signal lines. A switching element, a pixel electrode connected to the switching element, and the like are provided. Each of these scanning lines and each signal line is drawn to the outer periphery of the active area.

  In recent years, along with the demand for an increase in the number of pixels due to high definition and a narrow frame, various wiring lines such as scanning lines and signal lines are adjacent to each other with a narrow line width and a small gap on the outer periphery of the active area. Need to be arranged. However, there is a limit to narrowing the line widths and gaps between wirings due to restrictions on pattern formation accuracy and manufacturing yield. That is, it is extremely difficult to form wirings at a high density in a limited region while suppressing the occurrence of wiring defects such as a short circuit between the wirings and disconnection of each wiring.

As technologies that enable narrow frame and high-density wiring, technologies described in Patent Documents 1 and 2 are known.
JP 2002-268575 A JP 2002-258310 A

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a display capable of narrowing the frame and high-density wiring without causing defects in the reliability test and lowering the manufacturing yield. To provide an apparatus.

A display device according to an aspect of the present invention includes:
An active area composed of a plurality of pixels and a plurality of signal supply wirings for supplying a drive signal to each pixel;
A plurality of input units arranged outside the active area for inputting a drive signal supplied to the signal supply wiring;
A plurality of connection wirings for connecting between the signal supply wiring and the input unit, respectively,
The first connection wiring and the second connection wiring adjacent to each other are arranged in different layers with an insulating layer interposed therebetween.

  According to the present invention, it is possible to provide a display device capable of narrowing the frame and high-density wiring without causing defects in the reliability test and reducing the manufacturing yield.

  A display device according to an embodiment of the present invention will be described below with reference to the drawings.

  As shown in FIG. 1, a liquid crystal display device as an example of a display device includes a liquid crystal display panel 1 having a substantially rectangular flat plate shape. The liquid crystal display panel 1 is composed of a pair of substrates, that is, an array substrate 3 and a counter substrate 4, and a liquid crystal layer 5 held as a light modulation layer between the pair of substrates. The liquid crystal display panel 1 includes a substantially rectangular active area 6 for displaying an image. The active area 6 includes a plurality of pixels PX arranged in a matrix, a plurality of signal supply wirings for supplying a drive signal to each pixel PX, and the like.

  The array substrate 3 is a signal supply wiring arranged in the active area 6, for example, a plurality of scanning lines Y (1, 2, 3,..., M) extending along the row direction of the pixels PX or the pixels PX. A plurality of signal lines X (1, 2, 3,..., N) extending along the column direction are provided. These scanning lines Y and signal lines X are arranged in different layers with an insulating layer interposed therebetween. In addition, the array substrate 3 includes, in the active area 6, in addition to these signal supply wirings, switching elements 7 and switching elements 7 arranged for each pixel PX near the intersection of the scanning lines Y and the signal lines X. A connected pixel electrode 8 is provided.

  The switching element 7 is composed of, for example, a thin film transistor (TFT). The gate electrode 7G of the switching element 7 is electrically connected to the corresponding scanning line Y (or formed integrally with the scanning line). The source electrode 7S of the switching element 7 is electrically connected to the corresponding signal line X (or formed integrally with the signal line). The drain electrode 7D of the switching element 7 is electrically connected to the pixel electrode 8 of the corresponding pixel PX (or formed integrally with the pixel electrode).

  The pixel electrode 8 is formed of a light-transmitting metal material such as indium tin oxide (ITO) in a transmissive liquid crystal display device that selectively transmits backlight and displays an image. The pixel electrode 8 is made of a metal material having light reflectivity such as aluminum (Al) in a reflective liquid crystal display device that selectively reflects external light incident from the counter substrate 4 side and displays an image. It is formed.

  The counter substrate 4 includes a counter electrode 9 and the like common to all the pixels PX in the active area 6. The counter electrode 9 is made of a light-transmissive metal material such as ITO. The array substrate 3 and the counter substrate 4 are arranged with the pixel electrodes 8 and the counter electrodes 9 of all the pixels PX facing each other, and a gap is formed between them. The liquid crystal layer 5 is formed of a liquid crystal composition sealed in the gap between the array substrate 3 and the counter substrate 4.

  In a color display type liquid crystal display device, the liquid crystal display panel 1 includes a plurality of types of pixels, for example, a red pixel that displays red (R), a green pixel that displays green (G), and a blue pixel that displays blue (B). have. That is, the red pixel includes a red color filter that transmits light having a red main wavelength. The green pixel includes a green color filter that transmits light having a green dominant wavelength. The blue pixel includes a blue color filter that transmits light having a blue main wavelength. These color filters are arranged on the main surface of the array substrate 3 or the counter substrate 4.

  The liquid crystal display panel 1 includes a connection wiring group 20, a first connection portion 31, and a second connection portion 32 on the outer peripheral portion 10 located outside the active area 6. The first connection unit 31 can be connected to the drive IC chip 11 that functions as a signal supply source that supplies a drive signal to the signal supply wiring. The second connection unit 32 can be connected to a flexible printed circuit FPC that functions as a signal supply source. In the example shown in FIG. 1, the first connection portion 31 and the second connection portion 32 are disposed on the extending portion 10 </ b> A of the array substrate 3 that extends outward from the end portion 4 </ b> A of the counter substrate 4. . The drive IC chip 11 and the first connection part 31 are electrically and mechanically connected through, for example, an anisotropic conductive film.

  The driving IC chip 11 mounted on the first connection unit 31 of the liquid crystal display panel 1 includes at least a part of the signal line driving unit 11X that supplies a driving signal (video signal) to each signal line X in the active area 6, and It has at least a part of a scanning line driving section 11Y that supplies a driving signal (scanning signal) to each scanning line Y in the active area 6.

  The first connection unit 31 and the second connection unit 32 include a plurality of input units for inputting drive signals supplied to the signal supply wiring. In particular, as shown in FIG. 2, the first connection unit 31 includes as many input units 40 as the number of signal supply wirings or more. That is, the first connection unit 31 includes a Y connection unit 31Y connected corresponding to the scanning line drive unit 11Y of the drive IC chip 11 and an X connection unit 31X connected corresponding to the signal line drive unit 11X. Have. The Y connection unit 31Y includes the same number of input units 40Y as the number of scanning lines Y or more. The X connection section 31X includes the same number of input sections 40X as the number of signal lines X or more.

  The connection wiring group 20 includes a plurality of connection wirings that connect each signal supply wiring and the input unit 40. That is, the connection wiring group 20 includes the same number of connection wirings W as the number of signal supply wirings or more, and the connection for connecting each input section 40Y of the Y connection section 31Y and each scanning line Y. The wiring WY and the connection wiring WX that connects each input unit 40X of the X connection unit 31X and each signal line X are provided. In the example illustrated in FIG. 1, the connection wiring WY is disposed on one end side 10 </ b> B of the outer peripheral portion 10.

  With such a configuration, the scanning line driving unit 11Y is electrically connected to each scanning line Y (1, 2, 3,...) Via the connection wiring WY. That is, the drive signal output from the scanning line driving unit 11Y is supplied to each input unit 40Y of the Y connection unit 31Y in the first connection unit 31, and the corresponding scanning line Y (1, 1) is connected via each connection wiring WY. 2, 3, ...). The switching elements 7 included in each pixel PX in each row are on / off controlled based on the scanning signal supplied from the corresponding scanning line Y.

  Further, the signal line driver 11X is electrically connected to each signal line X (1, 2, 3,...) Via the connection wiring WX. That is, the drive signal output from the signal line drive unit 11X is supplied to each input unit 40X of the X connection unit 31X in the first connection unit 31, and each corresponding signal line X (1, 1) via each connection wiring WX. 2, 3, ...). The switching element 7 included in each pixel PX in each column writes the video signal supplied from the corresponding signal line X to the pixel electrode 8 at the timing when it is turned on.

  In the display device having the above-described configuration, in recent years, the number of pixels has been increased due to high definition, and the demand for narrowing the frame has been limited without causing short circuit between adjacent wirings or disconnection of each wiring. There is an urgent need to dispose wiring at high density in the frame space (outer peripheral part 10).

  Therefore, in the display device according to this embodiment, the connection wirings adjacent to each other are arranged in different layers via insulating layers. That is, as shown in FIG. 3, among the connection wirings, the first connection wiring 51 and the second connection wiring 52 adjacent to each other are arranged in different metal layers with the insulating layer 53 interposed therebetween. With such a configuration, a narrow frame and high-density wiring are possible.

  For example, when the line width of the first connection wiring 51 is a1, the line width of the second connection wiring 52 is a2, and the gap between these connection wirings is b, the pitch of the connection wirings arranged in the same layer, for example, the first The pitch between the connection wirings 51 can be set to (a1 + b) or more and (a1 + a2 + 2 * b) or less, and the frame is narrower and the wiring height is higher than when all the connection wirings are arranged in the same layer with the gap b. Densification is possible.

  In other words, a gap sufficient to prevent the occurrence of a short circuit between adjacent connection wires and the occurrence of disconnection of each connection wire while enabling reduction of the frame space and high density of connection wires arranged on the frame. Since a sufficient line width can be ensured to prevent the occurrence of defects, a display device with high occurrence of defects in a reliability test and a high manufacturing yield can be provided.

  In particular, in the layout in which the scanning signal is supplied from one side of the active area 6 as shown in FIG. 1, it is possible to increase the density of the connection wiring WY connected to the scanning line Y, and one end side of the outer peripheral portion 10. It becomes possible to reduce the frame size in 10B. Further, in a layout in which scanning signals are supplied from both sides of the active area 6, it is possible to reduce the frame size at both ends of the outer peripheral portion 10.

  In addition, the first connection wiring 51 and the second connection wiring 52 that are arranged on these two different layers can be simultaneously formed in a process of patterning various wirings in the active area 6 or a metal material such as an electrode. . For example, the first connection wiring 51 can be formed in the same process as the scanning line Y, and the second connection wiring 52 can be formed in the same process as the signal line X. That is, in forming such a multi-layered connection wiring group, there is no additional process and the manufacturing yield is not deteriorated.

  In short, the first connection wiring 51 and the second connection wiring 52 adjacent to each other can be arranged with a gap smaller than the resolution limit when patterning them. That is, the first connection wiring 51 and the second connection wiring 52 are arranged without overlapping when viewed in a plan view (that is, in the plane of the array substrate). However, in order to arrange these connection wirings in a region having a small frame size, even if these connection wirings appear to overlap each other when viewed in a plan view, the insulating layer 53 is interposed between these connection wirings. Therefore, the occurrence of a short circuit between these connection wirings can be prevented.

  Next, an embodiment will be described. In each embodiment, as an example, the signal supply wiring is the scanning line Y, the signal supply source is the scanning line drive unit 11Y of the drive IC chip 11 mounted on the outer peripheral portion 10, and the input of the Y connection unit 31Y. A case where each of the units 40Y and each scanning line Y are connected by the connection wiring WY will be described.

(Embodiment 1)
As shown in FIG. 4, scanning lines Y (1, 2, 3,...) Are arranged in the active area 6. In the outer peripheral portion 10, connection wirings WY (1, 2, 3,...) That connect the input portions 40Y (1, 2, 3,...) And the input portions 40Y corresponding to the respective scanning lines Y are arranged. ing. In the example shown in FIG. 4, the even-numbered connection wirings WY (2, 4,...) Are arranged in the same layer as the scanning lines Y. Further, the odd-numbered connection wirings WY (1, 3,...) Are arranged in a layer different from the scanning line Y, for example, in the same layer as the signal line X (not shown). Note that all the scanning lines Y in the active area 6 are naturally arranged in the same layer.

  Here, the connection wiring WY (2, 4,...) Is disposed below the connection wiring WY (1, 3,...), And an insulating layer is interposed between these layers. That is, the connection wiring WY (2, 4,...) Corresponds to the first connection wiring 51 shown in FIG. 3, and the connection wiring WY (1, 3,...) Corresponds to the second connection wiring 52. That is, the even-numbered connection wirings WY (2, 4,...) Are arranged in different layers from the adjacent odd-numbered connection wirings WY (1, 3,...).

  These first connection wirings 51 are electrically connected to the scanning line Y by being formed integrally with the corresponding scanning line Y arranged in the same layer. On the other hand, the second connection wiring 52 is electrically connected to the corresponding scanning line Y arranged in a different layer via the first jumper portion J1. Note that such a jumper portion corresponds to a connection portion of discontinuous wiring, and the same applies to the jumper portion in the following description.

  That is, as shown in FIG. 5, the second connection wiring 52 is disposed on the first insulating layer 61 covering the scanning line Y. The first jumper portion J1 is disposed on the second insulating layer 62 that covers the second connection wiring 52. The first jumper portion J1 is electrically connected to the second connection wiring 52 through the first contact hole H1 that penetrates the second insulating layer 62 to the second connection wiring 52, and the first insulating layer 61 In addition, the second insulating layer 62 is electrically connected to the scanning line Y through a second contact hole H2 that penetrates to the scanning line Y. The first jumper portion J1 can be formed at the same time in the formation process of the metal pattern in the active area 6, and can be formed of the same material as the pixel electrode 8, for example. For this reason, a separate process is not added to form the first jumper portion J1.

  The input section 40Y (2, 4,...) Corresponding to the first connection wiring 51 includes a first input terminal 71 that is disposed in the same layer as the first connection wiring 51 and connected to the first connection wiring 51. . The input section 40Y (1, 3,...) Corresponding to the second connection wiring 52 includes a second input terminal 72 that is disposed in the same layer as the second connection wiring 52 and connected to the second connection wiring 52. . The first connection wiring 51 and the first input terminal 71 can be formed in the same process using the same metal material, and are integrally formed here. Similarly, the second connection wiring 52 and the second input terminal 72 can be formed in the same process using the same metal material, and are integrally formed here.

  These input units 40Y (1, 2, 3, 4,...) Include a plurality of input pads connected to the output terminal 11A of the drive IC chip 11. That is, as shown in FIG. 6, the input unit 40Y (2, 4,...) Corresponding to the first connection wiring 51 includes an input pad 71P. The input pad 71P is electrically connected to the first input terminal 71 through a second contact hole H2 that penetrates the first insulating layer 61 and the second insulating layer 62 to the first input terminal 71. The input unit 40Y (1, 3,...) Corresponding to the second connection wiring 52 includes an input pad 72P. The input pad 72P is electrically connected to the second input terminal 72 through a first contact hole H1 that penetrates the second insulating layer 62 to the second input terminal 72. These input pads 71P and 72P can be formed at the same time in the formation process of the metal pattern in the active area 6, and can be formed of the same material as the pixel electrode 8, for example.

  Thus, the drive signal output from the output terminal 11A of the drive IC chip 11 can be supplied to the first connection wiring 51 via the input unit 40Y including the input pad 71P and the first input terminal 71, while the input The second connection wiring 52 can be supplied via the input unit 40Y including the pad 72P and the second input terminal 72.

  According to the first embodiment as described above, the width of the wiring that can prevent the occurrence of a short circuit between the connection wirings arranged on the outer peripheral portion and can suppress the occurrence of the disconnection of each connection wiring. On the other hand, the outer peripheral portion can be reduced and the connection wiring can be densified. Therefore, it is possible to narrow the frame and increase the density of the wiring without causing defects in the reliability test and reducing the manufacturing yield.

  In the first embodiment described above, there is no jumper portion on the wiring passing through the first connection wiring 51 between the scanning line and the input section, and 1 on the wiring passing through the second connection wiring 52. There are two jumper portions (first jumper portions). For this reason, it is desirable to select a material for forming the jumper portion having a relatively low sheet resistance. For example, the jumper portion may be formed of aluminum, which is a metal material having a relatively low resistance for forming the pixel electrode 8 in a reflective liquid crystal display device. In addition, the jumper portion may be formed using a low-resistance metal material in a process separate from the process of forming the metal pattern in the active area 6.

(Embodiment 2)
In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 7, scanning lines Y (1, 2, 3,...) Are arranged in the active area 6. In the outer peripheral portion 10, connection wirings WY (1, 2, 3,...) That connect the input portions 40Y (1, 2, 3,...) And the input portions 40Y corresponding to the respective scanning lines Y are arranged. ing. In the example shown in FIG. 7, even-numbered connection wirings WY (2, 4,...) Are arranged in the same layer as the scanning lines Y and correspond to the first connection wirings 51 shown in FIG. Further, the odd-numbered connection wirings WY (1, 3,...) Are arranged in a different layer from the scanning lines Y and correspond to the second connection wirings 52 shown in FIG. That is, the even-numbered connection wirings WY (2, 4,...) Are arranged in different layers from the adjacent odd-numbered connection wirings WY (1, 3,...).

  These first connection wirings 51 are electrically connected to the scanning line Y by being formed integrally with the corresponding scanning line Y arranged in the same layer. On the other hand, the second connection wiring 52 is electrically connected to the corresponding scanning line Y arranged in a different layer via the first jumper portion J1. The connection structure between the second connection wiring 52 and the corresponding scanning line Y via the first jumper portion J1 is as shown in FIG.

  The input section 40Y (2, 4,...) Corresponding to the first connection wiring 51 is arranged in a layer different from the first connection wiring 51 and connected to the first connection wiring 51 through the second jumper section J2. A first input terminal 71 is included. The input unit 40Y (1, 3,...) Corresponding to the second connection wiring 52 is arranged in the same layer as the second connection wiring 52 and connected to the second connection wiring 52, as in the first embodiment. An input terminal 72 is included. The first input terminal 71 and the second input terminal 72 constituting the input unit 40Y can be formed in the same process using the same metal material, and are formed simultaneously with the second connection wiring 52 here. At this time, the second input terminal 72 and the second connection wiring 52 are integrally formed. That is, the first input terminal 71 and the second input terminal 72 are arranged in the same layer.

  These input units 40Y (1, 2, 3, 4,...) Include a plurality of input pads connected to the output terminal 11A of the drive IC chip 11. That is, as shown in FIG. 8, the input unit 40Y (2, 4,...) Corresponding to the first connection wiring 51 includes an input pad 71P. The input pad 71P is electrically connected to the first connection wiring 51 through a second contact hole H2 that penetrates the first insulating layer 61 and the second insulating layer 62 to the first connection wiring 51, and the second connection pad 51P. The first input terminal 71 is electrically connected through a first contact hole H <b> 1 that penetrates the insulating layer 62 to the first input terminal 71. Here, the input pad 71P also functions as the second jumper portion J2. On the other hand, the input unit 40Y (1, 3,...) Corresponding to the second connection wiring 52 includes an input pad 72P. The structure of the input pad 72P is as described in the first embodiment. These input pads 71P and 72P can be formed at the same time in the formation process of the metal pattern in the active area 6, and can be formed of the same material as the pixel electrode 8, for example.

  Thus, the drive signal output from the output terminal 11A of the drive IC chip 11 can be supplied to the first connection wiring 51 via the input unit 40Y including the input pad 71P and the first input terminal 71, while the input The second connection wiring 52 can be supplied via the input unit 40Y including the pad 72P and the second input terminal 72.

  According to the second embodiment as described above, the same effect as the first embodiment can be obtained. Further, according to the second embodiment, it is possible to arrange the adjacent first and second input terminals in the same layer while arranging the adjacent connection wirings in different layers. For this reason, there is no step between adjacent input terminals, and the shape of the input pad for connecting the drive IC chip 11 can be made uniform, so that connection failure of the drive IC chip 11 can be prevented. Become.

  In addition, the first connection wiring and the second connection wiring adjacent to each other are arranged in different layers, and the same number of jumper portions are interposed between the input portion and the scanning line. That is, the first connection wiring 51 is interposed between the input unit 40Y and the scanning line Y via the second jumper unit J2. The second connection wiring 52 is interposed between the input unit 40Y and the scanning line Y via the first jumper unit J1. For this reason, even if the jumper portion is formed of a relatively high resistance material, the wiring resistance through the jumper portion can be made substantially equal between adjacent connection wirings. Therefore, the influence on the display quality by the drive signal supplied from each connection wiring can be suppressed.

  Further, these first to second jumper portions can be formed in the same process using the same material. For this reason, the separate process for forming the jumper part here is unnecessary.

(Embodiment 3)
In the third embodiment, the same components as those in the first and second embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 9A, scanning lines Y (1, 2, 3,...) Are arranged in the active area 6. In the outer peripheral portion 10, connection wirings WY (1, 2, 3,...) That connect the input portions 40Y (1, 2, 3,...) And the input portions 40Y corresponding to the respective scanning lines Y are arranged. ing. In the example shown in FIG. 9A, the even-numbered connection wirings WY (2, 4,...) Are arranged in the same layer as the scanning lines Y and correspond to the first connection wirings 51 shown in FIG. Further, the odd-numbered connection wirings WY (1, 3,...) Are arranged in a different layer from the scanning lines Y and correspond to the second connection wirings 52 shown in FIG. That is, the even-numbered connection wirings WY (2, 4,...) Are arranged in different layers from the adjacent odd-numbered connection wirings WY (1, 3,...).

  These first connection wirings 51 are electrically connected to the corresponding scanning lines Y arranged in the same layer via the third jumper portion J3. On the other hand, the second connection wiring 52 is electrically connected to the corresponding scanning line Y arranged in a different layer via the first jumper portion J1. The connection structure between the second connection wiring 52 and the corresponding scanning line Y via the first jumper portion J1 is as shown in FIG.

  As shown in FIG. 10, the third jumper portion J <b> 3 is disposed on the second insulating layer 62. The third jumper portion J3 is electrically connected to the first connection wiring 51 through a second contact hole H2 that penetrates the first insulating layer 61 and the second insulating layer 62 to the first connection wiring 51. The first insulating layer 61 and the second insulating layer 62 are electrically connected to the scanning line Y through a second contact hole H2 that penetrates to the scanning line Y. The third jumper portion J3 can be formed at the same time in the metal pattern forming process in the active area 6, and can be formed of the same material as the pixel electrode 8, for example. For this reason, a separate process does not increase in order to form the 3rd jumper part J3.

  The input section 40Y (2, 4,...) Corresponding to the first connection wiring 51 is arranged in a layer different from the first connection wiring 51 and connected to the first connection wiring 51 through the second jumper section J2. A first input terminal 71 is included. The input section 40Y (1, 3,...) Corresponding to the second connection wiring 52 is disposed in the same layer as the second connection wiring 52 and is connected to the second connection wiring 52 via the fourth jumper section J4. A second input terminal 72 is included. The first input terminal 71 and the second input terminal 72 constituting the input unit 40Y can be formed in the same process using the same metal material, and are formed simultaneously with the second connection wiring 52 here. That is, the first input terminal 71 and the second input terminal 72 are arranged in the same layer.

  These input units 40Y (1, 2, 3, 4,...) Include a plurality of input pads connected to the output terminal 11A of the drive IC chip 11. That is, as shown in FIG. 11, the input unit 40Y (2, 4,...) Corresponding to the first connection wiring 51 includes an input pad 71P. The input pad 71P is electrically connected to the first connection wiring 51 through a second contact hole H2 that penetrates the first insulating layer 61 and the second insulating layer 62 to the first connection wiring 51, and the second connection pad 51P. The first input terminal 71 is electrically connected through a first contact hole H <b> 1 that penetrates the insulating layer 62 to the first input terminal 71. Here, the input pad 71P also functions as the second jumper portion J2.

  On the other hand, the input unit 40Y (1, 3,...) Corresponding to the second connection wiring 52 includes an input pad 72P. The input pad 72P is electrically connected to the second connection wiring 52 through the first contact hole H1 that penetrates the second insulating layer 62 to the second connection wiring 52, and the second insulating layer 62 is connected to the second insulation layer 62 by the second contact hole H1. The second input terminal 72 is electrically connected through a first contact hole H1 that penetrates to the input terminal 72. Here, the input pad 72P also functions as the fourth jumper portion J4.

  These input pads 71P and 72P can be formed at the same time in the formation process of the metal pattern in the active area 6, and can be formed of the same material as the pixel electrode 8, for example.

  Thus, the drive signal output from the output terminal 11A of the drive IC chip 11 can be supplied to the first connection wiring 51 via the input unit 40Y including the input pad 71P and the first input terminal 71, while the input The second connection wiring 52 can be supplied via the input unit 40Y including the pad 72P and the second input terminal 72.

  According to the third embodiment as described above, the same effect as the second embodiment can be obtained.

  In addition, the first connection wiring and the second connection wiring adjacent to each other are arranged in different layers, and the same number of jumper portions are interposed between the input portion and the scanning line. That is, the first connection wiring 51 is interposed between the input unit 40Y and the scanning line Y via the second jumper unit J2 and the third jumper unit J3. The second connection wiring 52 is interposed between the input unit 40Y and the scanning line Y via the fourth jumper unit J4 and the first jumper unit J1. For this reason, even if the jumper portion is formed of a relatively high resistance material, the wiring resistance through the jumper portion can be made substantially equal between adjacent connection wirings. Therefore, the influence on the display quality by the drive signal supplied from each connection wiring can be suppressed.

  The first to fourth jumper portions can be formed in the same process using the same material. For this reason, the separate process for forming the jumper part here is unnecessary.

  In the third embodiment described above, the third jumper part J3 and the fourth jumper part J4 connect the wirings arranged in the same layer to each other, or the wirings arranged in the same layer and the input terminal. It functions as a dummy jumper. That is, each connection wiring may have a different wiring length from the input unit to the scanning line. In this case, the resistance difference between the connection wirings can be made closer to zero by adjusting the resistance value of the dummy jumper portion. Further, by providing such a dummy jumper portion, it is possible to align the layers on which the input terminals and the scanning lines are arranged. That is, the dummy jumper part also has a layer replacement function. Therefore, as shown in FIG. 9B, all the input terminals and all the scanning lines can be arranged in the same layer.

  In the first to third embodiments described above, the first connection wiring 51 and the second connection wiring 52 adjacent to each other are not necessarily formed of the same material. For example, the first connection wiring 51 is formed in the same process as the scanning line Y, and the material forming these has the sheet resistance R1. In addition, the second connection wiring 52 is formed in the same process as the signal line X, and the material forming these has the sheet resistance R2. When the first connection wiring 51 and the second connection wiring 52 are formed with the same line width, a resistance difference occurs between the wirings.

  Therefore, as shown in FIG. 12, the ratio (a1 / R1) of the line width a1 to the sheet resistance R1 of the first connection wiring 51 is the ratio (a2 / R2) of the line width a2 to the sheet resistance R2 of the second connection wiring 52. ). That is, since the sheet resistance of each material is an eigenvalue, the resistance difference between the wirings can be made close to zero by adjusting the line width of each connection wiring according to these sheet resistances.

  As described above, according to the display device according to this embodiment, among the plurality of connection wirings arranged in the outer peripheral portion of the active area, the connection wirings adjacent to each other are arranged in different layers. As a result, the outer peripheral portion can be reduced (narrow frame), and the outer peripheral portion wiring can be arranged at a high density (high density wiring). In addition, even when such a narrow frame and high-density wiring are performed, the line width of each wiring and the gap between adjacent wirings can be sufficiently secured, and the occurrence of defects in the reliability test and the manufacturing yield can be ensured. Can be improved.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the gist of the invention in the stage of implementation. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

  For example, the display device of the present invention is not limited to the liquid crystal display device described above, and may be another display device such as an organic electroluminescence display device using a self-luminous element as a display element.

  In the above-described embodiments, the signal supply wiring has been described as being a scanning line. However, the signal supply wiring may be a signal line or may include other wiring arranged on the outer peripheral portion of the array substrate. The signal supply source is the drive IC chip mounted on the array substrate, but the drive IC chip 11 is not directly mounted on the liquid crystal display panel 1, for example, connected to the second connection portion 32. In the case of a configuration in which a signal supply source is provided in the flexible printed circuit FPC, etc., the input unit provided in the second connection unit may have a structure as described in each of the above embodiments. .

  Further, in the second and third embodiments described above, the even-numbered connection wirings WY (2, 4,...) Correspond to the first connection wirings 51 arranged in the same layer as the scanning lines Y, and the odd-numbered connection wirings WY. In the above description, (1, 3,...) Corresponds to the second connection wiring 52 arranged in a layer different from the scanning line Y, but the even-numbered connection wiring WY (2, 4,...) Is the scanning line Y. .., And the odd-numbered connection wirings WY (1, 3,...) Correspond to the first connection wirings 51 arranged in the same layer as the scanning lines Y. You may comprise.

  In the second to third embodiments described above, the input section 40Y (2, 4,...) Corresponding to the first connection wiring 51 includes the first input terminal 71 arranged in a different layer from the first connection wiring 51. In the above description, the input unit 40Y (1, 3,...) Corresponding to the second connection wiring 52 includes the second input terminal 72 disposed in the same layer as the second connection wiring 52. Is not limited to the example described here, and the input unit 40Y (2, 4,...) May include the first input terminal 71 arranged in the same layer as the first connection wiring 51. The input unit 40Y (1, 3,...) May include the second input terminal 72 arranged in a layer different from the second connection wiring 52. Further, these input units may include the first connection wiring. 51 and the second connection wiring may be arranged in a different layer.

FIG. 1 schematically shows a configuration of a liquid crystal display panel of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a configuration example of the first connection portion in the liquid crystal display panel shown in FIG. FIG. 3 is a diagram for explaining an arrangement example of adjacent first connection wirings and second connection wirings. FIG. 4 is a diagram schematically illustrating the layout of the scanning lines, connection wirings, and input units in the first embodiment. FIG. 5 is a cross-sectional view schematically showing a structure when the jumper portion connecting the scanning line and the connection wiring shown in FIG. 4 is cut along an AA line. FIG. 6 is a cross-sectional view schematically showing a structure when the connection wiring and the input part are cut along the line BB when the driving IC chip is connected to the input part shown in FIG. FIG. 7 is a diagram schematically showing a layout of scanning lines, connection wirings, and an input unit in the second embodiment. FIG. 8 is a cross-sectional view schematically showing the structure when the connection wiring and the input section are cut along the CC line when the drive IC chip is connected to the input section shown in FIG. FIG. 9A is a diagram schematically illustrating a layout of a scanning line, a connection wiring, and an input unit in the third embodiment. FIG. 9B is a diagram schematically illustrating a layout of scanning lines, connection wirings, and an input unit according to the third embodiment. FIG. 10 is a cross-sectional view schematically showing a structure when the jumper portion connecting the scanning line and the connection wiring shown in FIG. 9A is cut along the DD line. FIG. 11 is a cross-sectional view schematically showing a structure when the connection wiring and the input part are cut along the line EE when the drive IC chip is connected to the input part shown in FIG. 9A. FIG. 12 is a diagram for explaining the relationship of the ratio of the line width to the sheet resistance of the adjacent connection wiring.

Explanation of symbols

  PX ... Display pixel Y ... Scanning line X ... Signal line FPC ... Flexible wiring board W (X, Y) ... Connection wiring J1 ... First jumper part J2 ... Second jumper part J3 ... Third jumper part J4 ... Fourth jumper part DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel 3 ... Array substrate 4 ... Opposite substrate 5 ... Liquid crystal layer 6 ... Effective display part 7 ... Switching element 8 ... Pixel electrode 9 ... Counter electrode 10 ... Outer peripheral part 11 ... Drive IC chip 11X ... Signal line drive part 11Y ... Scanning line drive unit 20 ... Connection wiring group 31 ... First connection part 31Y ... Y connection part 31X ... X connection part 32 ... Connection part 40 (X, Y) ... Input part 51 ... First connection wiring 52 ... Second connection Wiring 53 ... Insulating layer 61 ... First insulating layer 62 ... Second insulating layer 71 ... First input terminal 71P ... Input pad 72 ... Second input terminal 72P ... Input pad

Claims (12)

An active area composed of a plurality of pixels and a plurality of signal supply wirings for supplying a drive signal to each pixel;
A plurality of input units arranged outside the active area for inputting a drive signal supplied to the signal supply wiring;
A plurality of connection wirings for connecting between the signal supply wiring and the input unit, respectively,
The display device, wherein the first connection wiring and the second connection wiring adjacent to each other are arranged in different layers with an insulating layer interposed therebetween. The first connection wiring is disposed in the same layer as the signal supply wiring and connected to the signal supply wiring,
The display device according to claim 1, wherein the second connection wiring is disposed in a layer different from the signal supply wiring and is connected to the signal supply wiring through a jumper portion. The first connection wiring is disposed in the same layer as the signal supply wiring and connected to the signal supply wiring through a jumper portion,
The display device according to claim 1, wherein the second connection wiring is disposed in a layer different from the signal supply wiring and is connected to the signal supply wiring through a jumper portion.   The input unit is disposed in the same layer as the first connection wiring and connected to the first connection wiring, and is disposed in the same layer as the second connection wiring and connected to the second connection wiring. The display device according to claim 1, further comprising a connected second input terminal.   The input section is disposed in a layer different from the first connection wiring and is disposed in the same layer as the second connection wiring, and a first input terminal connected to the first connection wiring through a jumper section; The display device according to claim 1, further comprising: a second input terminal connected to the second connection wiring.   The input section is disposed in a layer different from the first connection wiring and is disposed in the same layer as the second connection wiring, and a first input terminal connected to the first connection wiring through a jumper section; The display device according to claim 1, further comprising: a second input terminal connected to the second connection wiring via a jumper portion.   The display device according to claim 1, wherein the first connection wiring and the second connection wiring are provided with the same number of jumper portions between the input portion and the signal supply wiring.   The display device according to claim 7, wherein the jumper portion is formed of the same material. The active area includes a pixel electrode disposed in each pixel,
The display device according to claim 7, wherein the jumper portion is formed of the same material as the pixel electrode.   The display device according to claim 1, wherein a ratio of a line width to a sheet resistance of the first connection wiring is substantially equal to a ratio of a line width to a sheet resistance of the second connection wiring.   The display device according to claim 1, wherein the input unit includes an input pad connected to an output terminal of a signal supply source that supplies a drive signal to the signal supply wiring. The signal supply wiring includes a plurality of scanning lines extending along the row direction of the pixels, and a plurality of signal lines extending along the column direction of the pixels in a layer different from the scanning lines,
The display device according to claim 1, wherein the first connection wiring is arranged in the same layer as the signal line, and the second connection wiring is arranged in the same layer as the scanning line.

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