JP2019070845A - Display device - Google Patents

Abstract

To efficiently arrange a plurality of wires in a frame area of a display device.SOLUTION: A circuit part of a display device LCD1 comprises: a display element part in which a plurality of display elements are arranged in a position overlapping with a display area where a display function layer is formed; an input part which transmits a signal for driving the display function layer on the display element part; and a lead-out wiring part LD electrically connecting the display element part and the input part. The lead-out wiring part LD includes a plurality of laminated wiring layers and the plurality of wiring layers include a wiring layer L1 on which a plurality of wires WL1 of wiring width W1 are formed and a wiring layer L2 on which a plurality of wires WL2 of wiring width W2 narrower than the wiring width W1 are formed. The number of the plurality of wires WL2 is greater than the number of the plurality of wires WL1.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a display device, for example, to a technology effectively applied to a display device having a plurality of lead wirings for transmitting signals to a plurality of display elements formed in a display region.

  There is a display device which transmits a signal to a plurality of display elements formed in a display region via a plurality of lead wirings and displays an image.

  For example, Japanese Patent Laid-Open No. 2007-164219 (Patent Document 1) describes a technique for forming a plurality of gate connection lines connected to a plurality of gate lines formed in a pixel region in a plurality of wiring layers. There is.

JP 2007-164219 A

  The display device includes, for example, a display functional layer such as a liquid crystal layer or a light emitting layer using electroluminescence. In addition, the display device includes a plurality of display elements such as transistors formed in a display region. In a display device, signals are transmitted to a plurality of display elements, and an image is displayed by driving the display elements.

  In order to transmit signals to the plurality of display elements, a large number of signal lines are required. The number of signal lines increases as the definition of the display image increases. In addition, for a display device, a technique for reducing the area of a peripheral region which is a non-display portion surrounding the periphery of a display region or a portion called a frame region is required. In the frame area, a lead that is connected to the signal line and supplies a signal to the signal line is formed. That is, in order to improve the performance of the display device, a large number of lead lines need to be efficiently laid out in the frame area.

  Therefore, the inventor of the present application studies a technique for improving the wiring density of the lead wires by allocating and providing a large number of lead wires in the plurality of wiring layers stacked via the insulating film, and finds the following problems. The Note that the leader line is connected to the signal line in the display area, and is considered to be a part of the signal line, so the leader line is hereinafter also referred to as a signal line.

  That is, when a plurality of signal lines are stacked, the signal lines interfere with each other, which causes noise. In addition, when the design rule for defining the minimum value of the wiring width and the distance between the wirings is different for each wiring layer due to the reason for the manufacturing process, etc., the wiring formed in the upper wiring layer and the wiring layer in the lower layer are formed. It has been found that, if the arranged wirings are alternately arranged, it may not be possible to sufficiently improve the wiring density of the signal lines.

  An object of the present invention is to provide a technique for efficiently arranging a plurality of wirings in a frame region of a display device.

A display device according to an aspect of the present invention includes a substrate including a first surface, a display functional layer provided on the first surface of the substrate, and the display functional layer formed on the first surface of the substrate. And a circuit unit for driving the
The first surface includes a display element unit in which a plurality of display elements for driving the display functional layer are arranged, an input unit to which a signal supplied to the display element unit is input, and the display element unit And a lead-out wiring portion electrically connected to the input portion;
The lead wiring portion has a plurality of wiring layers stacked via an insulating film,
In the plurality of wiring layers, a first wiring layer in which a plurality of first wirings having a first wiring width is formed, and a plurality of second wirings having a second wiring width narrower than the first wiring width are provided. And the formed second wiring layer,
The number of the plurality of second wires is greater than the number of the plurality of first wires.

Further, as another aspect, the first surface of the substrate has a first side extending in a first direction, a second side located opposite to the first side, and a second side orthogonal to the first direction. A third side extending in two directions, and a fourth side opposite to the third side,
Between the first side of the substrate and the display element portion, the input portion and the lead-out wiring portion are sequentially provided from the first side.
The length of the input portion in the first direction may be shorter than the length of the display element portion in the first direction.

Further, as another aspect, the first surface of the substrate has a first side extending in a first direction, a second side located on the opposite side of the first side, and a first side orthogonal to the first direction. A third side extending in two directions, and a fourth side opposite to the third side,
The lead wiring portion is
A first portion between the display element portion and the input portion, the plurality of lead wirings including the plurality of first wirings and the plurality of second wirings extending in the second direction;
Between the first portion and the input portion, a second portion extending along a third direction in which the plurality of lead-out lines intersect the second direction and the first direction;
A third portion between the second portion and the input portion, the plurality of lead wirings extending in the second direction;
Have
In a plan view, the plurality of first wirings and the plurality of second wirings may not overlap with each other.

Further, as another aspect, in the second portion of the lead-out wiring portion,
The plurality of first wires are arranged at a first distance,
The plurality of second wires may be arranged at a second separation distance smaller than the first separation distance.

  As another aspect, in plan view, a plurality of the plurality of second wirings may be respectively arranged between the adjacent first wirings among the plurality of first wirings.

In another aspect, each of the plurality of display elements arranged in the display element portion is a transistor having a gate electrode,
The gate electrode may be formed in the same layer as the first wiring layer.

  Further, as another aspect, the plurality of first wirings and the plurality of second wirings may be formed of metal materials of different types.

Further, as another aspect, the plurality of wiring layers further include a third wiring layer in which a plurality of third wirings having a third wiring width wider than the second wiring width is formed,
The number of the plurality of second wires may be larger than the number of the plurality of third wires.

In another embodiment, a first insulating film is provided between the first wiring layer and the second wiring layer.
A second insulating film thicker than the first insulating film is provided between the second wiring layer and the third wiring layer,
In a plan view, the plurality of first wires and the plurality of second wires do not overlap each other, and the plurality of third wires are selected from the plurality of first wires and the plurality of second wires. It may overlap with part.

  In another aspect, the plurality of first wires and the plurality of second wires do not overlap each other in plan view, and the plurality of second wires and the plurality of third wires overlap each other. Alternatively, the plurality of third wires may overlap the plurality of first wires.

Further, as another aspect, the first surface of the substrate has a first side extending in a first direction, a second side located on the opposite side of the first side, and a first side orthogonal to the first direction. A third side extending in two directions, and a fourth side opposite to the third side,
The lead wiring portion is
Between the display element portion and the input portion, a plurality of lead wirings including the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings extend along the second direction. One part,
Between the first portion and the input portion, a second portion extending along a third direction in which the plurality of lead-out lines intersect the second direction and the first direction;
A third portion between the second portion and the input portion, the plurality of lead wirings extending in the second direction;
Have
A first insulating film which is an inorganic insulating film is provided between the first wiring layer and the second wiring layer,
A second insulating film which is an organic insulating film is provided between the second wiring layer and the third wiring layer,
The third portion of the lead-out wiring portion may be provided with an opening extending along the first direction so as to penetrate the second insulating film in the thickness direction.

Moreover, the display apparatus which is the other one aspect | mode is formed in the said 1st surface of the board | substrate provided with a 1st surface, the display functional layer formed in the said 1st surface of the said board | substrate, and the said substrate, The said display function And circuitry for driving the layer;
The circuit unit is a display element unit in which a plurality of display elements are arranged at a position overlapping the display region in which the display function layer is formed, and an input unit for transmitting a signal for driving the display function layer to the display element unit. And a lead-out wiring portion electrically connecting the display element portion and the input portion;
The lead wiring portion has a plurality of stacked wiring layers,
In the plurality of wiring layers, a first wiring layer in which a plurality of first wires are formed at a first distance and a plurality of second wires are formed in a second distance smaller than the first distance. And a second wiring layer,
The number of the plurality of second wires is greater than the number of the plurality of first wires.

It is a top view showing an example of a display of an embodiment. It is sectional drawing along the AA of FIG. It is an expanded sectional view of the B section of FIG. It is an expanded sectional view of the C section of FIG. It is an enlarged plan view which shows typically the layout of the lead-out wiring part shown in FIG. FIG. 7 is an enlarged plan view showing a layout example in the case where a plurality of wirings are drawn by two wiring layers in the lead wiring portion shown in FIG. 1; It is a study example corresponding to FIG. 6, which is an enlarged plan view showing a layout example in the case where a plurality of wires are drawn by a single layer wiring layer. It is another study example corresponding to FIG. 6, which is an enlarged plan view showing a layout example in the case where a plurality of wirings are routed by two wiring layers. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view which shows the structural example of the display element provided in the display element part shown in FIG. FIG. 11 is an enlarged cross-sectional view showing a structural example of electrically connecting the wiring of the first wiring layer and the wiring of the second wiring layer shown in FIGS. 6 and 10; FIG. 7 is an enlarged plan view showing a layout example in the case where a plurality of wirings are drawn by three wiring layers, which is a modification of FIG. 6; It is an expanded sectional view along the AA of FIG. FIG. 14 is an enlarged plan view showing a layout example in the case where some of the plurality of wires overlap in the thickness direction, which is a modification example of FIG. 13; It is an expanded sectional view along the AA of FIG. FIG. 18 is an enlarged cross-sectional view showing a structural example of a portion for electrically connecting the wirings of a plurality of wiring layers in the display device shown in FIGS. 13 and 15;

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The disclosure is merely an example, and it is naturally included within the scope of the present invention as to what can be easily conceived of by those skilled in the art as to appropriate changes while maintaining the gist of the invention. In addition, the drawings may be schematically represented as to the width, thickness, shape, etc. of each portion in comparison with the actual embodiment in order to clarify the description, but this is merely an example, and the interpretation of the present invention is not limited. It is not limited. In the specification and the drawings, the same or related reference numerals are given to the same elements as those described above with reference to the drawings, and the detailed description may be appropriately omitted.

  Further, the technology described in the following embodiment can be widely applied to a display device provided with a mechanism for supplying a signal from the periphery of the display area to a plurality of elements in the display area provided with the display functional layer. Examples of the display device as described above include various display devices such as a liquid crystal display device and an organic EL (Electro-Luminescence) display device. In the following embodiments, a liquid crystal display device will be described as a representative example of a display device.

  Liquid crystal display devices are roughly classified into the following two types according to the application direction of an electric field for changing the alignment of liquid crystal molecules of a liquid crystal layer which is a display functional layer. That is, as a first classification, there is a so-called vertical electric field mode in which an electric field is applied in the thickness direction (or the out-of-plane direction) of the display device. The vertical electric field mode includes, for example, a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. In addition, as a second classification, there is a so-called horizontal electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. The horizontal electric field mode includes, for example, an IPS (In-Plane Switching) mode, and an FFS (Fringe Field Switching) mode which is one of the IPS modes. The techniques described below can be applied to any of the vertical electric field mode and the horizontal electric field mode, but in the embodiments described below, the display device of the horizontal electric field mode will be described by way of example.

<Basic Configuration of Display Device>
First, the basic configuration of the display device will be described. FIG. 1 is a plan view showing an example of the display device of the present embodiment, and FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 3 is an enlarged cross-sectional view of a portion B of FIG. 4 is an enlarged cross-sectional view of a portion C of FIG.

  In FIG. 1, the contour of the display unit DP is indicated by a two-dot chain line in order to make it easy to see the boundary between the display unit DP and the frame unit (peripheral unit) FL in plan view. In addition, the plurality of wirings WL illustrated in FIG. 1 extend from the peripheral region of the display unit DP to a region overlapping the display unit DP. However, in FIG. 1, the wiring WL is omitted in a region overlapping with the display portion DP for easy viewing. Further, FIG. 2 is a cross-sectional view, but hatching is omitted for easy viewing.

  As shown in FIG. 1, the display device LCD 1 according to the present embodiment has a display unit DP which is a display region in which an image visually recognizable from the outside is formed according to an input signal. In addition, the display device LCD1 has a frame portion FL which is a non-display region provided in a frame shape around the display portion DP in plan view. Although the display area of the present display device has a rectangular shape, the display area may be a polygon or a circle. Further, the display area may extend to the vicinity of the end portion of the display device. In this case, the peripheral area of the display area does not have a frame shape, but even in this case, it is referred to as a frame portion.

  Further, the display device LCD 1 has a structure in which a liquid crystal layer which is a display function layer is formed between a pair of substrates disposed opposite to each other. That is, as shown in FIG. 2, the display device LCD 1 includes a substrate FS on the display surface side, a substrate BS located on the opposite side of the substrate FS, and a liquid crystal layer LCL disposed between the substrate FS and the substrate BS (FIG. 3). See).

  Further, in plan view, the substrate BS shown in FIG. 1 has a side BSs1 extending along the X direction, a side BSs2 opposite to the side BSs1, a side BSs3 extending along the Y direction orthogonal to the X direction, and a side BSs3. And the side BSs4 opposite to. The distances from the side BSs2, the side BSs3, and the side BSs4 of the substrate BS shown in FIG. 1 to the display part DP are approximately the same and shorter than the distance from the side BSs1 to the display part DP. Hereinafter, in the present application, when the peripheral portion of the substrate BS is described, one of the side BSs1, the side BSs2, the side BSs3, and the side BSs4 that constitute the outer edge of the substrate BS is meant. Moreover, when it only describes as a peripheral part, the peripheral part of board | substrate BS is meant.

  Further, the liquid crystal layer LCL provided in the display unit DP shown in FIG. 1 is driven for each pixel (specifically, a sub-pixel) in accordance with a signal applied to the circuit unit CC.

  The circuit unit CC is connected to a display element unit DPQ in which a plurality of display elements are arranged at a position overlapping with the display unit DP. The plurality of display elements provided in the display element unit DPQ are provided in a matrix for each pixel (specifically, sub-pixel) and perform switching operation. In this embodiment, the plurality of display elements are transistors called thin film transistors (TFTs) formed on a substrate.

  In addition, the circuit portion CC is provided in the frame portion FL around the display portion DP, and includes a plurality of wirings WL electrically connected to a plurality of display elements of the display element portion DPQ. The circuit portion CC for driving the display functional layer is electrically connected to the display element portion DPQ, and inputs driving signals and video signals to the plurality of display elements of the display element portion DPQ through the plurality of wirings WL. , Input part IPC is included. In the example shown in FIG. 1, the semiconductor chip CHP in which the drive circuit DR1 for image display and the control circuit CNT1 are formed is mounted on the input unit IPC.

  Further, in the example illustrated in FIG. 1, the input unit IPC is provided between the side BSs1 of the substrate BS and the display unit DP in the frame unit FL of the display device LCD1. Further, between the side BSs1 of the substrate BS and the display unit DP, a lead-out wiring portion LD in which a plurality of wirings WL are formed is provided. The display element unit DPQ and the input unit IPC are electrically connected via the lead-out wiring unit LD. The detailed structure of the lead-out wiring portion LD will be described later.

  Further, the display device LCD 1 has a seal portion formed in the frame portion FL in a plan view. The seal portion is formed so as to continuously surround the periphery of the display portion DP, and the substrate FS and the substrate BS shown in FIG. 2 are adhesively fixed by the seal material provided in the seal portion. Thus, the liquid crystal layer LCL (see FIG. 3), which is a display function layer, can be sealed by providing the seal portion around the display portion DP.

  Further, as shown in FIG. 2, on the back surface BSb side of the substrate BS of the display device LCD1, a polarizing plate PL2 for polarizing the light generated from the light source LS is provided. The polarizing plate PL2 is fixed to the substrate BS. On the other hand, on the front surface FSf side of the substrate FS, a polarizing plate PL1 is provided. The polarizing plate PL1 is fixed to the substrate FS.

  Although FIG. 2 exemplarily shows basic components for forming a display image, as a modification, in addition to the components shown in FIG. 2, other components can be added. . For example, a protective film or a cover member may be attached to the front side of the polarizing plate PL1 as a protective layer for protecting the polarizing plate PL1 from scratches, dirt and the like. For example, it can apply to the embodiment which sticks optical elements, such as a phase difference plate, to polarizing plate PL1 and polarizing plate PL2. Alternatively, a method of forming an optical element on each of the substrate FS and the substrate BS can be applied.

  Further, as shown in FIG. 3, the display device LCD 1 has a plurality of pixel electrodes PE disposed between the substrate FS and the substrate BS, and a common electrode CE. Since the display device LCD1 of the present embodiment is a display device of the transverse electric field mode as described above, the plurality of pixel electrodes PE and the common electrode CE are respectively formed on the substrate BS.

  The substrate BS shown in FIG. 3 has a base material BSg made of a glass substrate or the like, and a circuit mainly for image display is formed on the base material BSg. The substrate BS has a front surface BSf located on the substrate FS side and a back surface BSb (see FIG. 2) located on the opposite side. Further, on the front surface BSf side of the substrate BS, a display element such as a TFT and a plurality of pixel electrodes PE are formed in a matrix.

  Since the example shown in FIG. 3 shows the display device LCD1 in the lateral electric field mode (specifically, the FFS mode), the common electrode CE is formed on the front side of the base material BSg provided in the substrate BS, and the insulating film (insulating layer ) Covered by OC2. Further, the plurality of pixel electrodes PE are formed on the substrate FS side of the insulating film OC2 so as to face the common electrode CE via the insulating film OC2.

  A substrate FS shown in FIG. 3 is a substrate on which a color filter CF for forming a color display image is formed on a base material FSg made of a glass substrate or the like, and is a front surface FSf on the display surface side (see FIG. 2). And a back surface FSb opposite to the front surface FSf. Like the substrate FS, the substrate on which the color filter CF is formed is opposed to the TFT substrate on which the above-described TFT is formed because the substrate is opposed to the color filter substrate or the TFT substrate through the liquid crystal layer. It is called a substrate. As a modification of FIG. 3, a configuration in which the color filter CF is provided on the TFT substrate may be adopted.

  For example, the substrate FS periodically arranges color filter pixels CFr, CFg, and CFb of three colors of red (R), green (G), and blue (B) on one surface of a base material FSg such as a glass substrate. A color filter CF configured as described above is formed. In a color display device, one pixel (also referred to as one pixel) is configured, for example, by combining the three color sub-pixels of red (R), green (G) and blue (B). The plurality of color filter pixels CFr, CFg, CFb of the substrate FS are disposed at positions facing each other with the respective sub-pixels having the pixel electrode PE formed on the substrate BS.

  In addition, a light shielding film BM is formed at each boundary of the color filter pixels CFr, CFg, and CFb of each color. The light shielding film BM is called a black matrix, and is made of, for example, a black resin or a low reflective metal. The light shielding film BM is formed in a lattice shape in plan view. In other words, the substrate FS has the color filter pixels CFr, CFg, and CFb of the respective colors formed in the openings of the light shielding film BM formed in a lattice. In addition, what constitutes one pixel is not limited to three colors of red (R), green (G) and blue (B). In addition, the black matrix is not limited to a lattice, and may be a stripe.

  In the present application, the area described as the display part DP or the display area is defined as an area inside the frame part FL. In addition, the frame portion FL is a region covered with a light shielding film BM that shields the light emitted from the light source LS illustrated in FIG. Although the light shielding film BM is also formed in the display part DP, in the display part DP, a plurality of openings are formed in the light shielding film BM. Generally, among the openings formed in the light shielding film BM and in which the color filter CF is embedded, the end of the opening formed closest to the peripheral edge is defined as the boundary between the display part DP and the frame part FL. Ru.

  Further, the substrate FS has a resin layer OC1 covering the color filter CF. Since the light shielding film BM is formed at the boundary between the color filter pixels CFr, CFg, and CFb of the respective colors, the inner surface of the color filter CF is an uneven surface. The resin layer OC1 functions as a planarizing film that planarizes the unevenness of the inner surface of the color filter CF. Alternatively, the resin layer OC1 functions as a protective film that prevents impurities from being diffused from the color filter CF to the liquid crystal layer. The resin layer OC1 can cure the resin material by including a component that is cured by applying energy, such as a thermosetting resin component or a photocurable resin component, to the material.

  In addition, a liquid crystal layer LCL for forming a display image is provided between the substrate FS and the substrate BS by applying a display voltage between the pixel electrode PE and the common electrode CE. The liquid crystal layer LCL modulates the light passing therethrough according to the state of the applied electric field.

  Further, the substrate FS has an alignment film AF1 covering the resin layer OC1 on the back surface FSb which is an interface in contact with the liquid crystal layer LCL. Further, the substrate BS has an alignment film AF2 covering the insulating film OC2 and the plurality of pixel electrodes PE on the front surface BSf which is an interface in contact with the liquid crystal layer LCL. The alignment films AF1 and AF2 are resin films formed to align the initial alignment of the liquid crystal contained in the liquid crystal layer LCL, and are made of, for example, polyimide resin.

  A method of displaying a color image by the display device LCD1 shown in FIG. 3 is, for example, as follows. That is, the light emitted from the light source LS (see FIG. 2) is filtered by the polarizing plate PL2 (see FIG. 2), and the light passing through the polarizing plate PL2 enters the liquid crystal layer LCL. The light incident on the liquid crystal layer LCL changes its polarization state according to the refractive index anisotropy (in other words, birefringence) of the liquid crystal, and the thickness direction of the liquid crystal layer LCL (in other words, the direction from the substrate BS to the substrate FS) , And emitted from the substrate FS. At this time, the liquid crystal alignment is controlled by an electric field formed by applying a voltage to the pixel electrode PE and the common electrode CE, and the liquid crystal layer LCL functions as an optical shutter. That is, in the liquid crystal layer LCL, the light transmittance can be controlled for each sub-pixel. The light that has reached the substrate FS is subjected to color filtering processing (that is, processing to absorb light other than a predetermined wavelength) in a color filter formed on the substrate FS, and emitted from the front surface FSf. In addition, light emitted from the front surface FSf reaches the viewer VW via the polarizing plate PL1.

  Further, as shown in FIG. 4, the seal portion SL provided on the peripheral edge side of the liquid crystal layer LCL includes a seal material (sealing material) SLp. The liquid crystal layer LCL is enclosed in a region surrounded by the sealing material SLp. That is, the sealing material SLp has a function as a sealing material for preventing the liquid crystal layer LCL from leaking. The sealing material SLp is in close contact with the back surface FSb of the substrate FS and the front surface BSf of the substrate BS, and the substrate FS and the substrate BS are bonded and fixed via the sealing material SLp. That is, the sealing material SLp has a function as an adhesive member for adhesively fixing the substrate FS and the substrate BS.

  In the example shown in FIG. 4, the seal portion SL includes a member PS which is a member disposed around the liquid crystal layer LCL and extending along the outer edge of the liquid crystal layer LCL. The member PS functions as a damming member for blocking the spread of the alignment film AF1. The thickness of the liquid crystal layer LCL shown in FIGS. 3 and 4 is extremely thin compared to the thickness of the substrate FS or the substrate BS. For example, the thickness of the liquid crystal layer LCL is about 0.1% to 10% as compared to the thicknesses of the substrate FS and the substrate BS. In the example shown in FIGS. 3 and 4, the thickness of the liquid crystal layer LCL is, for example, about 3 μm to 4 μm.

<Details of the lead wiring section>
Next, the details of the lead-out wiring portion LD shown in FIG. 1 will be described. FIG. 5 is an enlarged plan view schematically showing the layout of the lead-out wiring portion shown in FIG. FIG. 6 is an enlarged plan view showing a layout example in the case where a plurality of wirings are drawn by two wiring layers in the lead wiring portion shown in FIG. 7 is an examination example corresponding to FIG. 6, and is an enlarged plan view showing a layout example in the case where a plurality of wires are drawn by a single layer wiring layer. FIG. 8 is an enlarged plan view showing another example of study corresponding to FIG. 6, in which a plurality of wires are routed by two wiring layers. FIG. 9 is an enlarged cross-sectional view taken along the line A-A of FIG. 10 is an enlarged cross-sectional view taken along the line AA of FIG. FIG. 11 is an enlarged cross-sectional view showing a structural example of the display element provided in the display element portion shown in FIG.

  In FIGS. 6 and 8, in order to make it easy to distinguish between the wire WL1 and the wire WL2 formed in different layers, the wire WL1 formed in the first layer is shown by a solid line and formed in the second layer. The wire WL2 is shown by a dotted line.

  In the lead-out wiring portion LD shown in FIG. 1, a plurality of wiring lines WL including a plurality of signal lines transmitting a video signal to the display element portion DPQ and a plurality of gate lines transmitting a gate signal to the display element portion DPQ are formed. ing. In order to increase the number of pixels of the display device and improve the definition of the display image, it is necessary to increase the number of signal lines and gate lines, so a large number of wirings WL are provided in a limited space. Technology is required. Therefore, the inventor of the present application has studied on a technique of increasing the number of the wirings WL by forming the plurality of wirings WL in a plurality of stacked wiring layers.

  First, as shown in FIG. 5, the length PL1 of the input section IPC in the X direction is different from the length PL2 of the display element section DPQ. Therefore, a part of the wiring WL (see FIG. 6) electrically connecting the input portion IPC and the display element portion DPQ is in a direction intersecting with each of the X direction and the Y direction orthogonal to the X direction. I need to extend it. For this reason, the lead-out wiring portion LD includes a portion LD1 in which the plurality of wirings WL extend along the Y direction between the display element portion DPQ and the input portion IPC. Further, the lead-out wiring portion LD includes a portion LD2 extending along the direction in which the plurality of wires WL intersect the Y direction and the X direction, between the portion LD1 and the input portion IPC. The lead-out wiring portion LD also has a portion LD3 in which a plurality of wires WL extend along the Y direction between the portion LD2 and the input portion IPC.

  As in the present embodiment, in the portion LD2 in which the plurality of wires WL extend along the direction crossing the Y direction and the X direction, the length of the chip is reduced to reduce the cost of the chip. When the length PL1 decreases, or when the distance between the side BSs1 of the substrate BS and the display portion DP in the frame portion FL is narrowed for narrowing the frame, the distance between the adjacent wires WL is narrow in the portion LD2. Become. In other words, it is necessary to improve the wiring density in the portion LD2.

  Next, as in the display device LCD2 shown in FIG. 7, the case of drawing the wiring WL in a single layer will be examined. When a plurality of wires WL are routed in a single layer as in the display device LCD2, the number of wires WL that can be laid out is defined by the minimum value of the separation distance between the adjacent wires WL. For example, in the case of drawing a plurality of wirings WL in a wiring layer of a design rule in which the wiring width of each of the plurality of wirings WL1 shown in FIG. 7 is 4.2 μm and the separation distance between adjacent wirings WL1 is 5.1 μm. The distance between the centers of the adjacent wires WL1 in the LD 2 must be 9.3 μm or more. In other words, in the case of the layout shown in FIG. 7, the wiring WL1 needs to be disposed at a wiring pitch of 9.3 μm or more in the partial LD2.

  Next, as in the display device LCD3 shown in FIG. 8 and FIG. 9, the case where the wiring WL is routed in the two wiring layers sandwiching the insulating film will be examined. For example, one wiring layer sandwiching the insulating film is the same layer as the gate electrode of the TFT, and the other wiring layer is the same layer as the source / drain electrode of the TFT. When the wiring WL is routed in two wiring layers, as shown in FIGS. 8 and 9, the wiring WL1 provided in the first wiring layer L1 (see FIG. 9) and the second wiring layer The wiring WL2 provided in L2 (see FIG. 9) is preferably provided so as not to overlap with each other. By providing the wiring WL1 and the wiring WL2 so as not to overlap with each other, interference between the current flowing through the wiring WL1 and the current flowing through the wiring WL2 can be suppressed.

  Therefore, in the example of the display device LCD3, as shown in FIG. 8, the wires WL1 and the wires WL2 are alternately arranged in a plan view. In this case, among the plurality of wirings WL1 formed in the first wiring layer L1 (see FIG. 9), the space between the adjacent wirings WL1 can be utilized as a formation region of the wiring WL2, so the first layer The wiring density can be improved as compared with the case where the wiring WL is routed only by the wiring layer L1. Each of the wirings may be a single layer metal or a stack of a plurality of metals.

  For example, in the example shown in FIG. 9, in the wiring layer L1, the wiring width W1 of each of the plurality of wirings WL1 is 4.2 μm, and the distance between adjacent wirings WL1 is 5.1 μm. In the wiring layer L2, the wiring width W2 of each of the plurality of wirings WL2 is 1.8 μm, and the separation distance between the adjacent wirings WL2 is 7.5 μm. In this case, among the plurality of wirings WL shown in FIG. 8, the distance between the centers of the adjacent wirings WL in plan view is about 4.7 μm. In other words, in the case of the layout shown in FIG. 8, the wiring pitch can be improved as compared to the case of the display device LCD 2 shown in FIG. .

  When the wirings WL are formed in a plurality of wiring layers as in the display device LCD3, the design rule of the wiring width and the distance between the wiring layers for each wiring layer, ie, the wiring width and The lower limit of the inter-wire distance may be different. For example, it has been described that TFTs are formed as a plurality of display elements in the display element portion DPQ shown in FIG. From the viewpoint of efficiently forming the plurality of wiring layers of the lead-out wiring portion LD shown in FIGS. 8 and 9, it is preferable to collectively form the gate electrode and the source electrode of the TFT. In this case, design rules for the wire width and the distance between wires may differ depending on the wiring layer due to the manufacturing process of the TFT.

  For example, when the TFT as the display element described above has a bottom gate structure in which the gate electrode GT is formed below the source electrode ST and the drain electrode DT as in the transistor Q1 shown in FIG. The gate electrode GT is formed in the wiring layer L1 (see FIG. 1). Further, the source electrode ST and the drain electrode DT are formed in the second wiring layer L2. In the example shown in FIG. 11, the gate electrode GT is formed in the first wiring layer L1, and is covered with the insulating film (insulating layer) IL1 which is a gate insulating film. The insulating film IL1 is, for example, an inorganic insulating film formed of silicon oxide, silicon nitride, or a laminated film of these. The source electrode ST and the drain electrode DT are formed in the second wiring layer L2 provided on the insulating film IL1, and covered with the insulating film (insulating layer) IL2. The insulating film IL2 is an insulating film which functions as a protective film of the transistor Q1 and the wiring layer L2. Since the insulating film IL2 covers the transistor Q1, the insulating film IL2 is formed of an organic film having a better coverage than the inorganic film, and is further covered by an insulating film (insulating layer) IL3 formed of an inorganic insulating film such as silicon nitride.

  In the manufacturing process of the transistor Q1 shown in FIG. 11, after the gate electrode GT is formed, the semiconductor layer SCL is formed over the insulating film IL1 which is a gate insulating film covering the gate electrode GT. Although the transistor in FIG. 11 is a bottom gate, a top gate transistor in which a semiconductor layer is formed on the side close to the base BSg, a semiconductor layer is formed, a gate insulating film is formed, and a gate electrode is provided over the gate insulating film Exists. At the time of formation of a transistor, heat treatment may be performed, and resistance to heat treatment is often required for the wiring WL1 (see FIGS. 8 and 9) formed in the wiring layer L1 in which the gate electrode GT is formed. Therefore, the wiring layer L1 may be formed of, for example, a high melting point metal material such as molybdenum (Mo). On the other hand, since the source electrode ST and the drain electrode DT can be formed after heat treatment, a low resistance metal material such as aluminum is used for the wiring WL1 (see FIGS. 8 and 9) formed in the wiring layer L2. Can be used. As a result, the wiring WL2 of the wiring layer L2 can have a narrower wiring width than the wiring WL1 of the wiring layer L1.

  Note that the example in which different metal materials are used for the wiring WL1 and the wiring WL2 described above is an example of the reason why the design rule of the wiring width and the distance between the wirings is different for each wiring layer. In some cases, aluminum is used. However, even if the same metal material is used for the wiring WL1 and the wiring WL2, the design rule of the wiring thickness, the wiring width, and the distance between the wirings is set for each wiring layer due to process restrictions or step coverage. It may be different.

  In the example shown in FIG. 9, the wiring WL2 is an aluminum wiring, and as a design rule, the distance between the wirings may be, for example, 2.5 μm or more. Therefore, if all the wirings WL are arranged in the second wiring layer L2 shown in FIG. 9, the distance between the centers of the adjacent wirings WL2, that is, the wiring pitch is about 4.3 μm. That is, in the case of the example shown in FIG. 9, since the wires WL1 and the wires WL2 are alternately arranged in plan view, compared to the case where all the wires WL are provided in the second wiring layer L2, Wiring density is low. As described above, in the case where the wiring WL1 and the wiring WL2 are simply alternately arranged in the case where the design rule of the wiring width and the wiring distance is different for each wiring layer, a single layer of the second wiring layer L2 is used. It has been found that the wiring density may be lower than in the case where the wiring WL is routed.

  Therefore, the inventors of the present application further study a configuration capable of increasing the wiring density when arranging the wirings WL in each of the plurality of wiring layers, and the configuration of the present embodiment shown in FIG. 6 and FIG. I found it. That is, in the display device LCD1, the number of the wirings WL2 formed in the wiring layer L2 that can relatively easily improve the wiring density is higher than the number of the wirings WL1 that is relatively formed in the wiring layer L1. There are also many.

  As shown in FIGS. 6 and 10, the lead-out wiring portion LD (see FIG. 6) included in the display device of the present embodiment includes a plurality of wiring layers L1 (see FIG. 10) and wiring layers L2 (see FIG. 10). The wiring layer of Further, in the wiring layer L1, a plurality of wirings WL1 having a wiring width W1 are formed, and in the wiring layer L2, a plurality of wirings WL2 having a wiring width W2 smaller than the wiring width W1 are formed. That is, the wiring layer L2 is a wiring layer that can easily improve the wiring density relatively compared to the wiring layer L1. As described above, the point that the plurality of wirings WL1 and the plurality of wirings WL2 having different wiring widths are formed in the plurality of wiring layers is the same as the display device LCD3 illustrated in FIG. 8 and FIG.

  Further, in the case of the display device LCD3 shown in FIGS. 8 and 9, since the wirings WL1 and the wirings WL2 are alternately arranged, the number of the wirings WL1 and the number of the wirings WL2 are the same. On the other hand, in the case of the display device LCD1 shown in FIGS. 6 and 10, a plurality of (two in FIG. 6) wires WL2 are formed between the adjacent wires WL1 in plan view. Therefore, the number of the plurality of wirings WL2 formed in the wiring layer L2 shown in FIG. 10 is larger than the number of the plurality of wirings WL1 formed in the wiring layer L1. That is, in the display device LCD1 according to the present embodiment, the number of the wirings WL2 formed in the wiring layer L2 relatively easy to improve the wiring density is formed relatively in the wiring layer L1 relatively difficult to improve the wiring density Since the number is larger than the number of the wirings WL1, the wiring density of the plurality of wirings WL can be improved.

  In the example shown in FIG. 10, the wiring width W2 of the wiring WL2 is 1.8 μm, and the distance between the wiring layers L2 may be, for example, 2.5 μm or more. On the other hand, the wiring width W1 of the wiring WL1 may be 4.2 μm, and the distance between the wirings in the wiring layer L1 may be 5.1 μm or more, for example. However, in the example shown in FIG. 10, in order to arrange two wires WL2 between the adjacent wires WL1 in plan view, the distance between the wires of the wire layer L1 is 7.0 μm. In this case, since three wires WL are arranged in a range of 11.2 μm in plan view, the distance between centers of adjacent wires WL, that is, the wire pitch is about 3.7 μm. Therefore, compared with either of the case where the wiring WL is drawn in a single layer of the display device LCD2 shown in FIG. 7, the display device LCD3 shown in FIG. 8 or the second wiring layer L2 shown in FIG. Density can be improved.

  Further, in the above description, the width of the wiring WL is used as an index indicating the ease of improvement of the wiring density. However, as an index indicating the ease of improvement of the wiring density, it can be expressed using the distance between the adjacent wires WL1 in the wiring layer L1 and the distance between the adjacent wires WL2 in the wiring layer L2.

  That is, in the wiring layer L1 shown in FIG. 10, the plurality of wirings WL1 are formed at the separation distance S1. Further, in the wiring layer L2, a plurality of wires WL2 are formed at a separation distance S2 smaller than the separation distance S1. In the example shown in FIG. 10, although the separation distance S2 and the separation distance S4 are included in the separation distances of the plurality of wirings WL2, both the separation distance S2 and the separation distance S4 are smaller than the separation distance S1. As described above, when the separation distance between the adjacent wirings WL is different for each wiring layer, the wiring density can be easily improved in the wiring layer having a small separation distance. That is, in the example shown in FIG. 10, the wiring layer L2 is easier to improve the wiring density than the wiring layer L1.

  Further, as described above, in a portion of the lead-out wiring portion LD shown in FIG. 5, in particular, in a portion where the wiring density needs to be improved, a direction in which the plurality of wirings WL (see FIG. 6) cross in the X direction Is a portion LD2 extending to For example, as shown in FIG. 6, in the portions LD1 and LD3 in which the plurality of wires WL extend along the Y direction, the wire density is lower than in the portion LD2. Therefore, in the portion connected to the input unit IPC, each of the plurality of wirings WL can be collectively provided, for example, in the first wiring layer L1.

  A method of electrically connecting the first wiring layer L1 and the second wiring layer L2 is, for example, as illustrated in FIG. FIG. 12 is an enlarged cross-sectional view showing a structural example for electrically connecting the wiring of the first wiring layer and the wiring of the second wiring layer shown in FIGS. 6 and 10.

  In the example shown in FIG. 12, an opening OP1 is formed in the insulating film IL1 covering the first wiring layer L1, and in the opening OP1, the wiring WL1 is exposed from the insulating film IL1. Further, a part of the wiring WL2 formed in the second wiring layer L2 is embedded in the opening OP1 formed in the insulating film IL1, and is electrically connected to the wiring WL1. Thus, by forming the opening OP1 in a part of the insulating film IL1 covering the wiring layer L1, the wiring WL2 of the second wiring layer L2 and the wiring WL1 of the first wiring layer L1 are formed. It can be connected electrically. Although FIG. 12 shows an example in which the plurality of wiring layers are integrated into the first wiring layer L1, as a modification, for example, the plurality of wiring layers can be integrated into the second wiring layer L2.

  Further, as shown in FIG. 12, it is preferable that an opening OP1 electrically connecting the wiring WL1 and the wiring WL2 formed in different wiring layers is formed in the portion LD3 shown in FIG. The wiring density can be improved in the portion LD2 by distributing the wiring path to the plurality of wiring layers in the portion LD3 closest to the input portion IPC among the portion LD1, the portion LD2, and the portion LD3.

<Modification>
Next, representative modifications of the above-described embodiment will be exemplarily described.

<Modification 1>
In FIG. 6 and FIG. 10, as an example of the embodiment in which the wiring is formed in each of the plurality of wiring layers, a structural example in the case where the plurality of wirings WL are drawn by the two wiring layers is described. In the first modification, an example of a structure in which a plurality of wirings WL are routed by three wiring layers will be described. FIG. 13 is an enlarged plan view showing a layout example in the case where a plurality of wirings are drawn by three wiring layers, which is a modification of FIG. FIG. 14 is an enlarged cross-sectional view taken along the line AA of FIG. Note that in FIG. 13, in order to easily distinguish the wirings WL1, WL2, and WL3 formed in different layers, the wirings WL1 formed in the first layer are indicated by solid lines, and the second layer is formed. The formed wiring WL2 is indicated by a dotted line, and the wiring WL3 formed in the third layer is indicated by an alternate long and short dash line.

  The display device LCD4 shown in FIGS. 13 and 14 is different from the display device LCD1 shown in FIG. 6 in that the display device LCD4 has the wiring WL3 formed in the third wiring layer L3. The third wiring layer L3 is formed on the insulating film IL2 covering the wiring layer L2, and is covered with the insulating film IL3 which is an inorganic insulating film. Further, in the example shown in FIG. 14, the wiring width W3 of the wiring WL3 is wider than the wiring width W2 of the wiring WL2 of the second wiring layer L2. That is, in the display device LCD 4 of the first modification, the design rule differs for each wiring layer. Specifically, the wiring layer L2 can most easily improve the wiring density relatively, and the wiring layer L1 and the wiring layer L3 can hardly improve the wiring density more than the wiring layer L2.

  Even in the case where the plurality of wirings WL are routed by using three wiring layers having different wiring layout design rules as in the first modification, it can be considered in the same manner as the display device LCD 1 described above. That is, in the display device LCD3, the number of the wirings WL2 formed in the wiring layer L2 which can relatively easily improve the wiring density is the number of the wirings WL1 formed in the wiring layer L1 which relatively hardly improves the wiring density, And the number of wirings WL3 formed in the wiring layer L3. Thereby, the wiring density of the plurality of wirings WL can be improved.

  In the example shown in FIG. 14, the wiring width W1 of the wiring WL1 may be 4.2 μm, and the separation distance S1 of the wiring WL1 of the wiring layer L1 may be 5.1 μm or more, for example. The wiring width W2 of the wiring WL2 may be 1.8 μm, and the separation distance S2 of the wiring WL2 of the wiring layer L2 may be, for example, 2.5 μm or more. The wiring width W3 of the wiring WL3 may be 4.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 may be 5.1 μm or more, for example.

  However, in the example illustrated in FIG. 14, in order to prevent adjacent wires WL from overlapping each other in plan view, the separation distance S1 of the wires WL1 in the wiring layer L1 is 9.7 μm, and the wires in the wiring layer L2 are The separation distance S2 of the WL2 is 5.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 is 9.7 μm.

  In this case, since four wires WL are arranged in a range of 13.9 μm in plan view, the distance between centers of adjacent wires WL, that is, the wire pitch is about 3.5 μm. Therefore, the wiring density can be further improved compared to the display device LCD1 shown in FIG.

  Further, in the above description, the width of the wiring WL is used as an index indicating the ease of improvement of the wiring density. However, as an index indicating the ease of improvement of the wiring density, it can be expressed using the distance between the adjacent wires WL1 in the wiring layer L1 and the distance between the adjacent wires WL2 in the wiring layer L2.

  That is, among the plurality of interconnections WL2 formed in interconnection layer L2, the separation distance S2 between adjacent interconnections WL2 is greater than the separation distance S1 of interconnection WL1 in interconnection layer L1 and the separation S3 of interconnection WL3 in interconnection layer L3. small. Therefore, the wiring layer L2 can relatively easily improve the wiring density relatively, and the wiring layer L1 and the wiring layer L3 can hardly improve the wiring density more than the wiring layer L2.

  The display device LCD4 shown in FIGS. 13 and 14 is the same as the display device LCD1 shown in FIGS. 6 and 10, except for the differences described above. Therefore, duplicate explanations are omitted.

<Modification 2>
Next, in the display device LCD1 shown in FIG. 6, the display device LCD2 shown in FIG. 7, the display device LCD3 shown in FIG. 8, and the display device LCD 4 shown in FIG. Embodiments have been described which do not overlap. However, focusing on the point of improving the wiring density, the wiring density can be improved by partially overlapping the wirings WL formed in different wiring layers in the thickness direction. On the other hand, when part of the wirings WL formed in different wiring layers overlap in the thickness direction, the signal lines interfere with each other to generate noise, or the parasitic capacitance between the wirings affects the signal, or insulation There is a concern that a defect in the film may cause a short circuit between wires. Therefore, in the second modification, a technology for reducing the influence of noise in a part where the wirings WL formed in different wiring layers overlap in the thickness direction and in the overlapping part will be described.

  FIG. 15 is an enlarged plan view showing a layout example in the case where a part of a plurality of wires overlap in the thickness direction, which is a modification of FIG. FIG. 16 is an enlarged cross-sectional view along the line AA of FIG.

  The display device LCD5 shown in FIGS. 15 and 16 has a point that the wiring WL3 formed in the third wiring layer L3 and the wiring WL formed in the first wiring layer L1 overlap with each other. , And is different from the display device LCD 4 shown in FIG.

  Further, as shown in FIG. 16, the thickness TH2 of the insulating film IL2 covering the wiring layer L2 is thicker than the thickness TH1 of the insulating film IL1 covering the wiring layer L1. Since the insulating film IL1 doubles as the gate insulating film of the transistor Q1 shown in FIG. 11, if the thickness TH1 is extremely large, it becomes difficult to drive the transistor Q1. On the other hand, the insulating film IL2 tends to be thick from the viewpoint of reliably covering the source electrode ST and the drain electrode DT. In the example shown in FIG. 16, the thickness of the insulating film IL1 is smaller than 1 μm, and the thickness of the insulating film IL2 is, for example, about 2 μm.

  Here, when noise and the like between the wiring layers are taken into consideration, the influence can be reduced as the distance between the wiring layers increases. Therefore, the mutual influence between the wirings WL tends to be large between the wiring layer L1 and the wiring layer L2 provided via the relatively thin insulating film IL1. On the other hand, mutual influence between the wirings WL can be easily reduced between the wiring layer L2 and the wiring layer L3 which are formed of an organic insulating film or the like and are provided via the relatively thick insulating film IL2.

  From the above, the following configuration is preferable in consideration of noise influence between wiring layers and improvement of wiring density. That is, it is preferable that the plurality of wirings WL1 of the wiring layer L1 relatively influenced by noise and the plurality of wirings WL2 of the wiring layer L2 do not overlap with each other. In this case, the plurality of wirings WL3 provided over the insulating film IL2 whose thickness TH2 is thicker than the thickness TH1 may overlap with part of the plurality of wirings WL1 and the plurality of WL1.

  In the example shown in FIG. 16, although the wiring WL3 and the wiring WL2 do not overlap, the thickness TH2 of the insulating film IL2 is sufficiently thick, the influence of noise and parasitic capacitance is low, and there is a possibility of shorting between the wirings In the case of the low level, the wiring WL3 and the wiring WL2 may overlap.

  Further, as in the example shown in FIG. 16, when the wiring WL3 and the wiring WL2 do not overlap, the distance between the wiring WL1 and the wiring WL3 overlapping with each other is the total value of the thickness TH1 and the thickness TH2 in particular. Noise effects can be reduced.

  When the wirings WL formed in the plurality of wiring layers are provided so as to partially overlap with each other as in the display device LCD5 of the second modification, a plurality of wirings are further provided than in the display device LCD4 shown in FIG. The wiring density of WL can be improved.

  In the example illustrated in FIG. 16, the wiring width W1 of the wiring WL1 may be 4.2 μm, and the separation distance S1 of the wiring WL1 of the wiring layer L1 may be 5.1 μm or more, for example. The wiring width W2 of the wiring WL2 may be 1.8 μm, and the separation distance S2 of the wiring WL2 of the wiring layer L2 may be, for example, 2.5 μm or more. The wiring width W3 of the wiring WL3 may be 4.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 may be 5.1 μm or more, for example.

  However, in the example illustrated in FIG. 16, in order to prevent the plurality of wirings WL2 and the plurality of wirings WL1 from overlapping each other in plan view, the separation distance S1 of the wirings WL1 of the wiring layer L1 is 7.0 μm, The separation distance S2 of the wiring WL2 of the wiring layer L2 is 2.5 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 is 7.0 μm.

  In this case, since four wires WL are arranged in a range of 9.2 μm in plan view, the distance between centers of adjacent wires WL, that is, the wire pitch is about 2.3 μm. Therefore, the wiring density can be further improved compared to the display device LCD 4 shown in FIG.

  Except for the difference described above, the display device LCD5 shown in FIGS. 15 and 16 is the same as the display device LCD4 shown in FIGS. 13 and 14. Therefore, duplicate explanations are omitted.

<Modification 3>
In the case where the wiring WL3 is formed on the insulating film IL2 as in the display device LCD4 described in the first modification and the display device LCD5 described in the second modification, in the region where the wiring WL3 is formed. , And the insulating film IL2 needs to be formed.

  Here, the interface between the insulating film IL2 which is an organic insulating film and the insulating film IL1 which is an inorganic insulating film is characterized in that moisture easily infiltrates from the outside of the display device. For this reason, it is preferable to form a slit SLT by removing a part of the insulating film IL2 as shown in FIG. 17 from the viewpoint of preventing moisture from infiltrating to the display part DP (see FIG. 1). FIG. 17 is an enlarged cross-sectional view showing a structural example of a portion for electrically connecting the wirings of a plurality of wiring layers in the display shown in FIGS. 13 and 15. The slit SLT shown in FIG. 17 is a groove formed to extend along the X direction shown in FIG. 1, and the insulating film IL1 as a base layer is exposed at the opening of the slit SLT.

  As shown in FIG. 17, in order to form the slits SLT, it is necessary to electrically connect the wiring WL3 of the third wiring layer L3 and the wiring WL2 of the wiring layer L2 in a region avoiding the slits. .

  On the other hand, as described above, in the lead-out wiring portion LD shown in FIG. 5, the portion where the wiring density needs to be particularly improved is the portion LD2. Therefore, as shown in FIG. 17, it is preferable that the location where the slit SLT is formed is the portion LD3 of the lead-out wiring portion LD. Further, it is preferable that the wiring WL3 of the third wiring layer L3 and the wiring WL2 of the wiring layer L2 be connected by the partial LD3.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment and a typical modification, for example, the above-mentioned various modifications can be combined and applied. The wiring layer L3 can also be used as a metal for lowering the resistance of the common electrode in the case of a display device of the lateral electric field type. When the wiring layer L3 is formed of a low resistance metal such as aluminum, the wiring layer L3 can be formed with a wiring width and a wiring interval similar to those of the wiring WL2. Alternatively, depending on the film thickness of the wiring layer L3, the wiring width can be made slightly wider than the wiring WL2. Even in such a case, the present invention can be applied.

  Further, depending on the characteristics of the insulating film L1, the wiring WL1 and the wiring WL2 can be partially overlapped. Similarly, in the case where the insulating film L2 is formed using an inorganic film, the wiring WL2 and the wiring WL3 can also be overlapped. Thereby, further densification can be realized.

  Further, in the top gate thin film transistor, a light shielding metal for shielding light of the backlight may be used between the backlight and the semiconductor layer. It is also possible to use this light shielding metal instead of the wiring layer WL3. Moreover, it is also possible to use the said light shielding metal as a 4th wiring layer. Note that although the wiring layer described above is assumed to be a wiring connected to the source electrode or the drain electrode of the transistor in the display region, a wiring connected to the gate of a thin film transistor, a wiring for supplying a clock, a power supply, and the like Alternatively, the present invention can be applied to a wiring or the like for supplying a signal to a semiconductor chip. Further, for example, in the above-described embodiment, although the display device using the liquid crystal layer as the display functional layer is disclosed, the present invention is not limited to this. For example, the above-described technique can be applied to a lead wiring portion of a so-called organic EL type display device using a light emitting element formed of an organic compound as a display functional layer.

  It will be understood by those skilled in the art that various changes and modifications can be made within the scope of the concept of the present invention, and such changes and modifications are also considered to fall within the scope of the present invention. For example, a person skilled in the art appropriately adds, deletes or changes the design of the component or adds or omits a process or changes conditions to the above-described embodiments. As long as it is included in the scope of the present invention.

  The present invention is applicable to a display device and an electronic device in which the display device is incorporated.

AF1, AF2 Alignment film BM Light shielding film BS, FS substrate BSb, FSb Back surface BSf, FSf Front surface BSg, FSg Base materials BSs1, BSs2, BSs3, BSs4 Side CC circuit portion CE common electrode CF color filter CFr, CFg, CFb color filter pixel CHP semiconductor chip CNT1 control circuit DP display section DPQ display element section DR1 drive circuit DT drain electrode FL frame section GT gate electrode IL1, IL2, IL3 insulating film IPC input section L1, L2, L3 wiring layer LCD1, LCD2, LCD3, LCD4, LCD 5 display LCL liquid crystal layer LD lead wiring LD1, LD2, LD3 partial LS light source OC1, OC2 resin layer OP1 opening PE pixel electrode PL1, PL2 polarizer PS member Q1 transistor S1, S2, S3, S4 distance distance SCL semiconductor layer L seal portion SLp sealant (sealing material)
SLT Slit ST Source electrode VW Viewer W1, W2, W3 Wiring width WL, WL1, WL2, WL3 Wiring

Claims (1)

A substrate having a first surface, and a display function layer,
The first surface includes a display element unit in which a plurality of display elements for driving the display functional layer are arranged, an input unit to which a signal supplied to the display element unit is input, and the display element unit And a lead-out wiring portion electrically connected to the input portion;
The lead wiring portion has a plurality of wiring layers stacked via an insulating film,
In the plurality of wiring layers, a first wiring layer in which a plurality of first wirings having a first wiring width is formed, and a plurality of second wirings having a second wiring width narrower than the first wiring width are provided. And the formed second wiring layer,
The display device, wherein the number of the plurality of second wirings is larger than the number of the plurality of first wirings.

Images