JP6707156B2 - Display device - Google Patents

Description

The present invention relates to a display device, and for example, relates to a technique effectively applied to a display device having a plurality of lead wirings for transmitting signals to a plurality of display elements formed in a display area.

There is a display device in which a signal is transmitted to a plurality of display elements formed in a display region through a plurality of lead wirings to display an image.

For example, Japanese Patent Laying-Open No. 2007-164219 (Patent Document 1) describes a technique of forming a plurality of gate connection lines connected to a plurality of gate lines formed in a pixel region in a plurality of wiring layers. There is.

JP, 2007-164219, A

The display device has a display function layer such as a liquid crystal layer or a light emitting layer utilizing electroluminescence. Further, the display device has a plurality of display elements such as transistors formed in the display region. In a display device, an image is displayed by transmitting a signal to a plurality of display elements and driving the display elements.

A large number of signal lines are required to transmit signals to the plurality of display elements. The number of signal lines increases as the display image becomes higher in definition. In addition, a technology for reducing the area of a peripheral region, which is a non-display portion surrounding the display region, or a portion called a frame region is required for the display device. A lead line that is connected to the signal line and supplies a signal to the signal line is formed in the frame region. That is, in order to improve the performance of the display device, it is necessary to efficiently lay out a large number of leader lines in the frame area.

Therefore, the inventor of the present application studied a technique for improving the wiring density of the leader lines by allocating and providing a large number of leader lines to a plurality of wiring layers laminated via an insulating film, and found the following problems. It was Since the leader line is connected to the signal line in the display area and is considered to be a part of the signal line, the leader line is also referred to as a signal line below.

That is, when a plurality of signal lines are stacked, each signal line interferes with each other and may be affected by noise. In addition, if the design rule that defines the minimum value of the wiring width and the distance between wirings is different for each wiring layer due to reasons such as the manufacturing process, the wiring formed in the upper wiring layer and the wiring formed in the lower wiring layer are formed. It was found that the wiring density of the signal lines may not be sufficiently improved if the formed wirings are arranged alternately.

An object of the present invention is to provide a technique for efficiently arranging a plurality of wirings in a frame area of a display device.

A display device according to one aspect of the present invention includes a substrate having a first surface, a display function layer provided on the first surface of the substrate, and the display function layer formed on the first surface of the substrate. And a circuit section for driving
The first surface is a display element section in which a plurality of display elements for driving the display functional layer are arranged, an input section to which a signal supplied to the display element section is input, and the display element section. A lead-out wiring section electrically connecting the input section,
The lead-out wiring portion has a plurality of wiring layers stacked via an insulating film,
A first wiring layer having a plurality of first wirings having a first wiring width and a plurality of second wirings having a second wiring width narrower than the first wiring width are formed in the plurality of wiring layers. A second wiring layer formed is included,
The number of the plurality of second wirings is larger than the number of the plurality of first wirings.

Moreover, as another aspect, the first surface of the substrate may include a first side extending along a first direction, a second side located on the opposite side of the first side, and a second side orthogonal to the first direction. A third side extending along the two directions, and a fourth side opposite to the third side,
Between the first side of the substrate and the display element section, the input section and the lead wiring section are sequentially provided from the first side.
The length of the input unit in the first direction may be shorter than the length of the display element unit in the first direction.

Moreover, as another aspect, the first surface of the substrate may include a first side extending along a first direction, a second side located on the opposite side of the first side, and a second side orthogonal to the first direction. A third side extending along the two directions, and a fourth side opposite to the third side,
The lead wiring section is
A plurality of lead wirings including the plurality of first wirings and the plurality of second wirings between the display element portion and the input portion, a first portion extending along the second direction;
A second part between the first part and the input part, wherein the plurality of lead wirings extend along the second direction and a third direction intersecting the first direction;
A third portion between the second portion and the input portion, wherein the plurality of lead wirings extend in the second direction;
Have
In plan view, the plurality of first wirings and the plurality of second wirings may not overlap each other.

As another aspect, in the second portion of the lead-out wiring portion,
The plurality of first wirings are arranged at a first distance,
The plurality of second wirings may be arranged at a second separation distance smaller than the first separation distance.

Further, as another aspect, in plan view, a plurality of the plurality of second wirings may be arranged between adjacent first wirings of the plurality of first wirings.

As another aspect, each of the plurality of display elements arranged in the display element section is a transistor having a gate electrode,
The gate electrode may be formed in the same layer as the first wiring layer.

As another aspect, the plurality of first wirings and the plurality of second wirings may be formed of different kinds of metal materials.

Further, as another aspect, the plurality of wiring layers further includes a third wiring layer in which a plurality of third wirings having a third wiring width wider than the second wiring width are formed.
The number of the plurality of second wirings may be larger than the number of the plurality of third wirings.

As another aspect, a first insulating film is provided between the first wiring layer and the second wiring layer,
A second insulating film thicker than the first insulating film is provided between the second wiring layer and the third wiring layer,
In plan view, the plurality of first wirings and the plurality of second wirings do not overlap with each other, and the plurality of third wirings are among the plurality of first wirings and the plurality of second wirings. It may overlap with a part.

As another aspect, in plan view, the plurality of first wirings and the plurality of second wirings do not overlap with each other, and the plurality of second wirings and the plurality of third wirings do not overlap with each other. Alternatively, the plurality of third wirings may overlap the plurality of first wirings.

Moreover, as another aspect, the first surface of the substrate may include a first side extending along a first direction, a second side located on the opposite side of the first side, and a second side orthogonal to the first direction. A third side extending along the two directions, and a fourth side opposite to the third side,
The lead wiring section is
A plurality of lead wirings including the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings extend along the second direction between the display element portion and the input portion. 1 part,
A second part between the first part and the input part, wherein the plurality of lead wirings extend along the second direction and a third direction intersecting the first direction;
A third portion between the second portion and the input portion, wherein the plurality of lead wirings extend in the second direction;
Have
A first insulating film, which is an inorganic insulating film, is provided between the first wiring layer and the second wiring layer,
A second insulating film, which is an organic insulating film, is provided between the second wiring layer and the third wiring layer,
An opening extending along the first direction may be provided in the third portion of the lead-out wiring portion so as to penetrate the second insulating film in the thickness direction.

A display device according to another aspect is a substrate having a first surface, a display function layer formed on the first surface of the substrate, and a display function formed on the first surface of the substrate. A circuit portion for driving the layer,
The circuit section includes a display element section in which a plurality of display elements are arranged at a position overlapping with a display area in which the display function layer is formed, and an input section for transmitting a signal for driving the display function layer to the display element section. And a lead-out wiring section that electrically connects the display element section and the input section,
The lead-out wiring portion has a plurality of wiring layers stacked,
In the plurality of wiring layers, a first wiring layer in which a plurality of first wirings are formed at a first separation distance and a plurality of second wirings in a second separation distance that is smaller than the first separation distance are formed. A second wiring layer, and
The number of the plurality of second wirings is larger than the number of the plurality of first wirings.

It is a top view showing an example of a display of an embodiment. It is sectional drawing which followed the AA line of FIG. It is an expanded sectional view of the B section of FIG. It is an expanded sectional view of the C section of FIG. FIG. 2 is an enlarged plan view schematically showing the layout of the lead-out wiring section shown in FIG. 1. FIG. 3 is an enlarged plan view showing a layout example when a plurality of wirings are routed in two wiring layers in the lead-out wiring section shown in FIG. 1. FIG. 7 is an enlarged plan view showing a layout example when a plurality of wirings are laid out in a single wiring layer, which is a study example corresponding to FIG. 6. FIG. 9 is an enlarged plan view showing another layout example corresponding to FIG. 6 and showing a layout example when a plurality of wirings are routed in two wiring layers. It is an expanded sectional view which followed the AA line of FIG. It is an expanded sectional view which followed the AA line of FIG. It is an expanded sectional view which shows the constructional example of the display element provided in the display element part shown in FIG. FIG. 11 is an enlarged cross-sectional view showing a structural example for electrically connecting the wiring of the first wiring layer and the wiring of the second wiring layer shown in FIGS. 6 and 10. FIG. 11 is an enlarged plan view showing a layout example in which a plurality of wirings are routed in three wiring layers, which is a modification example of FIG. 6. It is an expanded sectional view which followed the AA line of FIG. FIG. 14 is an enlarged plan view showing a layout example when a part of the plurality of wirings overlaps with each other in the thickness direction, which is a modification example of FIG. 13. It is an expanded sectional view which followed the AA line of FIG. FIG. 16 is an enlarged cross-sectional view showing a structural example of a portion that electrically connects wirings of a plurality of wiring layers in the display device shown in FIGS. 13 and 15.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and a person having ordinary skill in the art can easily think of an appropriate modification while keeping the gist of the invention, and is naturally included in the scope of the invention. Further, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example, and the interpretation of the present invention will be understood. It is not limited. In the present specification and each drawing, the same or similar reference numerals are given to the same elements as those described in regard to the already-existing drawings, and detailed description thereof may be appropriately omitted.

Further, the techniques described in the following embodiments can be widely applied to a display device including a mechanism that supplies a signal from the periphery of the display area to a plurality of elements in the display area provided with the display function layer. Examples of the display device as described above include various display devices such as a liquid crystal display device and an organic EL (Electro-Luminescence) display device. In the following embodiments, a liquid crystal display device will be described as a typical example of the display device.

Further, the liquid crystal display device is roughly classified into the following two types depending on the direction of application of an electric field for changing the orientation of the liquid crystal molecules of the liquid crystal layer which is the display function layer. That is, as the first classification, there is a so-called longitudinal electric field mode in which an electric field is applied in the thickness direction (or the out-of-plane direction) of the display device. Examples of the vertical electric field mode include a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. Further, as a second classification, there is a so-called lateral electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. Examples of the lateral electric field mode include an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode which is one of the IPS modes. The technique described below can be applied to both the vertical electric field mode and the horizontal electric field mode, but in the embodiments described below, a horizontal electric field mode display device is taken as an example and described.

<Basic configuration of display device>
First, the basic configuration of the display device will be described. FIG. 1 is a plan view showing an example of the display device of the present embodiment, and FIG. 2 is a sectional view taken along the line AA of FIG. Further, FIG. 3 is an enlarged cross-sectional view of portion B of FIG. Further, FIG. 4 is an enlarged cross-sectional view of the C portion of FIG.

In FIG. 1, the outline of the display portion DP is shown by a two-dot chain line in order to make it easier to see the boundary between the display portion DP and the frame portion (peripheral portion) FL in a plan view. In addition, the plurality of wirings WL illustrated in FIG. 1 extend from the peripheral region of the display unit DP to a region overlapping with the display unit DP. However, in FIG. 1, the wiring WL is not shown in the region overlapping the display portion DP for ease of viewing. Further, although FIG. 2 is a sectional view, hatching is omitted for ease of viewing.

As shown in FIG. 1, the display device LCD1 of the present embodiment has a display portion DP which is a display area in which an image visually recognizable from the outside is formed according to an input signal. Further, the display device LCD1 has a frame portion FL which is a non-display area provided in a frame shape around the display portion DP in a plan view. Although the display area of the display device has a rectangular shape, the display area may be polygonal or circular. Further, the display area may extend to the vicinity of the end portion of the display device. In this case, the peripheral area of the display area does not have a frame shape, but even in this case, it is referred to as a frame portion.

Further, the display device LCD1 has a structure in which a liquid crystal layer which is a display function layer is formed between a pair of substrates which are arranged to face each other. That is, as shown in FIG. 2, the display device LCD1 includes a substrate FS on the display surface side, a substrate BS located on the opposite side of the substrate FS, and a liquid crystal layer LCL disposed between the substrate FS and the substrate BS (FIG. 3). See).

In the plan view, the substrate BS shown in FIG. 1 has a side BSs1 extending along the X direction, a side BSs2 facing the side BSs1, a side BSs3 extending along the Y direction orthogonal to the X direction, and a side BSs3. Has a side BSs4 opposite to. The distances from the sides BSs2, BSs3, and BSs4 included in the substrate BS shown in FIG. 1 to the display portion DP are substantially the same, and shorter than the distances from the side BSs1 to the display portion DP. Hereinafter, in the present application, when it is described as a peripheral portion of the substrate BS, it means any one of the side BSs1, the side BSs2, the side BSs3, and the side BSs4 that form the outer edge of the substrate BS. Further, when simply described as a peripheral portion, it means a peripheral portion of the substrate BS.

In addition, the liquid crystal layer LCL provided in the display unit DP shown in FIG. 1 is driven for each pixel (specifically, subpixel) according to a signal applied to the circuit unit CC.

The circuit section CC is connected to the display element section DPQ in which a plurality of display elements are arranged at a position overlapping the display section DP. The plurality of display elements provided in the display element portion DPQ are provided in a matrix for each pixel (specifically, subpixel) and perform a switching operation. In this embodiment, the plurality of display elements are transistors called TFTs (Thin-Film Transistors) formed on the substrate.

In addition, the circuit portion CC includes a plurality of wirings WL provided in the frame portion FL around the display portion DP and electrically connected to the plurality of display elements of the display element portion DPQ. Further, the circuit section CC that drives the display function layer is electrically connected to the display element section DPQ and inputs drive signals and video signals to a plurality of display elements of the display element section DPQ through a plurality of wirings WL. , An input unit IPC is included. In the example shown in FIG. 1, the input section IPC is equipped with a semiconductor chip CHP in which a drive circuit DR1 for image display and a control circuit CNT1 are formed.

Further, in the example shown in FIG. 1, the input unit IPC is provided between the side BSs1 of the substrate BS and the display unit DP in the frame portion FL of the display device LCD1. Further, a lead-out wiring portion LD having a plurality of wirings WL is provided between the side BSs1 of the substrate BS and the display portion DP. The display element section DPQ and the input section IPC are electrically connected to each other via the lead wiring section LD. The detailed structure of the lead-out wiring part LD will be described later.

Further, the display device LCD1 has a seal portion formed in the frame portion FL in a plan view. The seal part is formed so as to continuously surround the periphery of the display part DP, and the substrate FS and the substrate BS shown in FIG. 2 are bonded and fixed by a seal material provided in the seal part. By thus providing the seal portion around the display portion DP, the liquid crystal layer LCL (see FIG. 3) that is the display function layer can be sealed.

Further, as shown in FIG. 2, a polarizing plate PL2 that polarizes light generated from the light source LS is provided on the back surface BSb side of the substrate BS of the display device LCD1. The polarizing plate PL2 is fixed to the substrate BS. On the other hand, a polarizing plate PL1 is provided on the front surface FSf side of the substrate FS. The polarizing plate PL1 is fixed to the substrate FS.

Note that FIG. 2 exemplarily shows basic components for forming a display image, but as a modification, in addition to the components shown in FIG. 2, other components can be added. .. For example, a protective film or a cover member may be attached to the front surface side of the polarizing plate PL1 as a protective layer that protects the polarizing plate PL1 from scratches and dirt. Further, for example, it can be applied to an embodiment in which an optical element such as a retardation plate is attached to the polarizing plates PL1 and PL2. Alternatively, a method of forming an optical element on each of the substrate FS and the substrate BS can be applied.

Further, as shown in FIG. 3, the display device LCD1 has a plurality of pixel electrodes PE and a common electrode CE arranged between the substrate FS and the substrate BS. Since the display device LCD1 of the present embodiment is a display device of the horizontal electric field mode as described above, the plurality of pixel electrodes PE and the common electrode CE are respectively formed on the substrate BS.

The substrate BS shown in FIG. 3 has a base material BSg made of a glass substrate or the like, and a circuit for image display is mainly formed on the base material BSg. The substrate BS has a front surface BSf located on the substrate FS side and a back surface BSb (see FIG. 2) located on the opposite side. Further, a display element such as a TFT and a plurality of pixel electrodes PE are formed in a matrix on the front surface BSf side of the substrate BS.

Since the example shown in FIG. 3 shows the display device LCD1 in the lateral electric field mode (specifically, the FFS mode), the common electrode CE is formed on the front surface side of the base material BSg included in the substrate BS, and the insulating film (insulating layer) is formed. ) Covered with OC2. Further, the plurality of pixel electrodes PE are formed on the substrate FS side of the insulating film OC2 so as to face the common electrode CE via the insulating film OC2.

Further, the substrate FS shown in FIG. 3 is a substrate in which a color filter CF for forming an image of color display is formed on a base material FSg made of a glass substrate or the like, and a front surface FSf which is a display surface side (see FIG. 2). ) And a back surface FSb located opposite the front surface FSf. The substrate on which the color filter CF is formed, like the substrate FS, faces the color filter substrate or the TFT substrate through the liquid crystal layer when distinguished from the TFT substrate on which the above-mentioned TFT is formed. Called the substrate. In addition, as a modification of FIG. 3, a configuration in which the color filter CF is provided on the TFT substrate may be adopted.

In the substrate FS, color filter pixels CFr, CFg, and CFb of three colors of red (R), green (G), and blue (B) are periodically arranged on one surface of a base material FSg such as a glass substrate. The color filter CF configured as described above is formed. In a color display device, for example, one pixel (also referred to as one pixel) is configured by grouping sub-pixels of three colors of red (R), green (G), and blue (B) as one set. The plurality of color filter pixels CFr, CFg, CFb on the substrate FS are arranged at positions facing the respective sub-pixels having the pixel electrode PE formed on the substrate BS.

Further, a light shielding film BM is formed on each boundary of the color filter pixels CFr, CFg, CFb of each color. The light-shielding film BM is called a black matrix, and is made of, for example, a black resin or a metal having low reflectivity. The light-shielding film BM is formed in a lattice shape in plan view. In other words, the substrate FS has the color filter pixels CFr, CFg, and CFb of the respective colors formed in the openings of the light-shielding film BM formed in a grid pattern. In addition, what constitutes one pixel is not limited to three colors of red (R), green (G), and blue (B). Further, the black matrix is not limited to the grid shape, and may be the stripe shape.

In the present application, the area described as the display portion DP or the display area is defined as an area inside the frame portion FL. The frame portion FL is a region covered with a light blocking film BM that blocks the light emitted from the light source LS shown in FIG. Although the light shielding film BM is also formed in the display portion DP, the display portion DP has a plurality of openings formed in the light shielding film BM. In general, of the openings formed in the light-shielding film BM and having the color filter CF embedded therein, the end of the opening formed on the most peripheral side is defined as the boundary between the display portion DP and the frame portion FL. It

The substrate FS also has a resin layer OC1 that covers the color filter CF. Since the light-shielding film BM is formed at the boundary between the color filter pixels CFr, CFg, and CFb of each color, the inner surface of the color filter CF is uneven. The resin layer OC1 functions as a flattening film that flattens unevenness on the inner surface of the color filter CF. Alternatively, the resin layer OC1 functions as a protective film that prevents impurities from diffusing from the color filter CF into the liquid crystal layer. The resin layer OC1 can cure the resin material by adding a component such as a thermosetting resin component or a photocurable resin component that is cured by applying energy to the material.

Further, a liquid crystal layer LCL that forms a display image by applying a display voltage between the pixel electrode PE and the common electrode CE is provided between the substrate FS and the substrate BS. The liquid crystal layer LCL modulates the light passing therethrough according to the state of the applied electric field.

Further, the substrate FS has an alignment film AF1 that covers the resin layer OC1 on the back surface FSb that is an interface in contact with the liquid crystal layer LCL. Further, the substrate BS has an alignment film AF2 that covers the insulating film OC2 and the plurality of pixel electrodes PE on the front surface BSf that is an interface in contact with the liquid crystal layer LCL. The alignment films AF1 and AF2 are resin films formed to align the initial alignment of the liquid crystals included in the liquid crystal layer LCL, and are made of, for example, a polyimide resin.

A method of displaying a color image by the display device LCD1 shown in FIG. 3 is as follows, for example. That is, the light emitted from the light source LS (see FIG. 2) is filtered by the polarizing plate PL2 (see FIG. 2), and the light passing through the polarizing plate PL2 enters the liquid crystal layer LCL. The light incident on the liquid crystal layer LCL changes its polarization state according to the refractive index anisotropy of the liquid crystal (in other words, birefringence), and the thickness direction of the liquid crystal layer LCL (in other words, the direction from the substrate BS to the substrate FS). And is emitted from the substrate FS. At this time, the liquid crystal alignment is controlled by the electric field formed by applying a voltage to the pixel electrode PE and the common electrode CE, and the liquid crystal layer LCL functions as an optical shutter. That is, in the liquid crystal layer LCL, the light transmittance can be controlled for each subpixel. The light reaching the substrate FS is subjected to color filtering processing (that is, processing of absorbing light other than a predetermined wavelength) in the color filter formed on the substrate FS, and is emitted from the front surface FSf. Further, the light emitted from the front surface FSf reaches the viewer VW via the polarization plate PL1.

Further, as shown in FIG. 4, the seal portion SL provided on the peripheral side of the liquid crystal layer LCL includes a seal material (sealing material) SLp. The liquid crystal layer LCL is enclosed in a region surrounded by the seal material SLp. That is, the sealing material SLp has a function as a sealing material that prevents the liquid crystal layer LCL from leaking out. The seal material SLp is in close contact with each of the back surface FSb of the substrate FS and the front surface BSf of the substrate BS, and the substrate FS and the substrate BS are adhesively fixed via the seal material SLp. That is, the sealing material SLp has a function as an adhesive member that adheres and fixes the substrate FS and the substrate BS.

Further, in the example shown in FIG. 4, the seal portion SL has a member PS which is a member arranged around the liquid crystal layer LCL and extending along the outer edge of the liquid crystal layer LCL. The member PS functions as a damming member that dams the spread of the alignment film AF1. Further, the thickness of the liquid crystal layer LCL shown in FIGS. 3 and 4 is extremely thin as compared with the thickness of the substrate FS or the substrate BS. For example, the thickness of the liquid crystal layer LCL is about 0.1% to 10% as compared with the thickness of the substrate FS or the substrate BS. In the example shown in FIGS. 3 and 4, the thickness of the liquid crystal layer LCL is, for example, about 3 μm to 4 μm.

<Details of drawer wiring section>
Next, details of the lead wiring portion LD shown in FIG. 1 will be described. FIG. 5 is an enlarged plan view schematically showing the layout of the lead-out wiring section shown in FIG. Further, FIG. 6 is an enlarged plan view showing a layout example when a plurality of wirings are routed in two wiring layers in the lead-out wiring section shown in FIG. 7 is an examination example corresponding to FIG. 6 and is an enlarged plan view showing a layout example when a plurality of wirings are laid out in a single wiring layer. Further, FIG. 8 is another plan view corresponding to FIG. 6, and is an enlarged plan view showing a layout example when a plurality of wirings are routed in two wiring layers. Further, FIG. 9 is an enlarged cross-sectional view taken along the line AA of FIG. Further, FIG. 10 is an enlarged cross-sectional view taken along the line AA of FIG. Further, FIG. 11 is an enlarged cross-sectional view showing a structural example of the display element provided in the display element section shown in FIG.

Note that in FIGS. 6 and 8, in order to easily distinguish the wiring WL1 and the wiring WL2 which are formed in different layers, the wiring WL1 formed in the first layer is shown by a solid line and formed in the second layer. The formed wiring WL2 is shown by a dotted line.

In the lead-out wiring portion LD shown in FIG. 1, a plurality of wiring lines WL including a plurality of signal lines transmitting a video signal to the display element portion DPQ and a plurality of gate lines transmitting a gate signal to the display element portion DPQ are formed. ing. In order to increase the number of pixels of the display device and improve the definition of a display image, it is necessary to increase the number of signal lines and gate lines. Therefore, a large number of wirings WL are arranged in a limited space. Technology is required. Therefore, the inventor of the present application studied a technique for increasing the number of wirings WL by forming a plurality of wirings WL in a plurality of stacked wiring layers.

First, as shown in FIG. 5, the length PL1 of the input portion IPC and the length PL2 of the display element portion DPQ in the X direction are different. Therefore, a part of the wiring WL (see FIG. 6) that electrically connects the input unit IPC and the display element unit DPQ is arranged in a direction intersecting the X direction and the Y direction orthogonal to the X direction. Need to postpone. Therefore, the lead wiring portion LD has a portion LD1 between the display element portion DPQ and the input portion IPC, in which the plurality of wirings WL extend along the Y direction. The lead wiring portion LD has a portion LD2 extending between the portion LD1 and the input portion IPC along a direction in which the plurality of wirings WL intersect the Y direction and the X direction. Further, the lead wiring portion LD has a portion LD3 between the portion LD2 and the input portion IPC, in which a plurality of wirings WL extend in the Y direction.

As in the present embodiment, in the portion LD2 in which the plurality of wirings WL extend along the direction intersecting the Y direction and the X direction, the length of the chip is reduced to reduce the cost of the chip, thereby reducing the length of the input unit IPC. When the length PL1 is small, or when the space between the side BSs1 of the substrate BS and the display portion DP in the frame portion FL is narrowed to narrow the frame, the distance between the adjacent wirings WL is narrow in the portion LD2. Become. In other words, it is necessary to improve the wiring density in the partial LD2.

Next, a case where the wiring WL is laid out in a single layer as in the display device LCD2 shown in FIG. 7 will be examined. When a plurality of wirings WL are laid out in a single layer like the display device LCD2, the number of wirings WL that can be laid out is defined by the minimum value of the separation distance between the adjacent wirings WL. For example, when a plurality of wirings WL1 shown in FIG. 7 have a wiring width of 4.2 μm and a distance between adjacent wirings WL1 is 5.1 μm, and the wiring lines are laid out under a design rule, The distance between the centers of the adjacent wirings WL1 in the LD2 must be 9.3 μm or more. In other words, in the case of the layout shown in FIG. 7, it is necessary to arrange the wirings WL1 in the partial LD2 at a wiring pitch of 9.3 μm or more.

Next, as in the display device LCD3 shown in FIGS. 8 and 9, a case will be examined in which the wiring WL is routed in two wiring layers sandwiching an insulating film. For example, one wiring layer sandwiching the insulating film is the same layer as the gate electrode of the TFT, and the other wiring layer is the same layer as the source/drain electrodes of the TFT. When the wiring WL is routed in the two wiring layers, as shown in FIGS. 8 and 9, the wiring WL1 provided in the first wiring layer L1 (see FIG. 9) and the second wiring layer L1 are provided. It is preferable that the wiring WL2 provided in L2 (see FIG. 9) be provided so as not to overlap with each other. By providing the wiring WL1 and the wiring WL2 so as not to overlap with each other, the current flowing through the wiring WL1 and the current flowing through the wiring WL2 can be prevented from interfering with each other.

Therefore, in the example of the display device LCD3, as shown in FIG. 8, the wirings WL1 and the wirings WL2 are arranged alternately in a plan view. In this case, among the plurality of wirings WL1 formed in the wiring layer L1 of the first layer (see FIG. 9), the space between the adjacent wirings WL1 can be utilized as the formation region of the wiring WL2, and thus the first layer The wiring density can be improved by using only the wiring layer L1 as compared with the case where the wiring WL is routed. Each of the wirings may be a single layer metal or may be a stack of a plurality of metals.

For example, in the example shown in FIG. 9, in the wiring layer L1, the wiring width W1 of each of the plurality of wirings WL1 is 4.2 μm, and the distance between adjacent wirings WL1 is 5.1 μm. In the wiring layer L2, the wiring width W2 of each of the plurality of wirings WL2 is 1.8 μm, and the distance between the adjacent wirings WL2 is 7.5 μm. In this case, among the plurality of wirings WL shown in FIG. 8, the distance between the centers of the wirings WL adjacent to each other in plan view is about 4.7 μm. In other words, in the case of the layout shown in FIG. 8, since the wiring pitch in the partial LD2 may be 4.7 μm or more, the wiring density can be improved as compared with the case of the display device LCD2 shown in FIG. ..

By the way, when the wiring WL is formed in each of a plurality of wiring layers as in the display device LCD3, the design rule of the wiring width and the distance between the wirings, that is, the wiring width and The lower limit of the distance between wires may differ. For example, it has been described that TFTs are formed as a plurality of display elements in the display element section DPQ shown in FIG. From the viewpoint of efficiently forming the plurality of wiring layers of the lead-out wiring portion LD shown in FIGS. 8 and 9, it is preferable to collectively form the gate electrode and the source electrode of the TFT. In this case, the design rule of the wiring width and the distance between the wirings may be different for each wiring layer due to the manufacturing process of the TFT.

For example, in the case where the TFT, which is the display element described above, has a bottom gate type structure in which the gate electrode GT is formed below the source electrode ST and the drain electrode DT like the transistor Q1 shown in FIG. The gate electrode GT is formed on the wiring layer L1 (see FIG. 1). Further, the source electrode ST and the drain electrode DT are formed on the second wiring layer L2. In the example shown in FIG. 11, the gate electrode GT is formed in the first wiring layer L1 and covered with an insulating film (insulating layer) IL1 which is a gate insulating film. The insulating film IL1 is, for example, an inorganic insulating film made of silicon oxide, silicon nitride, or a laminated film thereof. Further, the source electrode ST and the drain electrode DT are formed in the second wiring layer L2 provided on the insulating film IL1 and covered with the insulating film (insulating layer) IL2. The insulating film IL2 is an insulating film that functions as a protective film for the transistor Q1 and the wiring layer L2. Since the insulating film IL2 covers the transistor Q1, the insulating film IL2 is formed of an organic film having better coverage than an inorganic film, and is further covered with an insulating film (insulating layer) IL3 formed of an inorganic insulating film such as silicon nitride.

In the manufacturing process of the transistor Q1 shown in FIG. 11, after the gate electrode GT is formed, the semiconductor layer SCL is formed on the insulating film IL1 which is a gate insulating film covering the gate electrode GT. Although the transistor in FIG. 11 is a bottom gate, a top gate transistor in which a semiconductor layer is formed on the side close to the base body BSg, a gate insulating film is formed after the semiconductor layer is formed, and a gate electrode is provided over the gate insulating film is also used. Exists. Heat treatment may be performed at the time of forming the transistor, and the wiring WL1 (see FIGS. 8 and 9) formed in the wiring layer L1 in which the gate electrode GT is formed is often required to have resistance to the heat treatment. Therefore, the wiring layer L1 may be formed of a refractory metal material such as molybdenum (Mo). On the other hand, since the source electrode ST and the drain electrode DT can be formed after the heat treatment, the wiring WL1 (see FIGS. 8 and 9) formed in the wiring layer L2 has a low resistance metal material such as aluminum. Can be used. As a result, the wiring WL2 of the wiring layer L2 can have a narrower wiring width than the wiring WL1 of the wiring layer L1.

Note that the above example of using different metal materials for the wiring WL1 and the wiring WL2 is an example of the reason why the design rules of the wiring width and the distance between the wirings are different for each wiring layer. Aluminum may be used in some cases. However, even when the same metal material is used for the wiring WL1 and the wiring WL2, the design rules for the wiring thickness, the wiring width, and the distance between the wirings are different for each wiring layer due to process restrictions or step coverage. May be different.

In the example shown in FIG. 9, the wiring WL2 is an aluminum wiring, and as a design rule, the distance between the wirings may be 2.5 μm or more, for example. Therefore, if all the wirings WL are arranged in the second wiring layer L2 shown in FIG. 9, the distance between the centers of the adjacent wirings WL2, that is, the wiring pitch becomes about 4.3 μm. That is, in the case of the example shown in FIG. 9, the wirings WL1 and the wirings WL2 are alternately arranged in a plan view, and therefore, as compared with the case where all the wirings WL are provided in the second wiring layer L2, The wiring density is low. In this way, when the wiring width and the inter-wiring distance design rule are different for each wiring layer and the wirings WL1 and the wirings WL2 are simply arranged alternately, a single layer of the second wiring layer L2 is used. It was found that the wiring density may be lowered rather than the case where the wiring WL is routed.

Therefore, the inventor of the present application further studied a configuration capable of increasing the wiring density when arranging the wiring WL in each of a plurality of wiring layers, and configured the configuration of the present embodiment shown in FIGS. 6 and 10. I found it. That is, in the display device LCD1, the number of wirings WL2 formed in the wiring layer L2 in which it is relatively easy to improve the wiring density is smaller than the number of wirings WL1 in the wiring layer L1 in which it is relatively difficult to improve the wiring density. There are also many.

As shown in FIGS. 6 and 10, the lead-out wiring portion LD (see FIG. 6) included in the display device of the present embodiment is composed of a plurality of wiring layers L1 (see FIG. 10) and wiring layers L2 (see FIG. 10). Wiring layer. A plurality of wirings WL1 having a wiring width W1 are formed in the wiring layer L1, and a plurality of wirings WL2 having a wiring width W2 narrower than the wiring width W1 are formed in the wiring layer L2. That is, the wiring layer L2 is a wiring layer in which the wiring density is relatively easy to be improved as compared with the wiring layer L1. As described above, the point that the plurality of wirings WL1 and the plurality of wirings WL2 having different wiring widths are formed in the plurality of wiring layers is similar to the display device LCD3 shown in FIGS. 8 and 9.

Further, in the case of the display device LCD3 shown in FIGS. 8 and 9, since the wirings WL1 and the wirings WL2 are alternately arranged, the number of the wirings WL1 and the number of the wirings WL2 are the same. On the other hand, in the case of the display device LCD1 shown in FIGS. 6 and 10, in plan view, a plurality of (two in FIG. 6) wirings WL2 are formed between the adjacent wirings WL1. Therefore, the number of the plurality of wirings WL2 formed in the wiring layer L2 shown in FIG. 10 is larger than the number of the plurality of wirings WL1 formed in the wiring layer L1. That is, in the display device LCD1 of the present embodiment, the number of wirings WL2 formed in the wiring layer L2 in which the wiring density is relatively easy to be improved is formed in the wiring layer L1 in which the wiring density is relatively hard to be improved. Since the number of the wirings WL1 is larger than the number of the wirings WL1, the wiring density of the plurality of wirings WL can be improved.

In the example shown in FIG. 10, the wiring width W2 of the wiring WL2 is 1.8 μm, and the wiring distance of the wiring layer L2 may be 2.5 μm or more, for example. On the other hand, the wiring width W1 of the wiring WL1 is 4.2 μm, and the inter-wiring distance of the wiring layer L1 may be, for example, 5.1 μm or more. However, in the example shown in FIG. 10, the two wirings WL2 are arranged between the adjacent wirings WL1 in a plan view, and thus the wiring distance of the wiring layer L1 is 7.0 μm. In this case, since the three wirings WL are arranged in a range of 11.2 μm in a plan view, the center-to-center distance between the adjacent wirings WL, that is, the wiring pitch is about 3.7 μm. Therefore, in comparison with the case where the wiring WL is routed in the display device LCD2 shown in FIG. 7, the display device LCD3 shown in FIG. 8, or the single layer of the second wiring layer L2 shown in FIG. The density can be improved.

Further, in the above description, the width of the wiring WL is used as an index indicating the ease of improving the wiring density. However, as an index indicating the ease of improving the wiring density, the distance between adjacent wirings WL1 in the wiring layer L1 and the distance between adjacent wirings WL2 in the wiring layer L2 can be used for expression.

That is, in the wiring layer L1 shown in FIG. 10, a plurality of wirings WL1 are formed with a separation distance S1. Further, in the wiring layer L2, a plurality of wirings WL2 are formed with a separation distance S2 smaller than the separation distance S1. In the example illustrated in FIG. 10, the distances between the plurality of wirings WL2 include the distance S2 and the distance S4, but both the distance S2 and the distance S4 are smaller than the distance S1. As described above, when the distance between the adjacent wirings WL is different for each wiring layer, the wiring layer having a smaller distance can easily improve the wiring density. That is, in the example shown in FIG. 10, the wiring layer L2 is easier to improve the wiring density than the wiring layer L1.

Further, as described above, in the lead wiring portion LD shown in FIG. 5, particularly in the portion where the wiring density needs to be improved, the direction in which the plurality of wirings WL (see FIG. 6) intersects in the X direction and the Y direction. The portion LD2 extends to. For example, as shown in FIG. 6, in the portions LD1 and LD3 in which the plurality of wirings WL extend in the Y direction, the wiring density is lower than that in the portion LD2. Therefore, in the portion connected to the input unit IPC, each of the plurality of wirings WL can be collectively provided in, for example, the first wiring layer L1.

A method for electrically connecting the first-layer wiring layer L1 and the second-layer wiring layer L2 is as illustrated in FIG. 12, for example. FIG. 12 is an enlarged cross-sectional view showing a structural example for electrically connecting the wiring of the first wiring layer and the wiring of the second wiring layer shown in FIGS. 6 and 10.

In the example illustrated in FIG. 12, the opening OP1 is formed in the insulating film IL1 that covers the first wiring layer L1, and the wiring WL1 is exposed from the insulating film IL1 in the opening OP1. A part of the wiring WL2 formed in the second wiring layer L2 is embedded in the opening OP1 formed in the insulating film IL1 and electrically connected to the wiring WL1. By thus forming the opening OP1 in a part of the insulating film IL1 covering the wiring layer L1, the wiring WL2 of the second wiring layer L2 and the wiring WL1 of the first wiring layer L1 are separated from each other. It can be electrically connected. Note that FIG. 12 shows an example in which a plurality of wiring layers are integrated into the first wiring layer L1. However, as a modified example, the wiring layers may be integrated into the second wiring layer L2.

Further, as shown in FIG. 12, it is preferable that the opening OP1 that electrically connects the wiring WL1 and the wiring WL2 formed in different wiring layers is formed in the portion LD3 shown in FIG. In the part LD1, the part LD2, and the part LD3, the part LD3 closest to the input part IPC is divided into a plurality of wiring layers, so that the wiring density can be improved in the part LD2.

<Modification>
Next, typical modified examples of the modified examples of the above-described embodiment will be described.

<Modification 1>
In FIGS. 6 and 10, as an example of an embodiment in which wiring is formed in each of a plurality of wiring layers, a structural example in which a plurality of wirings WL are laid out in two wiring layers has been described. In the first modification, a structural example in which a plurality of wirings WL are routed in three wiring layers will be described. FIG. 13 is a modification of FIG. 6 and is an enlarged plan view showing a layout example in which a plurality of wirings are laid out in three wiring layers. Further, FIG. 14 is an enlarged cross-sectional view taken along the line AA of FIG. Note that in FIG. 13, in order to easily distinguish the wiring WL1, the wiring WL2, and the wiring WL3 formed in different layers, the wiring WL1 formed in the first layer is shown by a solid line and the wiring WL1 formed in the second layer is shown. The formed wiring WL2 is shown by a dotted line, and the wiring WL3 formed in the third layer is shown by a dashed line.

The display device LCD4 shown in FIGS. 13 and 14 is different from the display device LCD1 shown in FIG. 6 in that it has the wiring WL3 formed in the third wiring layer L3. The third wiring layer L3 is formed on the insulating film IL2 which covers the wiring layer L2 and is covered with the insulating film IL3 which is an inorganic insulating film. In the example shown in FIG. 14, the wiring width W3 of the wiring WL3 is wider than the wiring width W2 of the wiring WL2 of the second wiring layer L2. That is, the display device LCD4 of the first modification has different design rules for each wiring layer. Specifically, the wiring layer L2 relatively easily improves the wiring density, and the wiring layers L1 and L3 are less likely to improve the wiring density than the wiring layer L2.

Even in the case where the plurality of wirings WL are routed in three wiring layers having different design rules of the wiring layout as in the first modification, it can be considered in the same manner as the display device LCD1 described above. That is, in the display device LCD3, the number of wirings WL2 formed in the wiring layer L2 in which it is relatively easy to improve the wiring density is the number of wirings WL1 formed in the wiring layer L1 in which it is relatively difficult to improve the wiring density, And the number of wirings WL3 formed in the wiring layer L3. Accordingly, the wiring density of the plurality of wirings WL can be improved.

In the example shown in FIG. 14, the wiring width W1 of the wiring WL1 is 4.2 μm, and the separation distance S1 between the wirings WL1 of the wiring layer L1 may be, for example, 5.1 μm or more. The wiring width W2 of the wiring WL2 is 1.8 μm, and the separation distance S2 between the wirings WL2 of the wiring layer L2 may be 2.5 μm or more, for example. The wiring width W3 of the wiring WL3 is 4.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 may be 5.1 μm or more, for example.

However, in the example shown in FIG. 14, in order to prevent adjacent wirings WL from overlapping with each other in plan view, the separation distance S1 between the wirings WL1 in the wiring layer L1 is set to 9.7 μm and the wirings in the wiring layer L2 are arranged. The separation distance S2 of WL2 is 5.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 is 9.7 μm.

In this case, since the four wirings WL are arranged in a range of 13.9 μm in a plan view, the center-to-center distance between adjacent wirings WL, that is, the wiring pitch is about 3.5 μm. Therefore, the wiring density can be further improved as compared with the display device LCD1 shown in FIG.

Further, in the above description, the width of the wiring WL is used as an index indicating the ease of improving the wiring density. However, as an index indicating the ease of improving the wiring density, the distance between adjacent wirings WL1 in the wiring layer L1 and the distance between adjacent wirings WL2 in the wiring layer L2 can be used for expression.

That is, among the plurality of wirings WL2 formed in the wiring layer L2, the distance S2 between the adjacent wirings WL2 is larger than the distance S1 between the wirings WL1 in the wiring layer L1 and the distance S3 between the wirings WL3 in the wiring layer L3. small. Therefore, the wiring layer L2 is relatively easy to improve the wiring density, and the wiring layers L1 and L3 are less likely to improve the wiring density than the wiring layer L2.

The display device LCD4 shown in FIGS. 13 and 14 is the same as the display device LCD1 shown in FIGS. 6 and 10 except for the above-described differences. Therefore, redundant description will be omitted.

<Modification 2>
Next, in the display device LCD1 shown in FIG. 6, the display device LCD2 shown in FIG. 7, the display device LCD3 shown in FIG. 8, and the display device LCD4 shown in FIG. 13, the wirings WL formed in the respective wiring layers are mutually adjacent. Non-overlapping embodiments have been described. However, focusing on the point that the wiring density is improved, the wiring density can be improved when a part of the wirings WL formed in different wiring layers overlap each other in the thickness direction. On the other hand, when the wirings WL formed in different wiring layers partially overlap each other in the thickness direction, the signal lines interfere with each other to generate noise, the signal is affected by the parasitic capacitance between the wirings, and There is a possibility that the wiring may be short-circuited due to a film defect. Therefore, in the second modification, a technique will be described in which the wirings WL formed in different wiring layers partially overlap each other in the thickness direction, and the influence of noise in the overlapping portions is reduced.

FIG. 15 is a modification of FIG. 13 and is an enlarged plan view showing a layout example in the case where some of the plurality of wirings overlap in the thickness direction. 16 is an enlarged cross-sectional view taken along the line AA of FIG.

In the display device LCD5 shown in FIGS. 15 and 16, the wiring WL3 formed in the third wiring layer L3 and the wiring WL formed in the first wiring layer L1 overlap each other. , The display device LCD4 shown in FIG.

Further, as shown in FIG. 16, the thickness TH2 of the insulating film IL2 covering the wiring layer L2 is thicker than the thickness TH1 of the insulating film IL1 covering the wiring layer L1. Since the insulating film IL1 also serves as the gate insulating film of the transistor Q1 shown in FIG. 11, if the thickness TH1 is extremely large, it becomes difficult to drive the transistor Q1. On the other hand, the insulating film IL2 tends to be thick from the viewpoint of reliably covering the source electrode ST and the drain electrode DT. In the example shown in FIG. 16, the thickness of the insulating film IL1 is smaller than 1 μm, and the thickness of the insulating film IL2 is, for example, about 2 μm.

Here, in consideration of noise between the wiring layers, the influence can be reduced as the distance between the wiring layers increases. Therefore, the mutual influence between the wirings WL is likely to be large between the wiring layer L1 and the wiring layer L2 provided via the relatively thin insulating film IL1. On the other hand, the mutual influence between the wirings WL is easily reduced between the wiring layer L2 and the wiring layer L3 which are formed of an organic insulating film or the like and are provided via the relatively thick insulating film IL2.

From the above, the following configuration is preferable in consideration of noise influence between wiring layers and improvement of wiring density. That is, it is preferable that the plurality of wirings WL1 of the wiring layer L1 and the plurality of wirings WL2 of the wiring layer L2, which have a relatively large noise influence, do not overlap with each other. In this case, the plurality of wirings WL3 provided over the insulating film IL2 having the thickness TH2 larger than the thickness TH1 may overlap with the plurality of wirings WL1 and a part of the plurality of WL1.

Note that in the example illustrated in FIG. 16, the wiring WL3 and the wiring WL2 do not overlap with each other, but the thickness TH2 of the insulating film IL2 is sufficiently thick, the influence of noise and parasitic capacitance is low, and a short circuit between wirings may occur. When the width is low, the wiring WL3 and the wiring WL2 may overlap with each other.

When the wiring WL3 and the wiring WL2 do not overlap each other as in the example shown in FIG. 16, the distance between the wirings WL1 and WL3 overlapping each other is the sum of the thickness TH1 and the thickness TH2. The influence of noise can be reduced.

When the wirings WL formed in the plurality of wiring layers are provided so as to partially overlap each other, as in the display device LCD5 of the present modification 2, a plurality of wirings are further provided than the display device LCD4 shown in FIG. The wiring density of WL can be improved.

In the example shown in FIG. 16, the wiring width W1 of the wiring WL1 is 4.2 μm, and the separation distance S1 between the wirings WL1 of the wiring layer L1 may be, for example, 5.1 μm or more. The wiring width W2 of the wiring WL2 is 1.8 μm, and the separation distance S2 of the wiring WL2 of the wiring layer L2 may be 2.5 μm or more, for example. The wiring width W3 of the wiring WL3 is 4.2 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 may be 5.1 μm or more, for example.

However, in the example illustrated in FIG. 16, in plan view, the separation distance S1 between the wirings WL1 of the wiring layer L1 is 7.0 μm in order to prevent the wirings WL2 and the wirings WL1 from overlapping with each other. The separation distance S2 of the wiring WL2 of the wiring layer L2 is 2.5 μm, and the separation distance S3 of the wiring WL3 of the wiring layer L3 is 7.0 μm.

In this case, since the four wirings WL are arranged in a range of 9.2 μm in a plan view, the center-to-center distance between the adjacent wirings WL, that is, the wiring pitch is about 2.3 μm. Therefore, the wiring density can be further improved as compared with the display device LCD4 shown in FIG.

Except for the differences described above, the display device LCD5 shown in FIGS. 15 and 16 is the same as the display device LCD4 shown in FIGS. 13 and 14. Therefore, redundant description will be omitted.

<Modification 3>
When the wiring WL3 is formed on the insulating film IL2 as in the display device LCD4 described in the first modification and the display device LCD5 described in the second modification, a region in which the wiring WL3 is formed is not formed. The insulating film IL2 needs to be formed.

Here, the interface between the insulating film IL2 which is an organic insulating film and the insulating film IL1 which is an inorganic insulating film is characterized in that moisture easily enters from the outside of the display device. Therefore, from the viewpoint of preventing moisture from entering the display part DP (see FIG. 1), it is preferable to remove a part of the insulating film IL2 to form the slit SLT, as shown in FIG. FIG. 17 is an enlarged cross-sectional view showing a structural example of a portion which electrically connects wirings of a plurality of wiring layers in the display device shown in FIGS. 13 and 15. The slit SLT shown in FIG. 17 is a groove formed so as to extend along the X direction shown in FIG. 1, and the insulating film IL1 which is a base layer is exposed at the opening of the slit SLT.

In order to form the slit SLT as shown in FIG. 17, it is necessary to electrically connect the wiring WL3 of the third wiring layer L3 and the wiring WL2 of the wiring layer L2 in a region avoiding the slit. ..

On the other hand, as described above, in the lead wiring portion LD shown in FIG. 5, the portion for which the wiring density needs to be particularly improved is the portion LD2. Therefore, as shown in FIG. 17, the location where the slit SLT is formed is preferably the portion LD3 of the lead wiring portion LD. Further, it is preferable that the wiring WL3 of the third wiring layer L3 and the wiring WL2 of the wiring layer L2 are connected to each other by the portion LD3.

Although the invention made by the inventor of the present application has been specifically described above based on the embodiment and the typical modifications, for example, the various modifications described above can be combined and applied. Further, the wiring layer L3 can also be used as a metal for reducing the resistance of the common electrode in the case of a horizontal electric field type display device. When the wiring layer L3 is formed of a low resistance metal such as aluminum, the wiring layer L3 can be formed with the same wiring width and wiring interval as the wiring WL2. Alternatively, depending on the film thickness of the wiring layer L3, the wiring width can be made slightly thicker than the wiring WL2. Even in such a case, the present invention can be applied.

Further, the wiring WL1 and the wiring WL2 can be partially overlapped with each other depending on the characteristics of the insulating film L1. Similarly, when the insulating film L2 is formed of an inorganic film, the wiring WL2 and the wiring WL3 can be overlapped with each other. As a result, a higher density can be realized.

Further, in a top-gate thin film transistor, a light shielding metal for shielding the light of the backlight may be used between the backlight and the semiconductor layer. This light-shielding metal can be used instead of the wiring layer WL3. It is also possible to use the light shielding metal as the fourth wiring layer. Note that the wiring layer shown above is assumed to be a wiring connected to the source electrode or the drain electrode of the transistor in the display region, but a wiring connected to the gate of the thin film transistor, a wiring for supplying a clock, power, or the like. Alternatively, it can be applied to a wiring or the like for supplying a signal to a semiconductor chip. Further, for example, in the above-described embodiment, the display device using the liquid crystal layer as the display function layer is disclosed, but the present invention is not limited to this. For example, the above-described technique can be applied to a lead wiring portion of a so-called organic EL type display device that uses a light emitting element made of an organic compound as a display function layer.

It is understood that various modifications and modifications can be conceived by those skilled in the art within the scope of the concept of the present invention, and those modifications and modifications also belong to the scope of the present invention. For example, a person skilled in the art may appropriately add, delete, or change the design of each of the above-described embodiments, or may add, omit, or change the conditions of the process, and the present invention is also included in the scope of the present invention. Within the scope of the present invention.

INDUSTRIAL APPLICABILITY The present invention can be used in a display device and an electronic device incorporating the display device.

AF1, AF2 alignment film BM light shielding film BS, FS substrate BSb, FSb back surface BSf, FSf front surface BSg, FSg base material BSs1, BSs2, BSs3, BSs4 side CC circuit part CE common electrode CF color filter CFr, CFg, CFb color filter pixel CHP semiconductor chip CNT1 control circuit DP display portion DPQ display element portion DR1 drive circuit DT drain electrode FL frame portion GT gate electrodes IL1, IL2, IL3 insulating film IPC input portions L1, L2, L3 wiring layers LCD1, LCD2, LCD3, LCD4, LCD5 Display device LCL Liquid crystal layer LD Lead wiring section LD1, LD2, LD3 Part LS Light source OC1, OC2 Resin layer OP1 Opening PE Pixel electrodes PL1, PL2 Polarizing plate PS member Q1 Transistors S1, S2, S3, S4 Separation distance SCL Semiconductor layer SL seal part SLp seal material (sealing material)
SLT Slit ST Source electrode VW Viewer W1, W2, W3 Wiring width WL, WL1, WL2, WL3 Wiring

Claims (11)

A substrate having a first surface,
A display unit on the first surface of the substrate, the display unit including a plurality of pixels;
A frame portion around the display portion on the first surface of the substrate;
Have
The frame portion is an input portion to which signals supplied to the plurality of pixels are input, and a lead-out wiring portion that electrically connects the display portion and the input portion between the display portion and the input portion. And have,
The lead-out wiring portion includes a first wiring layer having a plurality of first wirings formed on the first surface, and a plurality of second wirings stacked on the first surface via the first wiring layer. A second wiring layer having a plurality of third wirings stacked on the first surface with the second wiring layer interposed therebetween, the first wiring layer and the second wiring layer A first insulating layer formed between the second wiring layer and the third wiring layer, and a second insulating layer formed between the second wiring layer and the third wiring layer,
The first wiring, the second wiring, and the third wiring are signal lines for transmitting a video signal,
In the lead-out wiring section,
Each of the first wiring layer, the second wiring layer, and the third wiring layer is arranged on a boundary side with the display unit, and the plurality of first, second, or third wirings are arranged in a first direction. A first portion extending along the first portion, a third portion arranged at a position distant from the display portion, and the plurality of first, second or third wirings extending along the first direction; A second portion disposed between the third portion and extending in a direction different from the first direction,
In a plan view, the plurality of first wirings and the plurality of second wirings are arranged so as not to overlap each other,
A plurality of first openings are formed in the first insulating layer in the third portion, and the plurality of first wirings of the first wiring layer and the second wiring layer are formed through the plurality of first openings. Is electrically connected to the plurality of second wirings ,
The second wiring is to connect the first wiring is embedded in the first opening, a display device. The display device according to claim 1, wherein
The display device, wherein the first insulating layer is made of an inorganic material and the second insulating layer is made of an organic insulating layer. The display device according to claim 2, wherein
In the lead-out wiring portion, a plurality of second openings are formed in the second insulating layer, and the plurality of second wirings of the second wiring layer and the third wiring layer are formed through the plurality of second openings. A display device electrically connected to the plurality of third wirings. The display device according to claim 1, wherein
In the third portion, a slit is formed in the second insulating layer so that the first insulating layer is exposed,
The display device in which the slit extends in a direction orthogonal to the first direction. The display device according to claim 2, wherein
The display device in which the plurality of third wirings overlaps a part of the plurality of first wirings and the plurality of second wirings in the second portion when seen in a plan view. The display device according to claim 2, wherein
In a plan view, the plurality of third wirings do not overlap with the plurality of second wirings and do not overlap with the plurality of first wirings in the second portion . The display device according to claim 2, wherein
In a plan view, the line width of each of the plurality of third wirings is wider than the line width of each of the plurality of second wirings. The display device according to claim 2, wherein
In a plan view, each of the plurality of second wirings is arranged between the plurality of first wirings adjacent to each other. The display device according to claim 2, wherein
The display device in which the plurality of first wirings and the plurality of second wirings are alternately arranged in a plan view. The display device according to claim 1, wherein
A display device in which the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings are formed of different materials. The display device according to claim 1, wherein
Each of the plurality of pixels of the display unit has a transistor having a gate electrode,
The display device, wherein the first wiring layer is formed in the same layer as the gate electrode.

Images