JP7227416B2 - Display device - Google Patents

Description

The present invention relates to the technology of a display device, and more particularly to a technology effectively applied to a display device having a non-display area that does not overlap with pixels in the display area.

Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2006-343728) describes a display device in which a light shielding portion is arranged between a video display portion and a transparent display portion. Further, Patent Document 2 (U.S. Patent Application Publication No. 2017/0123452) describes a display device provided with a transparent area at a position overlapping a camera.

JP-A-2006-343728 U.S. Patent Application Publication No. 2017/0123452

There is a demand for display devices to increase the occupation ratio of the effective display area by minimizing the area of the non-display area within the display area. As part of efforts to meet this demand, the inventors of the present application have studied a technique for enlarging the area of the display area to a position surrounding the area in which components such as a camera are arranged. In a plan view, when there is an area in which parts such as a camera are arranged inside the display area, the layout of many signal wirings arranged in the display area becomes an issue. For example, when a visible light transmissive transparent area is arranged inside the display area, it is necessary to detour around the transparent area so that a plurality of signal wirings do not overlap the transparent area.

An object of the present invention is to provide a technique for improving performance of a display device.

A display device according to one aspect of the present invention includes a display region, a transparent region inside the display region in plan view, and a display region surrounding the transparent region along an outer edge of the transparent region in plan view. a frame region between the transparent region; a plurality of scanning signal lines formed in a first conductive layer on the first substrate in the display region and extending in a first direction; and a plurality of video signal lines formed in a second conductive layer on the first substrate in the display area and extending in a second direction crossing the first direction. Some of the plurality of video signal lines are arranged in the display area, and a plurality of extended wiring portions extending in the second direction are arranged in the frame area, and both ends thereof are connected to the plurality of extended wiring portions. and a plurality of detour wiring portions. The plurality of detour wiring portions of the plurality of video signal lines include: a plurality of second layer detour wiring portions arranged in the second conductive layer; and a plurality of third layer detour wiring portions arranged in the conductive layer. An arrangement pitch of the plurality of second layer detour wiring portions and an arrangement pitch of the plurality of third layer detour wiring portions are each smaller than an arrangement pitch of the plurality of video signal lines in the display area.

A display device according to another aspect of the present invention includes a display area, a transparent area inside the display area in plan view, and a transparent area surrounding the transparent area along an outer edge of the transparent area in plan view. a picture frame region between the transparent region and the transparent region; a first substrate comprising the display region and the picture frame region; a plurality of scanning signal lines extending; and a plurality of video signal lines formed in a second conductive layer on the first substrate in the display area and extending in a second direction intersecting the first direction. A portion of the plurality of scanning signal lines is arranged in the display region and extends in the first direction; and a plurality of first detour wiring portions connected to the wiring portion. Some of the plurality of video signal lines are arranged in the display area and extend in the second direction; and a plurality of second detour wiring portions connected to the wiring portion. The arrangement pitch of the plurality of first detour wiring portions is larger than the arrangement pitch of the plurality of first extended wiring portions. The arrangement pitch of the plurality of second detour wiring portions is smaller than the arrangement pitch of the plurality of second extended wiring portions. The frame area is arranged next to the transparent area in the first direction, and includes a first area in which a part of each of the plurality of second detour wiring portions is arranged, and the transparent area in the first direction. a second region disposed on the opposite side of the first region across the region and in which other parts of the plurality of second detour wiring portions are disposed; and a second region adjacent to the transparent region in the second direction. a third region in which a part of each of the plurality of first detour wiring portions is arranged; and a fourth region in which another portion of each of the plurality of first detour wiring portions is arranged.

1 is a plan view of a display surface side showing an example of a display device according to an embodiment; FIG. FIG. 2 is a cross-sectional view taken along line AA of FIG. 1; 2 is a circuit diagram showing a circuit configuration example around a pixel included in the display device shown in FIG. 1; FIG. 3 is an enlarged sectional view of a display area of the display device shown in FIG. 2; FIG. 2 is an enlarged plan view of the first conductive layer around the transparent region shown in FIG. 1; FIG. 2 is an enlarged plan view of the second conductive layer around the transparent region shown in FIG. 1; FIG. 2 is an enlarged plan view of a third conductive layer around a transparent region shown in FIG. 1; FIG. FIG. 8 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions shown in FIGS. 6 and 7 are arranged; 6 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions shown in FIG. 5 are arranged; FIG. 8 is an enlarged plan view showing a state in which the detour wirings shown in FIGS. 6 and 7 are overlapped in the B portion shown in FIG. 7; FIG. 11 is an enlarged plan view showing a state in which the detour wirings shown in FIGS. 5 and 6 are overlapped at the same position as in FIG. 10; FIG. FIG. 12 is an enlarged cross-sectional view taken along line AA shown in FIGS. 10 and 11; 8 is an enlarged plan view of the periphery of a portion connecting the second conductive layer shown in FIG. 6 and the third conductive layer shown in FIG. 7; FIG. 14 is an enlarged plan view of a portion A of FIG. 13; FIG. 15 is an enlarged cross-sectional view along line AA of FIG. 14; FIG. FIG. 2 is an enlarged plan view showing a planar shape of a sealing material arranged in a frame area around the transparent area shown in FIG. 1; FIG. 17 is an enlarged cross-sectional view taken along line AA of FIG. 16; FIG. 7 is an enlarged plan view of a second conductive layer around a transparent region included in a display device that is a modification of FIG. 6; 19 is an enlarged plan view schematically showing a region where a plurality of detour wiring portions shown in FIG. 18 are arranged; FIG. 19 is an enlarged plan view schematically showing a region where a plurality of detour wiring portions of the first conductive layer of the display device shown in FIG. 18 are arranged; FIG. FIG. 13 is an enlarged cross-sectional view showing a modification to FIG. 12;

Each embodiment of the present invention will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art will naturally include within the scope of the present invention any appropriate modifications that can be easily conceived while maintaining the gist of the invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example, and the interpretation of the present invention is not intended. It is not limited. In addition, in this specification and each figure, the same or related reference numerals may be given to elements similar to those described above with respect to the previous figures, and detailed description thereof may be omitted as appropriate.

In the following embodiments, a liquid crystal display device including a liquid crystal layer, which is an electro-optical layer, will be described as an example of the display device. However, the technique described below can be applied to various modifications other than the liquid crystal display device. For example, the electro-optical layer includes, in addition to the liquid crystal layer, an organic light-emitting element layer, an inorganic light-emitting element layer including a micro LED, a MEMS (Micro Electro Mechanical Systems) shutter, or an electrophoretic element layer, which applies electrical energy. Therefore, any layer may be used as long as it includes an element whose optical characteristics change.

In the present application, terms such as wiring width, arrangement pitch, or arrangement density of a plurality of wirings (scanning signal lines and video signal lines, which will be described later) that are arranged adjacent to each other in plan view may be used. The above terms are defined as follows. The wiring width is the length of the wiring in the direction orthogonal to the extending direction (longitudinal direction) of the wiring. The placement pitch is the center-to-center distance between adjacent wirings. The wiring density is the proportion of conductor patterns that constitute wiring per unit area. The wiring density is defined by the relationship between the wiring width and the arrangement pitch (center-to-center distance). That is, if the wiring width is a constant, the wiring density is inversely proportional to the arrangement pitch. Also, if the arrangement pitch is a constant, the wiring density is proportional to the wiring width. Also, the separation distance between wirings is the distance between wirings adjacent to each other. Note that each of the plurality of wirings has a trapezoidal cross-sectional shape in the cross section in the width direction. In this case, the distance between adjacent wirings means the distance between the bases of the trapezoids of the adjacent wirings. Also, the wiring width means the length of the base of the trapezoid that the wiring has. In this specification, the term "line and space" may be used. In this line and space, "line" means wiring width and "space" means separation distance.

Further, liquid crystal display devices are roughly classified into the following two types according to the application direction of an electric field for changing the orientation of liquid crystal molecules in a liquid crystal layer. That is, as a first classification, there is a so-called vertical electric field mode in which an electric field is applied in the thickness direction (or out-of-plane direction) of the display device. Vertical electric field modes include, for example, TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. As a second classification, there is a so-called horizontal electric field mode in which an electric field is applied in the planar direction (or in-plane direction) of the display device. The lateral electric field mode includes, for example, an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode, which is one of the IPS modes. The technique described below can be applied to both the vertical electric field mode and the horizontal electric field mode, but in the embodiments described below, the horizontal electric field mode display device will be taken as an example and explained.

(Embodiment 1)
<Configuration of display device>
First, the configuration of the display device will be described. FIG. 1 is a plan view of the display surface side showing an example of the display device of this embodiment. In FIG. 1, the boundary between the display area DA and the peripheral area PFA, the boundary between the display area DA and the frame area FRA, and the boundary between the frame area FRA and the transparent area TRA are indicated by two-dot chain lines. Also, in FIG. 1, the area where the sealing material SLM is arranged is indicated by a dot pattern. FIG. 2 is a cross-sectional view along line AA of FIG. As shown in later-described FIG. 4, there are a plurality of conductive layers and insulating layers in addition to the liquid crystal layer LQ between the substrate 10 and the substrate 20, but they are omitted in FIG. FIG. 3 is a circuit diagram showing a circuit configuration example around a pixel included in the display device shown in FIG. 4 is an enlarged sectional view of the display area of the display device shown in FIG. 2. FIG. FIG. 4 shows an example of the positional relationship between the scanning signal lines GL and the video signal lines SL in the thickness direction of the substrate 10 (the Z direction shown in FIG. 4). A line GL is indicated by a dotted line.

As shown in FIG. 1, the display device DSP1 of this embodiment has a display area DA. An image is formed in the display area DA according to an input signal supplied from the outside. The display area DA is an effective area in which the display device DSP1 displays an image in a plan view of the display surface. The display device DSP1 also has a peripheral area (non-display area) PFA around the display area DA in a plan view. The display device DSP1 has a peripheral area PFA around the display area DA, but as a modification, there is also a display device in which the display area DA extends to the peripheral edge. The technique described below can also be applied to a type of display device in which the display area DA extends to the periphery of the display device. Moreover, although the display area DA of the display device DSP1 shown in FIG. 1 is rectangular, the display area may have a shape other than a rectangular shape such as a polygon or a circle. For example, each of the four corners of the display area DA may be rounded.

The display device DSP1 also has a transparent area TRA inside the display area DA and a frame area FRA in plan view. The frame area FRA surrounds the transparent area TRA along the outer edge of the transparent area TRA in plan view, and is between the display area DA and the transparent area TRA. Further, the frame area FRA is shielded from light by a light shielding film BM which will be described later, and the frame area FRA can be rephrased as a "light shielding area". The transparent area TRA is an area in which components such as a camera attached to the display device DSP1 are arranged. The transparent area TRA is formed so as to transmit visible light in order to irradiate a member such as a camera with visible light. For example, the substrate and the polarizing plate that constitute the display device are provided with an opening in the transparent region TRA. Alternatively, the transparent region TRA is provided with a visible light transmissive member and is not provided with a light shielding member such as metal wiring. In addition to the camera, parts such as a microphone or a speaker may be placed in the transparent area TRA or the frame area FRA.

As shown in FIG. 2, the display device DSP1 has a substrate 10 and a substrate 20 that are bonded to face each other with a liquid crystal layer LQ interposed therebetween. The substrate 10 and the substrate 20 face each other in the thickness direction (Z direction) of the display device DSP1. The substrate 10 has a front surface (main surface, surface) 10f facing the liquid crystal layer LQ (and the substrate 20). The substrate 20 also has a rear surface (main surface, surface) 20b facing the front surface 10f of the substrate 10 (and the liquid crystal layer LQ). The substrate 10 is an array substrate in which a plurality of transistors (transistor elements) Tr1 (see FIG. 3) as switching elements (active elements) are arranged in an array. Further, the substrate 20 is a substrate provided on the display surface side. The substrate 20 can be rephrased as a counter substrate in the sense of being a substrate arranged opposite to the array substrate.

Also, the liquid crystal layer LQ is between the front surface 10 f of the substrate 10 and the rear surface 20 b of the substrate 20 . The liquid crystal layer LQ is an electro-optic layer that controls the transmission state of visible light. It has the function of modulating the light passing therethrough by controlling the state of the electric field formed around the liquid crystal layer LQ via the switching element. The display area DA on the substrate 10 and the substrate 20 overlaps the liquid crystal layer LQ as shown in FIG.

Further, the substrate 10 and the substrate 20 are adhered via a sealing material (adhesive material) SLM. As shown in FIG. 1, the sealing material SLM is arranged in the peripheral area PFA so as to surround the display area DA. As shown in FIG. 2, there is a liquid crystal layer LQ inside the sealing material SLM. The sealing material SLM serves as a seal that seals the liquid crystal between the substrates 10 and 20 . In addition, the sealing material SLM serves as an adhesive that bonds the substrate 10 and the substrate 20 together.

The display device DSP1 also has an optical element OD1 and an optical element OD2. The optical element OD1 is arranged between the substrate 10 and the backlight unit BL. The optical element OD2 is arranged on the display surface side of the substrate 20, that is, on the side opposite to the substrate 10 with the substrate 20 interposed therebetween. Each of the optical element OD1 and the optical element OD2 includes at least a polarizing plate, and may include a retardation plate if necessary. Further, as described above, the optical elements OD1 and OD2 that may hinder transparency are not formed in the transparent area TRA. More specifically, the optical elements OD1 and OD2 are provided with openings along the shape of the transparent region TRA.

The display device DSP1 also includes a cover member CVM (see FIG. 2) that covers the display surface side of the substrate 20 . The cover member CVM faces the front surface (surface) 10f on the opposite side of the back surface (surface) 20b of the substrate 20 . In other words, the cover member CVM faces the front surface (surface) 20f opposite to the back surface (surface) 20b of the substrate 20 . The substrate 20 is between the cover member CVM and the substrate 10 in the Z direction. The cover member CVM is a protective member that protects the substrates 10 and 20 and the optical element OD2, and is arranged on the display surface side of the display device DSP1. However, as a modification of this embodiment, there may be no cover member CVM.

Each of the substrate 10 and the substrate 20 is a transparent plate material having visible light transmittance (property of transmitting visible light). A glass substrate can be exemplified as a substrate that is a transparent plate material. Also, as the constituent material of the substrate 10 and the substrate 20, a resin material (visible light transmissive resin material) containing a polymer such as polyimide, polyamide, polycarbonate, or polyester can be used. Moreover, in the case of a substrate made of a resin material such as polyimide, the substrate is flexible. If the substrate 10 is flexible, a portion of the substrate 10 (for example, the peripheral area PFA) can be curved or folded. When the substrate 10 and the substrate 20 are flexible, the area of the peripheral area PFA in plan view can be reduced. In this case, the occupation ratio of the effective display area in plan view can be increased.

As shown in FIG. 3, a plurality of picture elements (pixels) PX are arranged in the display area DA. In the example shown in FIG. 3, each of the multiple pixels PX has multiple sub-pixels (sub-pixels) PXs. The multiple sub-pixels PXs include sub-pixels PXs for red, blue, and green, for example, and a color image can be displayed by controlling the color tone of the multiple sub-pixels PXs. The number of types of sub-pixels PXs that constitute one pixel PX can be applied to various modifications other than the three types illustrated in FIG.

Each of the plurality of sub-pixels PXs has a transistor Tr1 which is a switching element for controlling on/off of the electric field applied to the liquid crystal layer LQ. The transistor Tr1 controls the operation of the sub-pixel PXs. The transistor Tr1 is a thin film transistor (TFT) formed on the substrate 10, as will be described later.

Further, as shown in FIG. 3, the display device DSP1 has a plurality of scanning signal lines GL extending in the X direction in the display area DA, and a Y direction intersecting the X direction (perpendicular in FIG. 3) in the display area DA. and a plurality of video signal lines SL extending to the A scanning signal line GL is a gate line connected to the gate of the transistor Tr1. A video signal line SL is a source line connected to the source of the transistor Tr1. Each of the plurality of scanning signal lines GL extends in the X direction and is arranged, for example, at regular intervals in the Y direction. Each of the plurality of video signal lines SL extends in the Y direction and is arranged, for example, at equal intervals in the X direction.

Each of the plurality of scanning signal lines GL is connected to a scanning drive circuit (gate drive circuit) GD. A scanning signal Gsi output from the scanning drive circuit GD is input to the gate of the transistor Tr1 via the scanning signal line GL. Also, each of the plurality of video signal lines SL is connected to the video signal drive circuit SD. A video signal Spic output from the video signal drive circuit SD is input to the source of the transistor Tr1 via the video signal line SL.

Each of the plurality of video signal lines SL is connected to the pixel electrode PE via the transistor Tr1. Specifically, the video signal line SL is connected to the source of the transistor Tr1, and the pixel electrode PE is connected to the drain of the transistor Tr1. When the transistor Tr1 is turned on, the pixel electrode PE is supplied with the video signal Spic from the video signal line SL. Also, the pixel electrode PE is connected to the common electrode CE via a dielectric layer (capacitor CS shown in FIG. 3). A fixed potential is supplied to the common electrode CE from a common potential supply circuit CD. The fixed potential supplied to the common electrode CE is a potential common to the plurality of sub-pixels PXs. In the display period, an electric field is formed in each sub-pixel PXs according to the potential difference between the potential supplied to the common electrode CE and the potential supplied to the pixel electrode PE. Molecules are driven.

Each of the scanning drive circuit GD, the video signal drive circuit SD, and the common potential supply circuit CD shown in FIG. 3 is formed on the peripheral area PFA shown in FIG. 1 or on the wiring board FWB1 connected to the peripheral area PFA. A circuit mounted on the IC chip (CB1) may be used, or a built-in circuit formed on the substrate 10 may be used. Also, although not described in detail, the wiring board FWB1 is connected to a plurality of terminals TM1 formed on the board 10 .

As shown in FIG. 4, between the substrate 10 and the liquid crystal layer LQ are a plurality of conductive layers CL1-CL5, a plurality of insulating films 11-16, and an alignment film AL1. A plurality of conductive layers CL1-CL5, a plurality of insulating films 11-16, and an alignment film AL1 are formed on the front surface 10f of the substrate 10. FIG. Between the substrate 20 and the liquid crystal layer LQ are a light shielding film BM, color filters CFR, CFG and CFB, an insulating film OC1, and an alignment film AL2. A light shielding film BM, color filters CFR, CFG, CFB, an insulating film OC1, and an alignment film AL2 are formed on the back surface 20b of the substrate 20. FIG.

Conductive layers CL1, CL2 and CL3 shown in FIG. 4 are each formed with a metal conductor pattern (metal wiring). The conductive layer CL1 and the conductive layer CL3 include metal films made of metals such as molybdenum (Mo) and tungsten (W) or alloys thereof. The conductor pattern of the conductive layer CL2 includes a multi-layer metal film such as a laminated film in which an aluminum (Al) film is sandwiched between titanium (Ti) films, titanium nitride (TiN) films, or the like. Also, the conductive layer CL4 and the conductive layer CL5 mainly contain a conductive oxide material (transparent conductive material) such as ITO (Indium tin oxide) or IZO (Indium Zinc Oxide).

An insulating film is interposed between the conductive layers CL1 to CL5. Insulating film 11 and insulating film 12 are interposed between conductive layer CL1 and substrate 10 . An insulating film 13 is interposed between the conductive layer CL1 and the conductive layer CL2. An insulating film 14 is interposed between the conductive layer CL3 and the conductive layer CL4. An insulating film 15 is interposed between the conductive layer CL4 and the conductive layer CL5. An alignment film AL1 is interposed between the conductive layer CL5 and the liquid crystal layer LQ. Each of the insulating films 11, 12, 13, and 16 is an inorganic insulating film. Examples of the inorganic insulating film include a silicon nitride (SiN) film, a silicon oxide (SiO) film, an aluminum oxide (AlOx) film, or a laminated film thereof. Moreover, the insulating film 14 and the insulating film 15 are organic insulating films. By forming the insulating film made of an organic material thicker than the insulating film made of an inorganic material, the upper surface (front surface) can be flattened. The insulating film 14 and the insulating film 15 are used as planarizing films for planarizing the unevenness of the conductor pattern formed on the underlying layer. Therefore, the thickness of the insulating film 14 and the thickness of the insulating film 15 are thicker than the respective thicknesses of the insulating films 11, 12, and 13, which are inorganic insulating films. Examples of the organic insulating film include acrylic photosensitive resin.

Each of the plurality of scanning signal lines GL is formed on the conductive layer CL1 on the substrate 10. As shown in FIG. An insulating film 11 and an insulating film 12 are laminated on the substrate 10 , and the scanning signal lines GL are formed on the insulating film 12 . Each of the plurality of video signal lines SL is formed on the conductive layer CL2 on the substrate 10. FIG. Insulating films 11 , 12 and 13 are laminated on the substrate 10 , and the video signal line SL is formed on the insulating film 13 .

Between the insulating films 11 and 12, a semiconductor layer of the transistor (transistor element) Tr1 shown in FIG. 3 is formed. The semiconductor layer is not shown in FIG. 4 because it is in a different cross-section than in FIG. The source region of the semiconductor layer is electrically connected to the video signal line SL formed on the conductor layer CL2. A drain region of the semiconductor layer is electrically connected to the pixel electrode PE of the conductor layer CL5. In plan view, the scanning signal line GL extends between the source region and the drain region of the semiconductor layer. Also, the scanning signal line GL overlaps with the channel region of the semiconductor layer and functions as the gate electrode of the transistor Tr1. The insulating film 12 interposed between the channel region and the scanning signal line GL functions as a gate insulating film. A TFT having a structure in which the gate electrode is arranged above the channel region of the transistor Tr1 as in the above example is called a top-gate type TFT. However, there are various modifications of the TFT method, and for example, a bottom gate method in which a gate electrode is arranged below a channel region may be used. Alternatively, there is also a scheme in which gate electrodes are arranged both above and below the channel region.

A wiring MW3 is arranged on the conductive layer CL3. The wiring MW3 is a metal wiring made of metal like the scanning signal lines GL and the video signal lines SL. The wiring MW3 is arranged at a position overlapping the video signal line SL in the thickness direction (Z direction). The wiring MW3 is electrically connected to the common electrode CE formed over the conductive layer CL4. In this case, the wiring MW3 can be used as a wiring that supplies a potential to the common electrode CE. Alternatively, when the display device DSP1 has a touch panel function, the wiring MW3 is used as a signal transmission path for transmitting drive signals and detection signals used for detecting a touch position.

A common electrode CE is formed on the conductive layer CL4. The common electrode CE is formed on the insulating film 15 which is a planarizing film. Although one common electrode CE is shown in FIG. 4, a plurality of common electrodes CE may be spaced apart from each other in the display area DA shown in FIG. Further, as described above, the common electrode CE is supplied with a potential common to the plurality of sub-pixels PXs. Therefore, as shown in FIG. 4, the common electrode CE may be arranged over a plurality of sub-pixels PXs.

A plurality of pixel electrodes PE are formed on the conductive layer CL5. An insulating film 16, which is an inorganic insulating film, is interposed between the conductive layer CL5 on which the pixel electrode PE is formed and the conductive layer CL4 on which the common electrode CE is formed. The insulating film 16 functions as a dielectric layer to form the capacitive element CS shown in FIG.

The plurality of pixel electrodes PE are covered with an alignment film AL1. The alignment film AL1 is an organic insulating film having a function of aligning the initial alignment of the liquid crystal molecules contained in the liquid crystal layer LQ, and is made of polyimide resin, for example. Also, the alignment film AL1 is in contact with the liquid crystal layer LQ.

Further, as shown in FIG. 4, on the rear surface (main surface) 20b of the substrate 20, a light shielding film BM, color filters CFR, CFG, CFB, an insulating film OC1, and an alignment film AL2 are formed.

Color filters CFR, CFG and CFB are formed on the back surface 20 b side facing the substrate 10 . In the example shown in FIG. 3, three color filters CFR, CFG, and CFB of red (R), green (G), and blue (B) are arranged periodically. In a color display device, for example, a color image is displayed using pixels of three colors of red (R), green (G), and blue (B) as one set. A plurality of color filters CFR, CFG, and CFB on the substrate 20 are arranged at positions facing each pixel PX (see FIG. 1) having a pixel electrode PE formed on the substrate 10 . Note that the types of color filters are not limited to the three colors of red (R), green (G), and blue (B).

A light shielding film BM is arranged at each boundary between the color filters CFR, CFG, and CFB of each color. The light shielding film BM is called a black matrix, and is made of, for example, black resin or low-reflectivity metal. The light shielding film BM is formed, for example, in a lattice shape in plan view. In other words, the light shielding film BM extends in the X direction and the Y direction. Specifically, the light shielding film BM has a plurality of portions extending in the Y direction and a plurality of portions extending in the X direction crossing the Y direction. By partitioning each pixel PX with a black matrix, light leakage and color mixture can be suppressed.

The light shielding film BM overlaps with the scanning signal lines GL, the video signal lines SL, and the wiring MW3, which are metal wirings, in the display area DA. By arranging the metal wiring having a light shielding property at a position overlapping with the light shielding film BM, the metal wiring becomes difficult to be visually recognized on the display screen. On the other hand, at least part of the common electrode CE and the pixel electrode PE are arranged at positions not overlapping the light shielding film BM. The common electrode CE and the pixel electrode PE are made of a conductive material that transmits visible light. Therefore, although the common electrode CE and the pixel electrode PE are arranged at positions not overlapping the light shielding film BM, visible light is not blocked by the common electrode CE and the pixel electrode PE in each sub-pixel PXs.

The light shielding film BM is also formed in the peripheral area PFA of the substrate 20 (see FIG. 1). The peripheral area PFA overlaps with the light shielding film BM. The display area DA is defined as an area inside the peripheral area PFA. The peripheral area PFA is an area that overlaps with the light shielding film BM that shields light emitted from the backlight unit (light source) BL shown in FIG. The light shielding film BM is also formed in the display area DA, and a plurality of openings are formed in the light shielding film BM in the display area DA. Generally, the end of the opening formed in the light shielding film BM and exposing the color filter, which is formed closest to the peripheral edge, is defined as the boundary between the display area DA and the peripheral area PFA.

The insulating film OC1 shown in FIG. 4 covers the color filters CFR, CFG, and CFB. The insulating film OC1 functions as a protective film that prevents impurities from diffusing from the color filter to the liquid crystal layer. The insulating film OC1 is an organic insulating film made of, for example, an acrylic photosensitive resin.

The insulating film OC1 is covered with the alignment film AL2. The alignment film AL2 is an organic insulating film having a function of aligning the initial alignment of the liquid crystal molecules contained in the liquid crystal layer LQ, and is made of polyimide resin, for example. Also, the alignment film AL2 is in contact with the liquid crystal layer LQ.

<Details around the transparent area TRA>
Next, the periphery of the transparent area TRA shown in FIG. 1 will be described in detail. 5 is an enlarged plan view of the first conductive layer around the transparent region shown in FIG. 1. FIG. 6 is an enlarged plan view of the second conductive layer around the transparent region shown in FIG. 1. FIG. 7 is an enlarged plan view of the third conductive layer around the transparent region shown in FIG. 1. FIG.

As shown in FIG. 5, each of the plurality of scanning signal lines GL extends in the X direction within the display area DA. Further, as shown in FIG. 6, each of the plurality of video signal lines SL extends in the Y direction within the display area DA. As shown in FIG. 3, one sub-pixel PXs is formed at one intersection between the scanning signal line GL and the video signal line SL.

Here, as shown in FIG. 5, when the transparent area TRA is arranged in the display area DA, some of the plurality of scanning signal lines GL linearly extending along the X direction are the scanning signal lines GL The transparent region TRA is arranged on the extension line of the extended wiring portion (scanning signal extended wiring portion) GLr. Similarly, as shown in FIG. 6, when the transparent area TRA is arranged in the display area DA, some of the plurality of video signal lines SL linearly extending along the Y direction are A transparent region TRA is arranged on an extension line of the extended wiring portion (extended wiring portion for video signal) SLr. However, in order to improve the visible light transmittance in the transparent area TRA, it is preferable that the scanning signal lines GL and the video signal lines SL, which are metal wirings, do not overlap the transparent area TRA. In this specification, in a part of the scanning signal line GL or the video signal line SL, a portion extending along one direction is called an extended wiring portion, and a portion bypassing the transparent region TRA is called a detour wiring portion. However, the term "wiring section" may be simply referred to as "wiring". For example, even if the "extended wiring section" is simply referred to as "extended wiring" and the "detour wiring section" is simply referred to as "detour wiring", the meaning is the same.

On the other hand, in order to use the area around the transparent area TRA as the display area, it is necessary to prevent the scanning signal lines GL and the video signal lines SL from being cut off near the transparent area TRA.

In the case of the display device DSP1 of the present embodiment, as shown in FIG. 5, some of the plurality of scanning signal lines GL are arranged in the display area DA and extend in the X direction. and a plurality of detour wiring portions GLc arranged in the frame region FRA of the conductive layer CL1 and having both ends connected to the plurality of extended wiring portions GLr. The detour wiring part GLc is a wiring that detours the transmission path of the scanning signal along the outer edge of the transparent region TRA. The detour wiring portion GLc forming the transmission path of the scanning signal may be referred to as a scanning signal detour wiring portion in this specification. Further, since the detour wiring portion GLc is formed in the conductive layer CL1 which is the first conductive layer, it may be referred to as a first layer detour wiring portion in the specification of the present application. The detour wiring portion GLc extends in a direction different from the X direction, which is the extending direction of the extended wiring portion GLr. In the example shown in FIG. 5, each of the multiple detour wiring portions GLc extends in an arc shape along the outer edge of the circular transparent region TRA. Further, each of the plurality of detour wiring portions GLc has two end portions GLe, and the extended wiring portion GLr is connected to each of the two end portions GLe.

In the case of the display device DSP1, as shown in FIG. 6, some of the plurality of video signal lines SL are arranged in the display area DA and extend in the Y direction to form a plurality of extended wiring portions (video signal extended wirings). part) SLr, and a plurality of detour wiring portions SLc2 arranged in the frame region FRA of the conductive layer CL2 and having both ends connected to the plurality of extended wiring portions SLr. The detour wiring part SLc2 is a wiring that detours the transmission path of the video signal along the outer edge of the transparent area TRA. In the present specification, the detour wiring section SLc2 forming the transmission path of the video signal may be referred to as a video signal detour wiring section. Further, since the detour wiring portion SLc2 is formed in the conductive layer CL2 which is the second conductive layer, it may be referred to as a second layer detour wiring portion in this specification. The detour wiring portion SLc2 extends in a direction different from the Y direction, which is the extending direction of the extended wiring portion SLr. In the example shown in FIG. 6, each of the multiple detour wiring portions SLc2 extends in an arc shape along the outer edge of the circular transparent region TRA. Further, each of the multiple detour wiring portions SLc2 has two end portions SLe, and the extended wiring portion SLr is connected to each of the two end portions SLe.

Here, in the frame area FRA where the detour wiring portion GLc shown in FIG. 5 and the detour wiring portion SLc2 shown in FIG. is different. Therefore, it is difficult to use the frame area FRA as an effective display area. Therefore, in order to increase the occupation ratio of the effective display area in plan view, it is preferable to reduce the area of the frame area FRA. Therefore, the inventor of the present application has studied a technique for reducing the area of the frame area FRA surrounding the transparent area TRA.

The lower limit of the number of wirings (scanning signal lines GL or video signal lines SL) arranged in the frame area FRA is defined by the relationship between the area of the transparent area TRA and the arrangement pitch of the wirings in the display area DA. For example, the planar shape of the transparent area TRA shown in FIG. 5 is circular, and the radius of this circle is 1080 to 4050 μm, and the arrangement pitch (center-to-center distance) of the scanning signal lines GL adjacent to each other in the display area DA is 54 μm. In this case, at least 40 to 150 scanning signal lines GL are arranged in the frame area FRA. Further, for example, the planar shape of the transparent area TRA shown in FIG. In some cases, at least 120 to 450 video signal lines SL are arranged in the frame area FRA.

In the case of a color display device, video signal lines SL for a plurality of colors are required. In the case of the present embodiment, the plurality of video signal lines SL shown in FIG. 6 includes a plurality of video signal lines SLR for transmitting video signals for a first color (for example, red) and a plurality of video signal lines SLR for transmitting a video signal for a second color (for example, blue). for green), and a plurality of video signal lines SLG for transmitting video signals for a third color (for example, for green). In this case, since three video signal lines SL are arranged in one pixel, the arrangement pitch of the video signal lines SL is smaller than the arrangement pitch of the scanning signal lines GL. Therefore, the number of video signal lines SL arranged in the frame area FRA is greater than the number of scanning signal lines GL arranged in the frame area FRA. Therefore, the number of video signal lines SL is more dominant than the number of scanning signal lines GL as a factor that defines the lower limit of the area of the frame region FRA. As will be described later as a modified example, as a modified example of FIG. 5, the detour wiring portion GLc may not be arranged in the frame area FRA.

In order to reduce the area of the frame area FRA, it is important to reduce the arrangement pitch of the video signal lines SL arranged in the frame area FRA shown in FIG. In the case of the display device DSP1, the arrangement pitch of the detour wiring portions of the video signal lines SL arranged in the frame area FRA is smaller than the arrangement pitch of the video signal lines SL in the display area DA. For example, in the example shown in FIG. 6, the arrangement pitch SLp1 of the video signal lines SL in the display area DA is 18 μm. On the other hand, the arrangement pitch SLp2 of the detour wiring portion SLc2 in the frame region FRA is 4.5 μm. In the case of the display device DSP1, since the arrangement pitch SLp2 of the detour wiring portions SLc2 is smaller than the arrangement pitch SLp1 of the video signal lines SL in the display area DA, the area of the frame area FRA can be reduced.

Further, in the case of the display device DSP1, the detour wiring portions of the video signal lines SL are formed in a plurality of conductive layers. That is, the plurality of detour wiring portions of the plurality of video signal lines SL include the plurality of detour wiring portions (second layer detour wiring portions) SLc2 arranged in the conductive layer CL2 shown in FIG. 6 and the conductive layer ( and a plurality of detour wiring portions (third layer detour wiring portions) SLc3 arranged in the third conductive layer) CL3. Also, the arrangement pitch SLp3 of the detour wiring portion SLc3 is smaller than the arrangement pitch SLp1 of the video signal lines SL in the display area DA of the conductive layer CL2 shown in FIG. For example, the arrangement pitch SLp3 of the detour wiring portion SLc3 is 9 μm.

In the case of the display device DSP2 shown in FIG. 18, which will be described later as a modified example, all the detour wiring portions SLc2 of the plurality of video signal lines SL are connected to the conductive layer CL2, and are conductive layers corresponding to the conductive layer CL3 shown in FIG. A detour wiring portion is not arranged in the layer. Even in this case, the increase in the frame area FRA can be suppressed by reducing the arrangement pitch SLp2 of the detour wiring portion SLc2. However, in the case of the display device DSP1, compared with the display device DSP2, the area of the frame region FRA can be further reduced.

FIG. 8 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions shown in FIGS. 6 and 7 are arranged. As shown in FIG. 6, in the case of the display device DSP1, the multiple detour wiring portions SLc2 are arranged on both sides of the transparent region TRA in the X direction. Similarly, the multiple detour wiring portions SLc3 shown in FIG. 7 are arranged on both sides of the transparent region TRA in the X direction. In other words, as shown in FIG. 8, the frame region FRA is arranged next to the transparent region TRA in the X direction, and includes a plurality of detour wiring portions SLc2 (see FIG. 6) and a plurality of detour wiring portions SLc3 (see FIG. 7). ) are arranged (first area) FRA1. In addition, the frame region FRA is arranged on the opposite side of the region FRA1 with the transparent region TRA interposed therebetween in the X direction, and other parts of the plurality of detour wiring portions SLc2 and the plurality of detour wiring portions SLc3 are arranged. It includes a region (second region) FRA2.

As shown in FIG. 8, when the detour wiring portions SLc2 (see FIG. 6) and SLc3 (see FIG. 7) are arranged on both sides of the transparent region TRA in the X direction, any one of the transparent regions TRA The area of the frame region FRA can be reduced compared to the case where the detour wiring is arranged only next to one of them.

Further, in the case of the display device DSP1, the number of the detour wiring portions SLc2 (see FIG. 6) arranged in the region FRA1 shown in FIG. 8 is equal to the number of the detour wiring portions SLc2 arranged in the region FRA2. Further, the number of detour wiring portions SLc3 (see FIG. 7) arranged in region FRA1 is equal to the number of detour wiring portions SLc3 arranged in region FRA2. In other words, the detour wiring portions SLc2 and SLc3 are arranged in a well-balanced manner on both sides of the transparent region TRA in the X direction. For example, in the example shown in FIG. 6, the number of detour wiring portions SLc2 arranged in the region FRA1 (see FIG. 8) and the number of detour wiring portions SLc2 arranged in the region FRA2 (see FIG. 8) are 18, respectively. one by one. In the example shown in FIG. 7, the number of detour wiring portions SLc3 arranged in the region FRA1 (see FIG. 8) and the number of detour wiring portions SLc3 arranged in the region FRA2 (see FIG. 8) are respectively nine. one by one. Note that the examples shown in FIGS. 6 and 7 show an example in which the number of video signal lines SL is small in consideration of the visibility of the drawings. Therefore, the number of video signal lines SL and the total number of detour wiring portions SLc2 and SLc3 may be modified in various ways other than the examples shown in FIGS. For example, as described above, when a total of 120 to 450 video signal lines SL are arranged in the frame region FRA, the number of detour wiring portions SLc2 arranged in the region FRA1 and the number of detour wiring portions SLc2 arranged in the region FRA2 The number of detour wiring portions SLc2 may be 40 to 150 each. In this case, the number of detour wiring portions SLc3 arranged in region FRA1 and the number of detour wiring portions SLc3 arranged in region FRA3 are 20 to 75, respectively.

By arranging the detour wiring portions SLc2 and SLc3 in a well-balanced manner, the shapes of the regions FRA1 and FRA2 are symmetrical with respect to the center line passing through the center of the transparent region TRA in the Y direction. In this case, since the area around the transparent area TRA can be efficiently used as an arrangement area for the detour wiring portions, compared to the case where the numbers of the detour wiring portions arranged in the regions FRA1 and FRA2 are greatly different. can reduce the area of the frame region FRA. When the total number of detour wiring portions is an even number, the number of detour wiring portions arranged in the region FRA1 and the region FRA2 can be the same as in the display device DSP1. However, if the total number of detour wiring portions is an odd number, the number of detour wiring portions arranged in one of the regions FRA1 and FRA2 may be one more.

Further, each of the plurality of detour wiring portions SLc2 (see FIG. 6) and the plurality of detour wiring portions SLc3 (see FIG. 7) arranged in the region FRA1 shown in FIG. Extend. The planar shape of the region FRA1 is a crescent shape. The width FRw1 of the area FRA1 changes according to the position in the Y direction, and is the largest at the position overlapping the first virtual line VL1 extending in the X direction from the center of the transparent area TRA. Similarly, each of the plurality of detour wiring portions SLc2 and the plurality of detour wiring portions SLc3 arranged in the region FRA2 extends in an arc shape along the outer edge of the transparent region TRA. The planar shape of region FRA2 is a crescent shape. The width FRw2 of the region FRA2 varies depending on the position in the Y direction, and is the largest at the position overlapping the first virtual line VL1 extending in the X direction from the center of the transparent region TRA. The width of the regions FRA1 and FRA2 is defined as the length in the direction orthogonal to the tangential direction of the detour wiring portion arranged on the innermost periphery of each region. Widths FRw1 and FRw2 gradually decrease as the distance from virtual line VL1 increases.

Further, as shown in FIG. 5, in the case of the display device DSP1, the detour wiring portions GLc are also provided for the plurality of scanning signal lines GL. Some of the plurality of scanning signal lines GL are arranged in the display area DA, and arranged in a plurality of extended wiring portions (scanning signal extended wiring portions) GLr extending in the X direction and the frame region FRA of the conductive layer CL1. , and a plurality of detour wiring portions GLc having both ends connected to the plurality of extended wiring portions GLr.

As described above, the number of scanning signal lines GL corresponding to one pixel PX (see FIG. 3) is smaller than the number of video signal lines SL. Therefore, when the shape of the frame region FRA is annular, the arrangement pitch GLp2 of the plurality of detour wiring portions GLc has a margin compared to the arrangement pitch SLp2 of the plurality of detour wiring portions SLc2 shown in FIG. However, when a plurality of detour wiring portions GLc are arranged in the frame region FRA, it is preferable to reduce the arrangement pitch GLp2. In the example shown in FIG. 5, the arrangement pitch GLp2 of the plurality of detour wiring portions GLc is smaller than the arrangement pitch GLp1 of the plurality of scanning signal lines GL in the display area DA. In the example shown in FIG. 5, the arrangement pitch GLp1 of the scanning signal lines GL in the Y direction is 54 μm. On the other hand, the arrangement pitch GLp2 of the detour wiring portions GLc of the scanning signal lines GL in the Y direction is 9 μm. In this case, since the width of the frame region FRA in the Y direction can be reduced, the area of the frame region FRA can be reduced as a result.

FIG. 9 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions shown in FIG. 5 are arranged. As shown in FIG. 5, in the case of the display device DSP1, the multiple detour wiring portions GLc are arranged on both sides of the transparent region TRA in the Y direction. In other words, as shown in FIG. 9, the frame area FRA is arranged next to the transparent area TRA in the Y direction, and is an area ( 3rd area) including FRA3. In addition, the frame area FRA is arranged on the opposite side of the area FRA3 with the transparent area TRA interposed therebetween in the Y direction, and is an area (fourth area) FRA4 in which other parts of the plurality of detour wiring portions GLc are arranged. including.

In the case of the display device DSP1, the number of detour wiring portions GLc (see FIG. 5) arranged in the region FRA3 shown in FIG. 9 and the number of detour wiring portions GLc arranged in the region FRA4 are equal to each other. In other words, the same number of detour wiring portions GLc are arranged in good balance on both sides of the transparent region TRA in the Y direction. For example, in the example shown in FIG. 5, the number of detour wiring portions GLc arranged in the region FRA3 (see FIG. 9) and the number of detour wiring portions GLc arranged in the region FRA4 (see FIG. 9) are respectively nine. one by one. Note that the example shown in FIG. 5 shows an example in which the number of scanning signal lines GL is small in consideration of the visibility of the drawing. Therefore, it goes without saying that there are various modifications other than the example shown in FIG. 5 for the number of scanning signal lines GL and the total number of detour wiring portions GLc. For example, as described above, when a total of 40 to 150 scanning signal lines GL are arranged in the frame region FRA, the number of detour wiring portions GLc arranged in the region FRA3 and the number of detour wiring portions GLc arranged in the region FRA4 The number of detour wiring portions GLc may be 20 to 75 in each case. Further, when the total number of detour wiring portions GLc is an odd number, the number of detour wiring portions arranged in one of the regions FRA3 and FRA4 may be increased by one.

Further, each of the plurality of detour wiring portions GLc (see FIG. 5) arranged in the region FRA3 shown in FIG. 9 extends in an arc shape along the outer edge of the transparent region TRA. The planar shape of the region FRA3 is a crescent shape. The width FRw3 of the region FRA3 varies depending on the position in the X direction, and is the largest at the position overlapping the second virtual line VL2 extending in the Y direction from the center of the transparent region TRA. Similarly, each of the multiple detour wiring portions GLc arranged in the region FRA4 extends in an arc shape along the outer edge of the transparent region TRA. The planar shape of region FRA4 is a crescent shape. The width FRw4 of the region FRA4 changes according to the position in the X direction, and is the largest at the position overlapping the second virtual line VL2 extending in the Y direction from the center of the transparent region TRA. The width of the regions FRA3 and FRA4 is defined as the length in the direction orthogonal to the tangential direction of the detour wiring portion arranged on the innermost periphery of each region. Widths FRw3 and FRw4 gradually decrease as the distance from virtual line VL2 increases.

As described with reference to FIG. 6, the plurality of video signal lines SL include a plurality of video signal lines SLR for transmitting video signals for a first color (for example, red), and a plurality of video signal lines SLR for transmitting a video signal for a second color (for example, for blue). ) to which video signals are transmitted, and a plurality of video signal lines SLG to which video signals for a third color (for example, green) are transmitted. In the case of the display device DSP1, the plurality of video signal lines SLR and the plurality of video signal lines SLB shown in FIG. is connected to a plurality of detour wiring portions SLc3 in the frame area FRA shown in FIG. When some of the plurality of video signal lines SL are connected to the detour wiring portion SLc3 of the conductive layer CL3 shown in FIG. 7 as in the display device DSP1, the video signal line SL connected to the detour wiring portion SLc3 are preferably unified to the same type of video signal line SL among the plurality of types of video signal lines SL. The detour wiring portion SLc2 and the detour wiring portion SLc3 have different values of wiring resistance, capacitive load, and the like. Therefore, when the video signal line SL for a specific color is connected to the detour wiring portion SLc3, when displaying an image in a raster format in which a color density is set for each pixel and an image is displayed, the video signal line SL is connected to the detour wiring part SLc3. For example, when only the video signal line SL for a specific color is connected to the detour wiring section SLc3, the signal intensity of the video signal supplied to the detour wiring section SLc3 can be adjusted.

FIG. 10 is an enlarged plan view showing a state in which the bypass wirings shown in FIGS. 6 and 7 are overlapped in the B portion shown in FIG. 11 is an enlarged plan view showing a state in which the detour wirings shown in FIGS. 5 and 6 are superimposed at the same position as in FIG. 10. FIG. FIG. 12 is an enlarged cross-sectional view taken along line AA shown in FIGS. 10 and 11. FIG. Although FIGS. 10 and 11 are plan views, dot patterns or hatching are added in order to make it easier to see the positional relationship in a plan view of detour wiring portions arranged in each conductive layer. Specifically, the wiring formed on the conductive layer CL2 shown in FIG. 12 is indicated by a dot pattern, and the wiring formed on the conductive layer CL1 and the conductive layer CL3 is hatched. Further, in the region where the detour wiring part SLc2 and the detour wiring part SLc3 overlap, the outline of the detour wiring part SLc2 is indicated by a dotted line.

As shown in FIG. 10, in the frame area FRA, the video signal line SLR and the video signal line SLB paired are arranged adjacent to each other. A video signal line SLG is arranged between. In a plan view, the arrangement pitch SLp3 of the multiple adjacent detour wiring portions SLc3 is larger than the arrangement pitch SLp2 of the multiple adjacent detour wiring portions SLc2. For example, the layout pitch SLp3 of the detour wiring portions SLc3 is 9 μm, and the layout pitch SLp2 of the detour wiring portions SLc2 in the frame region FRA is 4.5 μm.

As shown in FIG. 10, by arranging the detour wiring portion SLc3 between the detour wiring portions SLc2 adjacent to each other in plan view, variation in the capacitive load applied to each of the plurality of detour wiring portions SLc2 is reduced. can. In addition, the above layout can reduce variations in the capacitive load applied to each of the plurality of detour wiring portions SLc3.

As shown in FIG. 11, in the frame area FRA, the video signal line SLR and the video signal line SLB that form a pair are arranged adjacent to each other, and in a plan view, the video signal line SLR and the video signal line SLB that form a pair are arranged. and the scanning signal line GL is arranged between them. Further, in plan view, the arrangement pitch GLp2 of the plurality of adjacent detour wiring portions GLc is larger than the arrangement pitch SLp2 of the plurality of adjacent detour wiring portions SLc2.

As shown in FIG. 11, by arranging the detour wiring portion GLc between the detour wiring portions SLc2 adjacent to each other in plan view, variation in the capacitive load applied to each of the plurality of detour wiring portions SLc2 is reduced. can. In addition, with the layout described above, it is possible to reduce variations in the capacitive load applied to each of the plurality of detour wiring portions GLc.

As shown in FIG. 12, in a plan view, the plurality of detour wiring portions GLc of the scanning signal lines GL and the plurality of detour wiring portions SLc3 of the video signal lines SLG overlap. Although FIG. 12 is a cross-sectional view, the plurality of detour wiring portions GLc and the plurality of detour wiring portions SLc3 are overlapped with each other in a plan view by superimposing the lines AA shown in FIGS. 10 and 11 . It is clear that Further, as shown in FIG. 10 or FIG. 11, a plurality of detour wiring portions GLc of the scanning signal lines GL and a plurality of detour wiring portions SLc3 of the video signal lines SLG are arranged between pairs adjacent to each other in plan view. not. Therefore, as shown in FIGS. 10 and 11, a plurality of detour wirings are provided between pairs adjacent to each other (for example, between adjacent detour wiring portions SLc3 or between mutually adjacent scanning signal lines GL). There is a light transmissive region TLA extending along the extending direction of portion SLc2.

As shown in FIG. 12, light shielding metal wiring (conductive layer CL1, conductive layer CL2, and conductive layer CL3) are arranged at high density in the frame area FRA. Further, as will be described later with reference to FIG. 16, in the frame area FRA, the sealing material SLM may be arranged so as to overlap the light-shielding metal wiring. At this time, the sealing material SLM contains an ultraviolet curable resin. By irradiating the sealing material SLM with ultraviolet rays, the sealing material SLM is cured and the substrate 10 and the substrate 20 are bonded. Further, by curing the sealing material SLM arranged between the substrate 10 and the substrate 20, it is possible to prevent liquid crystal from entering the transparent area TRA from the display area DA. In this case, it is possible to prevent the transparency of the transparent region TRA from being hindered by the liquid crystal. When curing the sealing material SLM, which is an ultraviolet curable resin in the frame area FRA, it is necessary to irradiate the sealing material SLM with ultraviolet rays. In the frame region FRA, light-shielding metal wirings are arranged at a high density, and as shown in FIGS. 10 and 11, the frame region FRA is provided with a light-transmitting region TLA. For this reason, the ultraviolet rays pass through the area TLA and irradiate the sealing material SLM, so that the sealing material SLM can be cured. Further, as shown in FIGS. 10 and 11, since the plurality of areas TLA are continuously provided, the sealing material SLM is easily irradiated with ultraviolet rays.

The configurations shown in FIGS. 10 to 12 can also be expressed as follows. As shown in FIG. 12, the plurality of video signal lines SL include a plurality of video signal lines SLR through which video signals for a first color (for example, red) are transmitted, and a plurality of video signal lines SLR for transmitting video signals for a second color (for example, for blue). It includes a plurality of video signal lines SLB through which signals are transmitted, and a plurality of video signal lines SLG through which video signals for a third color (for example, green) are transmitted. As shown in FIG. 10, one video signal line SLR and one video signal line SLB are arranged between adjacent detour wiring portions GLc in plan view. Further, as shown in FIG. 12, the multiple detour wiring portions SLc3 overlap the multiple detour wiring portions GLc and are connected to the multiple video signal lines SLG.

In the above description, an example of curing the sealing material SLM shown in FIG. 16 with ultraviolet light has been described. However, the insulating film 14 and the insulating film 15 shown in FIG. 12 may contain an ultraviolet curable resin. The frame area FRA may overlap with the light shielding film BM shown in FIG. As shown in FIGS. 10 and 11, when a plurality of regions TLA are provided, ultraviolet rays can be irradiated from the substrate 10 side to reach the sealing material SLM shown in FIG. , the entire frame area FRA may overlap with the light shielding film BM shown in FIG.

Next, a connection structure between the extended wiring portion SLr of the video signal line SL shown in FIG. 6 and the detour wiring portion SLc3 shown in FIG. 7 will be described. 13 is an enlarged plan view of the periphery of a portion connecting the second conductive layer shown in FIG. 6 and the third conductive layer shown in FIG. 7. FIG. 14 is an enlarged plan view of a portion A in FIG. 13. FIG. 15 is an enlarged cross-sectional view taken along line AA of FIG. 14. FIG. 13 and 14 are plan views, the wiring formed on the conductive layer CL2 shown in FIG. 15 is indicated by a dot pattern, and the wiring formed on the conductive layer CL3 is hatched. 13 and 14, the outline of the scanning signal line GL formed in the conductive layer CL1 shown in FIG. 15 and the outline of the bottom surface CHb of the contact hole CH1 are indicated by two-dot chain lines. In FIG. 13, a contact area CTA in which a plurality of contact holes CH1 are arranged is hatched. In FIG. 14, the outline of the detour wiring part SLc2 is indicated by a dotted line in the region where the detour wiring part SLc2 and the detour wiring part SLc3 overlap. Also, the detour wiring portion GLc is indicated by a chain double-dashed line.

As shown in FIGS. 13 to 15, the frame region FRA is provided with a contact hole CH1 electrically connecting the conductive layer CL2 (see FIG. 15) and the conductive layer CL3 (see FIG. 15). As shown in FIG. 15, the contact hole CH1 is an opening penetrating the insulating film 14 . A portion of the extended wiring portion SLr of the video signal line SL is exposed from the insulating film 14 at the bottom surface CHb of the contact hole CH1. A metal pattern is formed on the exposed portion of extended wiring portion SLr from insulating film 14, and this metal pattern extends toward detour wiring portion SLc3 formed in conductive layer CL3. The extended wiring portion SLr formed in the conductive layer CL2 and the detour wiring portion SLc3 formed in the conductive layer CL3 are electrically connected via the contact hole CH1. As shown in FIG. 13, the frame area FRA has a contact area CTA in which a plurality of contact holes CH1 electrically connecting the conductive layers CL2 and CL3 are arranged along the X direction.

As shown in FIG. 14, a contact portion SLCP having a larger width (length in the Y direction) than the extended wiring portion SLr is connected to the tip of the extended wiring portion SLr of the video signal line SLG. Bottom surface CHb of contact hole CH1 is arranged in contact portion SLCP. From the viewpoint of improving connection reliability between the conductive layer CL2 (see FIG. 15) and the conductive layer CL3 (see FIG. 15), the area of the bottom surface CHb of the contact hole CH1 is preferably large. Therefore, the contact portion SLCP has a width wider than that of the extended wiring portion SLr. However, at locations where the conductor pattern formed on the conductive layer CL2 has a large area, the capacitive load caused by this conductor pattern increases. Therefore, as shown in FIG. 14, the bottom surfaces CHb of the plurality of contact holes CH1 are preferably formed at positions that do not overlap with the plurality of scanning signal lines GL in plan view. Thereby, the mutual capacitive load between the contact portion SLCP and the plurality of scanning signal lines GL can be reduced.

In order to reduce the mutual capacitive load between the contact portion SLCP and the plurality of scanning signal lines GL, as shown in FIG. 14, the entire contact portion SLCP of the video signal line SLG does not overlap the scanning signal line GL. is particularly preferred. However, the contact portions SLCP are formed in the frame region where the detour wiring portions GLc of the scanning signal lines GL are arranged at high density. Therefore, it may be difficult to dispose the entire contact portion SLCP of the video signal line SLG so as not to overlap the scanning signal line GL. Even in this case, if at least the bottom surface CHb of each of the plurality of contact holes CH1 is formed at a position that does not overlap with the plurality of scanning signal lines GL, mutual contact between the contact portion SLCP and the plurality of scanning signal lines GL is possible. can reduce the capacitive load of

In the example shown in FIG. 14, the separation distance GLs1 between the detour wiring portions GLc of the adjacent scanning signal lines GL is larger than the separation distance SLs1 between the detour wiring portions SLc2 of the adjacent video signal lines SL. In this way, by increasing the distance GLs1 between the detour wiring portions GLc of the adjacent scanning signal lines GL, the bottom faces CHb of the plurality of contact holes CH1 are formed at positions that do not overlap with the plurality of scanning signal lines GL. It becomes easier to realize a layout that Further, as described with reference to FIGS. 5 and 6, the number of scanning signal lines GL arranged in the frame area FRA is smaller than the number of video signal lines SL arranged in the frame area FRA. Therefore, when the shape of the frame region is annular, the layout pitch of the detour wiring portions SLc2 of the video signal lines SL is dominant as a factor that defines the area of the frame region FRA. Even if the separation distance GLs1 is large, it is possible to suppress an increase in the area of the frame region FRA.

FIG. 16 is an enlarged plan view showing the planar shape of the sealing material arranged in the frame area around the transparent area TRA shown in FIG. 17 is an enlarged cross-sectional view taken along line AA of FIG. 16. FIG. As shown in FIG. 16, the display device DSP1 is arranged in the frame area FRA so as to surround the transparent area TRA in plan view, and the substrate 10 (see FIG. 17) and the substrate 20 (see FIG. 17) are adhesively fixed. A seal SLM is provided. The sealing material SLM is made of the same material as the sealing material SLM arranged in the peripheral area PFA shown in FIGS. 1 and 2, and has the function of suppressing leakage of the liquid crystal layer LQ (see FIG. 17) to the outside of the display area DA. Prepare. In the example shown in FIG. 17, the substrate 10 and the substrate 20 exist in the transparent area TRA. (or the substrate 10 and the substrate 20) may be formed with an opening. Further, the ultraviolet curing of the sealing material SLM is as described above.

As shown in FIG. 16, when the sealing material SLM is arranged in the frame area FRA, application of the sealing material SLM is started from an arbitrary point (starting point) in the frame area FRA. The coating process of the sealing material SLM is continuously performed in a circle along the outer circumference of the transparent region TRA, and ends when the coating of the sealing material SLM returns to the starting point. In the case of the method of applying the sealing material SLM described above, the amount of the sealing material SLM applied increases at the position where the start point and the end point of the application process overlap. As a result, the width WSL1 of the sealing material SLM at the start point of the coating process becomes wider than the width WSL2 of the sealing material SLM at positions different from the start point and the end point. If the sealing material SLM leaks into the display area DA, it causes display defects, and if the sealing material SLM leaks into the transparent area TRA, it causes poor light transmission characteristics. Therefore, it is necessary to prevent the sealing material SLM from leaking out of the frame area FRA even at the start position of the coating process of the sealing material SLM.

In the case of the display device DSP1, the conductive layer CL2 is covered with the insulating film 14, and the conductive layer CL3 is formed on the insulating film 14 and covered with the insulating film 15, as shown in FIG. Further, as shown in FIG. 13, in the frame area FRA, a plurality of contact holes CH1 electrically connecting the conductive layer CL2 (see FIG. 15) and the conductive layer (see FIG. 15) are arranged along the X direction. There is a contact area CTA that is As shown in FIG. 17, between the contact area CTA and the display area DA, there is a stepped portion STP1 on which the conductive layer CL3 (see FIG. 15) and the insulating film 15 are not formed on the insulating film . The stepped portion STP1 has a concave shape from which the insulating film 15 is removed. When the application amount of the sealing material SLM is locally increased, the sealing material SLM may flow into the stepped portion STP1. However, in the stepped portion STP1, the separation distance between the alignment films AL1 and AL2 is larger than that in the display area DA. Therefore, even if the sealing material SLM spreads within the stepped portion STP1, the end thereof does not spread to the display area DA. That is, by forming the stepped portion STP1, it is possible to suppress leakage of the sealing material SLM into the display area DA or the transparent area TRA.

The stepped portion STP1 is formed by removing a portion of the insulating film 15 . In the case of the display device DSP1, since the conductor pattern of the conductive layer CL3 is formed within the frame area FRA as shown in FIG. 15, it is necessary to form the insulating film 15 within the frame area FRA. However, as shown in FIG. 17, the stepped portion STP1 can be formed by shifting the position of the contact region CTA toward the transparent region TRA.

Further, as shown in FIG. 13, in the frame area FRA, the plurality of video signal lines SL and the detour wiring portions GLc of the plurality of scanning signal lines GL intersect each other. In the step of forming the conductive layer CL1 and the conductive layer CL2 shown in FIG. 15, the conductive layer CL1 and the insulating film 13 are formed before forming the conductive layer CL2. In addition, since the insulating film 13 is thinner than the insulating film 14, which is an inorganic insulating film, the flatness of the surface of the insulating film 13 is lower than that of the insulating film 14. FIG. Therefore, the wiring width of the video signal lines SL is likely to be narrowed at the intersections where the plurality of video signal lines SL and the detour wiring portions GLc of the plurality of scanning signal lines GL intersect.

Therefore, in the case of the display device DSP1, measures are taken to suppress the reduction in signal transmission characteristics due to the thinning of the video signal lines SL at the intersections with the scanning signal lines GL. That is, the width SLw1 of the extended wiring portion SLr included in each of the plurality of video signal lines SL illustrated in FIG. 6 is larger than the width SLw2 of the plurality of detour wiring portions SLc2. As described above, in order to reduce the area of the frame region FRA, the arrangement pitch SLp2 of the detour wiring portions SLc2 is preferably as small as possible. By reducing the width SLw2 of the detour wiring portion SLc2, the arrangement pitch SLp2 can be reduced. In the example shown in FIG. 6, the width SLw2 of the detour wiring portion SLc2 is 2.1 μm, and the arrangement pitch SLp2 is 4.5 μm. On the other hand, the width SLw1 of the extended wiring portion SLr included in each of the plurality of video signal lines SL is 2.7 μm. As a result, it is possible to prevent the signal transmission reliability from deteriorating due to thinning of the video signal line SL at the intersection with the scanning signal line GL.

Note that the width SLw3 of the detour wiring portion SLc3 shown in FIG. 7 is 3.5 μm. The conductor pattern formed on the conductive layer CL3 (see FIG. 15) is made of a metal having a higher resistance than the conductor pattern formed on the conductive layer CL2 (see FIG. 15). Therefore, in the conductive layer CL3, the width SLw3 of the detour wiring portion SLc3 is made larger than the width SLw2 shown in FIG. 6, thereby reducing the wiring impedance difference between the detour wiring portion SLc3 and the detour wiring portion SLc2. can do. Also, the width GLw2 of the detour wiring portion GLc of the scanning signal line GL shown in FIG. 5 is the same as the width GLw1 of the scanning signal line GL in the display area DA. For example, in the example shown in FIG. 5, width GLw1 and width GLw2 are each 3 μm.

Further, as shown in FIG. 13, at the intersections where the plurality of video signal lines SL and the detour wiring portions GLc of the plurality of scanning signal lines GL intersect with each other, from the viewpoint of reducing the capacitive load due to the intersection, the video It is preferable that the area of the portion where the signal line SL and the scanning signal line GL overlap is small. From the viewpoint of reducing the area of the portion where the video signal line SL and the scanning signal line GL overlap, it is preferable that the angle at which the video signal line SL and the scanning signal line GL intersect is as close to a right angle as possible. In the case of the present embodiment, as shown in FIG. 13, in the frame area FRA, the acute angle formed at each of the plurality of intersections where the plurality of video signal lines SL and the plurality of detour wiring portions GLc intersect is 45°. The number of acute angles θ1 of angles greater than or equal to 45 degrees is greater than the number of acute angles less than 45 degrees. In the example shown in FIG. 13, there is no acute angle less than 45 degrees formed at the intersection where the video signal line SL and the detour wiring portion GLc intersect. The expression "the number of acute angles θ1 of 45 degrees or more is greater than the number of acute angles of less than 45 degrees" includes the case where there are no acute angles of less than 45 degrees. In addition, it goes without saying that the above expression includes the case where there is an acute angle of less than 45 degrees.

(Embodiment 2)
In the first embodiment described above, an embodiment has been described in which the area of the frame region FRA shown in FIG. 6 is reduced by forming the detour wiring portions of the video signal lines SL in a plurality of conductive layers. In the second embodiment, a description will be given of an embodiment in which the detour wiring portion of the video signal line SL is routed by one conductive layer. 18 is an enlarged plan view of the second conductive layer around the transparent region included in the display device which is a modification of FIG. 6. FIG.

In the display device DSP2 shown in FIG. 18, all detour wiring portions SLc2 of the video signal lines SL are arranged in the conductive layer CL2, which is the second conductive layer, and no wiring is formed in the conductive layer CL3 shown in FIG. It is different from the display device DSP1 shown in FIG. The arrangement pitch SLp1 of the video signal lines SL in the display area DA is 18 μm, which is the same as the example shown in FIG. Also, the arrangement pitch SLp2 of the detour wiring portions SLc2 in the frame region FRA is 4.5 μm as in the example shown in FIG. In the case of the display device DSP2, since the arrangement pitch SLp2 of the detour wiring portions SLc2 is smaller than the arrangement pitch SLp1 of the video signal lines SL in the display area DA, the area of the frame area FRA can be reduced.

19 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions shown in FIG. 18 are arranged; FIG. As shown in FIG. 19, in the case of the display device DSP2, the multiple detour wiring portions SLc2 are arranged on both sides of the transparent region TRA in the X direction. In other words, as shown in FIG. 19, the frame area FRA is arranged next to the transparent area TRA in the X direction, and is an area ( First region) includes FRA1. Further, the frame area FRA is arranged on the opposite side of the area FRA1 with the transparent area TRA interposed therebetween in the X direction, and is an area (second area) FRA2 in which the other part of each of the plurality of detour wiring portions SLc2 is arranged. including.

As shown in FIG. 19, when the detour wiring portions SLc2 (see FIG. 18) are arranged on both sides of the transparent region TRA in the X direction, the detour wiring portion SLc2 (see FIG. 18) is arranged only next to one of the transparent regions TRA in the X direction. The area of the frame region FRA can be reduced as compared with the case where wiring is arranged.

Further, each of the plurality of bypass wiring portions SLc2 (see FIG. 18) arranged in the region FRA1 shown in FIG. 19 extends in an arc shape along the outer edge of the transparent region TRA. The planar shape of the region FRA1 is a crescent shape. The width FRw1 of the area FRA1 changes according to the position in the Y direction, and is the largest at the position overlapping the first virtual line VL1 extending in the X direction from the center of the transparent area TRA. Similarly, each of the multiple detour wiring portions SLc2 arranged in the region FRA2 extends in an arc shape along the outer edge of the transparent region TRA. The planar shape of region FRA2 is a crescent shape. The width FRw2 of the region FRA2 varies depending on the position in the Y direction, and is the largest at the position overlapping the first virtual line VL1 extending in the X direction from the center of the transparent region TRA. The width of the regions FRA1 and FRA2 is defined as the length in the direction orthogonal to the tangential direction of the detour wiring portion arranged on the innermost periphery of each region. Widths FRw1 and FRw2 gradually decrease as the distance from virtual line VL1 increases.

FIG. 20 is an enlarged plan view schematically showing a region in which a plurality of detour wiring portions of the first conductive layer of the display device DSP2 shown in FIG. 18 are arranged. Similar to the display device DSP1 shown in FIG. 9, the frame region FRA included in the display device DSP2 shown in FIG. A region (third region) FRA3 in which a part of each is arranged is included. In addition, the frame area FRA is arranged on the opposite side of the area FRA3 with the transparent area TRA interposed therebetween in the Y direction, and is an area (fourth area) FRA4 in which other parts of the plurality of detour wiring portions GLc are arranged. including.

Further, as shown in FIG. 19, in a plan view, the outer edges (peripheral edges on the display area DA side) of the area FRA1 and the area FRA2 of the frame area FRA form a first ellipse ELP1 having two focal points along the X direction. placed along. Further, as shown in FIG. 20, in a plan view, the outer edges (peripheral parts on the side of the display area DA) of the areas FRA3 and FRA4 of the frame area FRA are along the second ellipse ELP2 having two focal points along the Y direction. are placed.

Further, as shown in FIGS. 19 and 20, the transparent area TRA is circular in plan view. In plan view, inner edges (peripheral edges on the side of the transparent area TRA) of the areas FRA1 and FRA2 of the frame area FRA shown in FIG. 19 are arranged along a circle concentric with the center of the transparent area TRA. Further, as shown in FIG. 20, in a plan view, the inner edges (peripheral edges on the side of the transparent area TRA) of the areas FRA3 and FRA4 of the frame area FRA are arranged along a circle that is concentric with the center of the transparent area TRA. be.

FIG. 21 is an enlarged sectional view showing a modified example with respect to FIG. In the case of the display device DSP2, the detour wiring portion is not arranged in the conductive layer CL3 as described above. Therefore, the layout of the video signal lines SL is different from that of the display device DSP1 described with reference to FIG. That is, as shown in FIG. 21, the plurality of video signal lines SL includes a plurality of video signal lines SLR for transmitting video signals for a first color (for example, red) and a plurality of video signal lines SLR for transmitting a video signal for a second color (for example, for blue). , and a plurality of video signal lines SLG through which video signals for a third color (for example, green) are transmitted. In plan view, one video signal line SLR, one video signal line SLG, and one video signal line SLB are arranged between adjacent detour wiring portions GLc.

Further, it is preferable that the video signal lines SLR, the video signal lines SLG, and the video signal lines SLB are arranged regularly. That is, in the example shown in FIG. 21, the detour wiring portion SLc2 of the video signal line SLR is arranged between the video signal line SLG and one of the detour wiring portions GLc, and the video signal line SLG and the other detour wiring portion GLc are arranged. A detour wiring portion SLc2 of the video signal line SLB is arranged between them. In this case, the capacitive load on each wiring of the video signal line SLR, the video signal line SLG, and the video signal line SLB can be made uniform for each color. As a result, display unevenness caused by a difference in capacitive load on the video signal line SL can be reduced when displaying an image in a raster format in which an image is displayed by setting the color density for each pixel.

The display device DSP2 is the same as the display device DSP1 shown in FIG. 1 except for the differences described above. Duplicate description is therefore omitted. However, some of the technical features of the display device DSP1 described with reference to FIGS. 1 to 17 may be applied to the display device DSP2.

Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications and modifications, and it is understood that these modifications and modifications also fall within the scope of the present invention. For example, additions, deletions, or design changes of components, or additions, omissions, or changes of conditions to the above-described embodiments by those skilled in the art are also subject to the gist of the present invention. is included in the scope of the present invention as long as it has

In addition, the following technical ideas are included in the description of the above-described embodiments.

[Appendix 1]
a display area;
a transparent area inside the display area in plan view;
a frame region surrounding the transparent region along the outer edge of the transparent region in plan view and between the display region and the transparent region;
a first substrate comprising
a plurality of scanning signal lines formed in a first conductive layer on the first substrate in the display region and extending in a first direction;
a plurality of video signal lines formed on a second conductive layer on the first substrate in the display area and extending in a second direction crossing the first direction;
has
Some of the plurality of scanning signal lines are arranged in the display area and extend in the first direction, and a plurality of first elongated wirings are arranged in the frame area and both ends of the plurality of first elongated wirings are arranged. and a plurality of first bypass wirings connected to
Some of the plurality of video signal lines are arranged in the display area and extend in the second direction, and a plurality of second elongated wirings are arranged in the frame area and both ends of the plurality of second elongated wirings are arranged. and a plurality of second bypass wirings connected to
an arrangement pitch of the plurality of first detour wirings is smaller than an arrangement pitch of the plurality of first extended wirings;
an arrangement pitch of the plurality of second detour wirings is smaller than an arrangement pitch of the plurality of second extended wirings;
The frame area is
a first region arranged next to the transparent region in the first direction and in which a part of each of the plurality of second detour wirings is arranged;
a second region disposed on the opposite side of the first region with the transparent region interposed therebetween in the first direction, and in which another part of each of the plurality of second detour wirings is disposed;
a third region arranged next to the transparent region in the second direction and in which a part of each of the plurality of first detour wirings is arranged;
a fourth region arranged on the opposite side of the third region with the transparent region interposed therebetween in the second direction, and in which another part of each of the plurality of first detour wirings is arranged;
a display device.

[Appendix 2]
In Appendix 1,
In a plan view, outer edges (peripheral edges on the display area side) of the first area and the second area of the frame area are arranged along a first ellipse having two focal points along the first direction,
In plan view, outer edges (peripheral edges on the display area side) of the third area and the fourth area of the frame area are arranged along a second ellipse having two focal points along the second direction. , display device.

[Appendix 3]
In Appendix 2,
In plan view, the transparent region is circular,
In plan view, inner edges (peripheral edges on the side of the transparent area) of the first area and the second area of the frame area are arranged along a first circle that is concentric with the center of the transparent area,
In a plan view, the inner edges (peripheral edges on the side of the transparent area) of the third area and the fourth area of the frame area are arranged along a second circle that is concentric with the center of the transparent area. .

[Appendix 4]
In Appendix 1,
The plurality of video signal lines include a plurality of first video signal lines through which video signals for a first color are transmitted, a plurality of second video signal lines through which video signals for a second color are transmitted, and a third video signal line. and a plurality of third video signal lines through which color video signals are transmitted,
The display device, wherein one each of the first video signal line, the second video signal line, and the third video signal line is arranged between the adjacent first detour wirings in plan view.

INDUSTRIAL APPLICABILITY The present invention can be used for display devices.

10, 20 substrates 10f, 20f front surface (surface, main surface)
20b Back (surface, main surface)
11-16 Insulating films AL1, AL2 Alignment film CH1 Contact hole CHb Bottom surface CL1, CL2, CL3, CL4, CL5 Conductive layer CTA Contact area DA Display area DSP1, DSP2 Display device FRA Frame area GL Scanning signal lines GLc, SLc2, SLc3 Detour Wiring part (detour wiring)
GLr, SLr extended wiring part (extended wiring)
GLs1, SLs1 Spacing distances GLp1, GLp2, SLp1, SLp2, SLp3 Arrangement pitches GLw1, GLw2, SLw1, SLw2, SLw3 Width LQ Liquid crystal layer SL, SLB, SLG, SLR Video signal line SLCP Contact portion SLM Sealing material (adhesive material)
STP1 Stepped portion TRA Transparent area

Claims (11)

a first substrate having a display area;
a transparent area inside the display area in plan view;
a frame region surrounding the transparent region along the outer edge of the transparent region in plan view and between the display region and the transparent region;
a plurality of scanning signal lines formed of a first conductive layer on the first substrate in the display area and extending in a first direction;
a plurality of video signal lines formed of a second conductive layer on the first substrate in the display area and extending in a second direction crossing the first direction;
has
Some of the plurality of video signal lines are arranged in the display area, and a plurality of extended wirings extending in the second direction are arranged in the frame area, and both ends thereof are connected to the plurality of extended wirings. a plurality of detour wires; and
The plurality of detour wirings of the plurality of video signal lines comprise a plurality of first portions arranged on the second conductive layer and a plurality of second portions arranged on a conductive layer different from the second conductive layer. , including
the arrangement pitch of the plurality of first portions and the arrangement pitch of the plurality of second portions are each smaller than the arrangement pitch of the plurality of video signal lines in the display area;
The plurality of video signal lines include a plurality of first video signal lines through which video signals for a first color are transmitted, a plurality of second video signal lines through which video signals for a second color are transmitted, and a third video signal line. and a plurality of third video signal lines through which color video signals are transmitted,
the plurality of first video signal lines and the plurality of second video signal lines are connected to the plurality of first portions in the frame region;
the plurality of third video signal lines are connected to the plurality of second portions in the frame area;
In the frame region, the pair of the first video signal line and the second video signal line are arranged adjacent to each other, and in a plan view, the pair of the first video signal line and the second video. The third video signal line is arranged between the signal line,
The display device, wherein the arrangement pitch of the plurality of second portions adjacent to each other is larger than the arrangement pitch of the plurality of first portions adjacent to each other in plan view. In claim 1,
Some of the plurality of scanning signal lines are arranged in the display region, and a plurality of scanning signal extended wirings extending in the first direction are arranged in the frame region of the first conductive layer. a plurality of third portions connected to the plurality of scanning signal extended wirings,
The display device, wherein the arrangement pitch of the plurality of third portions is smaller than the arrangement pitch of the plurality of scanning signal lines in the display area. In claim 2 ,
In the frame region, the first video signal line and the second video signal line that form the pair are arranged adjacent to each other, and in plan view, the first video signal line that forms the pair and the second video signal line are arranged to be adjacent to each other. The scanning signal line is arranged between the video signal line,
The display device, wherein the arrangement pitch of the plurality of third portions adjacent to each other is larger than the arrangement pitch of the plurality of first portions adjacent to each other in plan view. In claim 1 ,
a second substrate provided with the display area and the frame area and arranged opposite to the first substrate;
a sealing material disposed in the frame area so as to surround the transparent area in a plan view and adhesively fixing the first substrate and the second substrate;
further comprising
The display device, wherein the frame region includes a contact region in which a plurality of contact holes electrically connecting the second conductive layer and the plurality of second portions are arranged along the first direction. In claim 2,
A display device, wherein at least one of the plurality of first portions overlaps some of the plurality of third portions. In claim 2,
The display device, wherein the plurality of second portions are formed on a third conductive layer different from the first conductive layer and the second conductive layer. In claim 6 ,
further comprising a first organic insulating film having a top surface and a bottom surface and formed in the frame region;
the second conductive layer is in contact with the bottom surface of the first organic insulating film;
The display device, wherein the third conductive layer is in contact with the upper surface of the first organic insulating film. In claim 7 ,
The display device, wherein the plurality of second portions formed in the third conductive layer are covered with a second organic insulating film in the frame region. In claim 5 ,
the plurality of first portions are covered with a first organic insulating film in the frame region;
The display device, wherein the plurality of second portions are covered with a second organic insulating film in the frame region. In claim 9 ,
The display device, wherein the plurality of third portions are covered with an inorganic insulating film in the frame region. In claim 10 ,
the plurality of first portions are between the inorganic insulating film and the first organic insulating film;
The display device, wherein the plurality of second portions are between the first organic insulating film and the second organic insulating film.

Images