JP2000105390A - Display panel and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of production stages by decreasing the number of times of forming photoresist films of a liquid crystal display device of an active matrix system having thin-film transistors (TFTs). SOLUTION: This display panel is constituted by forming gate electrodes G on a glass substrate 1, depositing a gate insulating film 31 and a semiconductor film 34 consisting of amorphous silicon, forming a blocking layer 32 on the semiconductor film 34, forming drain electrodes D and source electrodes S consisting of an n+ silicon film 54 as the lowermost layer, removing the unnecessary portions of the deposited semiconductor film 34, depositing an over-coating film 41, forming contact holes 61 in the over-coating film 41 and connecting pixel electrodes 7 via these contact holes 61 to the source electrodes S on the over-coating film 41. In such a case, the photoresist films are formed five times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel such as a liquid crystal display panel and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, when an active matrix type liquid crystal display panel is manufactured, in order to improve productivity, a transparent substrate made of glass or the like serving as a base of the liquid crystal display panel is divided into a plurality of liquid crystal display panels. There is a case where a product of a corresponding size is prepared, and a plurality of components are manufactured at a time until a predetermined process is performed. In the case of manufacturing a liquid crystal display panel including a thin film transistor as a switching element, for example, static electricity generated when rubbing the alignment film before dividing into individual pieces, for example, static electricity after dividing into individual pieces, etc. Contact with other high-voltage objects may cause dielectric breakdown of the thin film transistor or change the voltage-current characteristics of the thin film transistor. It is carried out.

FIG. 9 is a plan view of an equivalent circuit in a state where pixel electrodes and the like are formed on a glass substrate having a size corresponding to a plurality of liquid crystal display panels. The glass substrate 1 having a size corresponding to a plurality of liquid crystal display panels is finally cut along a cut line 2 indicated by a dashed line, thereby being divided into individual units. In this case, an area surrounded by the cut line 2 is a panel formation area 3, and the surrounding area is a surplus area 4. Further, a region surrounded by a two-dot chain line in the panel forming region 3 is a display region 5, and the outside thereof is a non-display region 6.

In the display area 5, a plurality of pixel electrodes 7 arranged in a matrix, a plurality of thin film transistors 8 respectively connected to the pixel electrodes 7, and a plurality of thin film transistors 8 are arranged in a row direction. And a plurality of data lines 10 arranged in the column direction and supplying a data signal to the thin film transistor 8.
A plurality of auxiliary capacitance lines 11 arranged in the row direction and forming an auxiliary capacitance portion Cs with the pixel electrode 7; a protection ring 12 disposed around the plurality of pixel electrodes 7; A plurality of scan line side protection elements 13 each including two protection thin film transistors interposed between the protection ring 12 and each scan line 9 on the outside.
And a plurality of data line-side protection elements 14 each including two protective thin film transistors interposed between the protection ring 12 and each data line 10 outside the protection ring 12. In the surplus area 4, short lines 15 are provided in a lattice pattern.

[0005] The left end of each scanning line 9 is connected to the short line 15 via an output-side connection pad 17 provided in a semiconductor chip mounting area 16 indicated by a dotted line of the non-display area 6. The upper end of each data line 10 is in the semiconductor chip mounting area 1 indicated by a dotted line of the non-display area 6.
It is connected to the short line 15 via a connection pad 19 on the output side provided in 8. Input-side connection pads 20 provided in the semiconductor chip mounting regions 16 and 18;
Reference numeral 21 is connected to an external connection terminal 22 provided at a predetermined position in the non-display area 6 via a wiring 23. The external connection terminal 22 is connected to the short line 15.

The right end of each auxiliary capacitance line 11 is connected to the short line 15 via a common line 24 and a connection pad 25 arranged outside the right side of the protection ring 12. Note that the common line 24 may be connected to the protection ring 12 in some cases. The gate electrode G and the source electrode S of the upper protection thin film transistor of the scanning line side protection element 13 are both connected to the scanning line 9, and the drain electrode D is connected to the protection ring 12. The gate electrode G and the source electrode S of the lower protective thin film transistor of the scanning line side protection element 13 are both connected to the protection ring 12, and the drain electrode D is connected to the scanning line 9. The gate electrode G and the source electrode S of the protection thin film transistor on the left side of the data line side protection element 14 are both connected to the protection ring 12, and the drain electrode D is connected to the data line 10. The gate electrode G and the source electrode S of the protection thin film transistor on the right side of the data line side protection element 14 are both connected to the data line 10, and the drain electrode D is connected to the protection ring 12.

Next, a specific structure of a part of the liquid crystal display panel will be described with reference to FIG. However, in this case, the manufacturing method will be described with reference to the manufacturing process shown in FIG. First, the metal film forming process P shown in FIG.
In FIG. 1, an Al-based metal film made of Al (aluminum), an Al alloy, or the like is formed on the upper surface of the glass substrate 1, and then, in a first photoresist forming step P2 of FIG. Then, in a scan line etc. forming step P3 in FIG. 11, the Al-based metal film is etched using the first photoresist film as a mask. Then, on the upper surface of the glass substrate 1,
The gate electrode G of the thin film transistor 8, the scanning line 9, the auxiliary capacitance line 11, a part 12a of the protection ring 12 (in this case, an upper side and a lower side of the protection ring 12 shown in FIG. 9), a connection pad 17a, and an external connection terminal 22a. , Wiring 2
3 is formed. The short line 1 shown in FIG.
5, common lines 24, connection pads 25 and the like are formed.
Note that the formation of the protective thin film transistors of the protection elements 13 and 14 is almost the same as the formation of the thin film transistor 7, and thus the description thereof is omitted. Thereafter, the first photoresist film is stripped.

Next, in a three-layer film forming step P4 in FIG. 11, a gate insulating film 31, a semiconductor film made of amorphous silicon, and a blocking layer forming layer made of silicon nitride are successively formed. In a second photoresist forming step P5, a second photoresist film is formed, and then, in a blocking layer forming step P6 of FIG. 11, the blocking layer forming layer is etched using the second photoresist film as a mask. Then, since the semiconductor film of the intermediate layer among the three layers remains formed, the semiconductor film (3) on the gate electrode G of the thin film transistor 8 is formed.
The blocking layer 32 is formed on the upper surface of 4). Also,
A blocking layer 33 is formed on the upper surface of the semiconductor film (37) in the intersection region between the two lines 9 and 10. After this, the second
Is peeled off.

Next, an n ⁺ silicon film forming step P7 shown in FIG.
, An n ⁺ silicon film is formed, then, in a third photoresist forming step P8 of FIG. 11, a third photoresist film is formed, and then, in a device area forming step P9 of FIG. The n ⁺ silicon film and the semiconductor film are etched using the resist film as a mask. Then, in the formation region of the thin film transistor 8 and the like, the semiconductor film 3 is formed at a predetermined position on the upper surface of the gate insulating film 31.
4 are formed, and a drain side n ⁺ silicon film 35 and a source side n ⁺ silicon film 36 are formed on both sides of the upper surface of the blocking layer 32 and both sides of the upper surface of the semiconductor film 34.
In a region where the lines 9 and 10 intersect, a semiconductor film 37 is formed below the blocking layer 33. Thereafter, the third photoresist film is stripped.

Next, in an ITO film forming step P10 of FIG. 11, an ITO film is formed, and then, in a fourth photoresist forming step P11 of FIG. 11, a fourth photoresist film is formed. Pixel electrode forming process P12
In the IT using the fourth photoresist film as a mask
Etch the O film. Then, in the formation region of the thin film transistor 8 and the like, the pixel electrode 7 is formed at a predetermined position on the upper surface of the gate insulating film 31 by being connected to the source side n ⁺ silicon film 36. Thereafter, the fourth photoresist film is stripped.

Next, in a fifth photoresist forming step P13 of FIG. 11, a fifth photoresist film is formed. Then, in a contact hole forming step P14 of FIG. 11, the gate is formed using the fifth photoresist film as a mask. A contact hole is formed in each predetermined portion of the insulating film 31. That is, for example, in the connection region of the protection ring 12, the contact holes 38 are formed in the gate insulating film 31 at portions corresponding to both ends of the protection ring 12a. In the connection pad 17 formation region, a contact hole 39 is formed in the gate insulating film 31 in a portion corresponding to the connection pad 17. Further, in a region where the external connection terminal 22 is formed, a contact hole 40 is formed in the gate insulating film 31 in a portion corresponding to the external connection terminal 22.
To form Thereafter, the fifth photoresist film is stripped.

Next, in a three-layer film forming step P15 of FIG. 11, a Cr (chromium) film, an Al-based metal film, and a Cr film are successively formed, and then a sixth photoresist forming step P16 of FIG. Forming a sixth photoresist film,
Next, in a data line etc. forming step P17 in FIG. 11, the three layers in this case are sequentially etched using the sixth photoresist film as a mask, then the sixth photoresist film is removed, and then the upper Cr film in FIG. 11 is removed. Process P18
Then, the upper Cr film is peeled off. Then, the Cr film 10
A data line 10 composed of two layers of a and an Al-based metal film 10b is formed. In the region where the thin film transistor 8 and the like are formed, a drain electrode D composed of two layers of a Cr film and an Al-based metal film is formed on the upper surface of the drain-side n ⁺ silicon film 35.
Is formed, and a source electrode S composed of two layers of a Cr film and an Al-based metal film is formed on the upper surface of the source side n ⁺ silicon film 36. Also, the remaining portion 12 of the protection ring 12
b, that is, the left side and right side of the protection ring 12 shown in FIG. 9 are formed of two layers of a Cr film and an Al-based metal film. In this case, in the protection ring 12 connection region, both ends of the protection ring 12b are connected to both ends of the protection ring 12a via the contact holes 38, respectively. In the connection pad 17 formation region, a Cr film and an Al-based metal film are formed at predetermined positions on the upper surface of the gate insulating film 31.
A connection pad 17b made of a layer is formed to be connected to the connection pad 17a via the contact hole 39. In the region where the connection pad 19 is formed, a Cr film and an Al-based metal film are formed at predetermined positions on the upper surface of the gate insulating film 31.
A connection pad 19 made of a layer is formed. Further, in the external connection terminal 22 formation region, an external connection terminal 22 b composed of two layers of a Cr film and an Al-based metal film is provided at a predetermined location on the upper surface of the gate insulating film 31 to the external connection terminal 22 a via the contact hole 40. Connected and formed.

Next, an overcoat film forming process P shown in FIG.
In 19, an overcoat film 41 made of silicon nitride is formed, and then in a seventh photoresist forming step P20 of FIG. 11, a seventh photoresist film is formed, and then in an opening forming step P21 of FIG. An opening is formed at each predetermined location of the overcoat film 41 using the seventh photoresist film as a mask. That is, for example, in the connection pad 17 formation region, the opening 42 is formed in the overcoat film 41 in a portion corresponding to the connection pad 17b. In the connection pad 19 forming region, an opening 43 is formed in the overcoat film 41 at a portion corresponding to the connection pad 19. In the area where the external connection terminals 22 are formed, the external connection terminals 22
An opening 44 is formed in the overcoat film 41 in a portion corresponding to b. Further, in the formation region of the thin film transistor 8 and the like, an opening 45 is formed in the overcoat film 41 at a portion corresponding to a predetermined portion of the pixel electrode 7. Thereafter, the seventh photoresist film is stripped. Thus, the liquid crystal display panel shown in FIG. 9 is obtained.

Here, a description will be given of a case where static electricity is generated when the alignment film is rubbed, for example, before cutting along the cut line 2 in manufacturing the liquid crystal display panel. In this case, all the wirings in the panel formation region 3 are short lines 1 in the surplus region 4.
Since the short line 15 is connected to the ground 5, the generated static electricity can be quickly removed if the short line 15 is grounded. Next, a brief description will be given of a case where the liquid crystal display panel is cut along the cut line 2 and then comes into contact with another object charged with static electricity, for example, in manufacturing the liquid crystal display panel. In this case, the protection ring 12, the scanning lines 9 and all the data lines 10 have the same potential by appropriately turning on the protection thin film transistors of the protection elements 13 and 14. The protective thin film transistors of the protection elements 13 and 14 do not adversely affect the normal display driving of the liquid crystal display device including the liquid crystal display panel.

[0015]

In the above-mentioned conventional method for manufacturing a liquid crystal display panel, as shown in FIG. 11, the first to seventh photoresist forming steps are performed to form each thin film. Since the mask is formed seven times, there is a problem that the number of manufacturing steps is large. Moreover, since the connection pads 17 and 19 and the external connection terminals 22 are exposed from the openings 42, 43 and 44 of the overcoat film 41 and are easily oxidized, it is necessary to form a metal which is hardly oxidized such as ITO thereon. However, this requires a further mask. An object of the present invention is to reduce the number of times of forming a photoresist mask to reduce the number of manufacturing steps.

[0016]

According to a first aspect of the present invention, there is provided a display panel comprising: a plurality of pixel electrodes arranged in a matrix; a plurality of switching elements respectively connected to the pixel electrodes; And a plurality of scanning lines that supply a scanning signal to the switching element, a plurality of data lines that are arranged in a column direction and supply a data signal to the switching element, and that are arranged around the plurality of pixel electrodes. And a protection ring interrupted on the way, a plurality of scan line side protection elements interposed between the protection ring and each of the scanning lines, and a protection ring interposed between the protection ring and each of the data lines. A plurality of data line-side protection elements, wherein each of the elements except for the pixel electrode is covered with an overcoat film. A jumper line for providing the pixel electrode and connecting a blocking portion of the protection ring, or a top layer of a connection pad connected to the data line is provided, and at least one of the jumper line or the top layer of the connection pad is provided. It is characterized by being formed of the same material as the pixel electrode. The method of manufacturing a display panel according to claim 4, wherein the plurality of pixel electrodes arranged in a matrix, the plurality of switching elements respectively connected to the pixel electrodes, and the plurality of switching elements arranged in a row direction are provided. A plurality of scanning lines for supplying a scanning signal to the element, and a plurality of data lines arranged in the column direction and supplying a data signal to the switching element,
A protection ring disposed around the plurality of pixel electrodes and interrupted on the way, a plurality of scan line side protection elements interposed between the protection ring and each of the scan lines, the protection ring and the protection ring; When manufacturing a display panel including a plurality of data line-side protection elements interposed between the respective data lines and predetermined wirings arranged in a non-display area, the pixel among the elements on the substrate Elements other than the electrodes are formed, these elements are covered with an overcoat film, and the pixel electrodes are formed on the overcoat film and connected to jumper lines connecting the blocking portions of the protection ring or to the data lines. And forming at least one of the jumper line and the uppermost layer of the connection pad with the same material as the pixel electrode at the same time. In which it was to be formed. According to the first or fourth aspect of the present invention, since the pixel electrode and the jumper line connecting the blocking portion of the protection ring are formed of the same material on the overcoat film, the jumper line is formed of the same material as the pixel electrode. The material can be formed simultaneously with the formation of the pixel electrode, and accordingly, the number of manufacturing steps can be reduced by an amount corresponding to the formation. In the method of manufacturing a display panel according to the present invention, a gate electrode, a gate insulating film, a semiconductor film, a data line, a source electrode, and a drain electrode are formed on a substrate, and these elements are covered with an overcoat film. Forming a contact hole penetrating the overcoat film and a contact hole penetrating the overcoat film and the gate insulating film at predetermined locations using one photoresist film; Forming a pixel electrode on the film by connecting to the source electrode through the contact hole. Therefore, according to the seventh aspect of the present invention, the step of forming the contact hole in the overcoat film and the step of forming the pixel electrode can simultaneously form the pixel electrode, the jumper line of the protection ring, and the uppermost layer of the connection pad. Thus, the number of manufacturing steps can be reduced.

[0017]

FIG. 1 shows a manufacturing process of a liquid crystal display panel according to an embodiment of the present invention, and FIGS. 2 to 7 are sectional views showing respective manufacturing processes. For convenience of description, in FIGS. 2 to 7, components having the same names as those in FIGS. 9 and 10 are denoted by the same reference numerals. FIG. 8 is a plan view of an equivalent circuit similar to FIG. 9 in this embodiment.

When manufacturing a liquid crystal display panel in this embodiment, first, in the metal film forming step S1 in FIG. 1, an Al or Al alloy
First, a first photoresist film is formed on the upper surface of the Al-based metal film in a first photoresist forming step S2 of FIG. 1, and then in a first photoresist forming step S3 of FIG. Then, the Al-based metal film is etched using the first photoresist film as a mask. Then, as shown in FIG. 2, on the upper surface of the glass substrate 1, the gate electrode G of the thin film transistor 8, the scanning line 9, and the auxiliary capacitance line 1
1. A part 12a of the protection ring 12 (in this case, an upper side, a lower side, and a right side of the protection ring 12 shown in FIG. 8), a connection pad 17, an external connection terminal 22, and a wiring 23 are formed. Further, a short line 15, a common line 24, a connection pad 25, and the like shown in FIG. 8 are formed. Note that the formation of the protective thin film transistors of the protection elements 13 and 14 is almost the same as the formation of the thin film transistor 7, and thus the description thereof is omitted. Thereafter, the first photoresist film is stripped.

Next, in the three-layer film forming step S4 of FIG.
As shown in FIG. 2, a gate insulating film 31 made of silicon nitride, a semiconductor film 51 made of amorphous silicon, and a blocking layer forming layer 52 made of silicon nitride are successively formed. Next, in a second photoresist forming step S5 of FIG. 1, a second photoresist film is applied on the upper surface of the blocking layer forming layer 52, and then exposed using the gate electrode G or the like as a mask from the back surface. Exposure is performed from the front side using a photomask (not shown), and then development is performed. Then, as shown in FIG. 2, a second photoresist film 53a is formed on the upper surface of the blocking layer forming layer 52 on the gate electrode G of the thin film transistor 8. Further, a second photoresist film 53b is formed on the upper surface of the blocking layer forming layer 52 in the intersection region of both lines 9, 10.

Next, the blocking layer forming step S6 of FIG.
Then, the blocking layer forming layer 52 is etched using the second photoresist films 53a and 53b as a mask. Then, as shown in FIG. 3, the blocking layers 32 and 33 are formed below the second photoresist films 53a and 53b, respectively. Thereafter, a second photoresist film 53a,
53b is peeled off.

Next, in an n ⁺ silicon film forming step S7 of FIG. 1, an n ⁺ silicon film 54 is formed as shown in FIG. Next, in the three-layer film forming step S8 in FIG. 1, as shown in FIG. 4, the Cr film 55, the Al-based metal film 56, and the Cr film 5
7 is continuously formed. In this case, a Cr silicide film 58 is formed at the interface between the lower Cr film 55 and the n ⁺ silicon film 54. Next, in a third photoresist forming step S9 of FIG. 1, as shown in FIG.
A third photoresist film 59a at each predetermined location on the upper surface of the substrate.
To 59d. In this case, the third photoresist films 59a and 59b are for forming the drain electrode D and the source electrode S of the thin film transistor 8, and the like.
The third photoresist film 59c is for forming the data lines 10 and the connection pads 19. The third photoresist film 59d is for forming the remaining portion of the protection ring 12, that is, the left side portion of the protection ring 12 shown in FIG. Next, in a data line etc. forming step S10 of FIG.
Using the 59d as a mask, the Cr film 57, the Al-based metal film 56,
The Cr film 55 is etched, and then, in a device area forming step S11 of FIG.
9a to 59d as a mask, a Cr silicide film 58, n
^{+ The} silicon film 54 and the semiconductor film 51 are etched.

Then, as shown in FIG. 5, the data line 10 and the connection pad 19 are formed. In this case, the data line 10 and the connection pad 19 are sequentially formed from the bottom in the order of the semiconductor film 51, the n ⁺ silicon film 54, the Cr silicide film 5,
8, a Cr film 55, an Al-based metal film 56, and a Cr film 57 have a six-layer structure. In the region where the thin film transistor 8 and the like are formed, the semiconductor film 34 is formed at a predetermined position on the upper surface of the gate insulating film 31, and the drain electrode D and the source electrode are formed on both upper surfaces of the blocking layer 32 and both upper surfaces of the semiconductor film 34. S is formed. In this case, the drain electrode D
And the source electrode S are, in order from the bottom, an n ⁺ silicon film 5.
4, a five-layer structure of a Cr silicide film 58, a Cr film 55, an Al-based metal film 56, and a Cr film 57. Further, the remaining portion 12b of the protection ring 12, that is, the left side portion of the protection ring 12 shown in FIG. 8 is formed. In this case, the protection ring 1
The remaining portions 12b of the semiconductor film 51,
n ⁺ silicon film 54, Cr silicide film 58, Cr film 5
5, a six-layer structure of an Al-based metal film 56 and a Cr film 57.
Thereafter, the third photoresist films 59a to 59d are peeled off.

Next, the overcoat film forming step S1 shown in FIG.
2, an overcoat film 4 made of silicon nitride
1 (see FIG. 6), and then, in a fourth photoresist forming step S13 in FIG. 1, the overcoat film 41 is formed.
A fourth photoresist film (not shown) is formed on the upper surface of the substrate. Then, in a contact hole forming step S14 in FIG. 1, each of the overcoat film 41 and the gate insulating film 31 is formed using the fourth photoresist film as a mask. A contact hole is formed at the location. That is, as shown in FIG. 6, in the region where the thin film transistor 8 and the like are formed, the contact hole 61 is formed in the overcoat film 41 in the portion corresponding to the source electrode S. In addition, protection ring 1
In the two connection region, a contact hole 62 that penetrates the overcoat film 41 and the gate insulating film 31 is formed in the overcoat film 41 and the gate insulating film 31 in a portion corresponding to a predetermined portion of the protective ring 12a, and A contact hole 63 is formed in the overcoat film 41 at a portion corresponding to a predetermined portion of 12b. In the connection pad 19 formation region, a contact hole 64 is formed in the overcoat film 41 in a portion corresponding to the connection pad 19. In the region where the connection pad 17 is to be formed, a contact hole 65 is formed in the overcoat film 41 and the gate insulating film 31 in a portion corresponding to the connection pad 17 so as to penetrate the overcoat film 41 and the gate insulating film 31. Further, in the region where the external connection terminal 22 is formed, the overcoat film 41 and the gate insulating film 3
1 is formed. Thereafter, the fourth photoresist film is stripped.

Next, in an ITO film forming step S15 of FIG. 1, an ITO film (not shown) is formed, and then the fifth step of FIG.
In a photoresist forming step S16, a fifth photoresist film (not shown) is formed on the upper surface of the ITO film,
Next, in a pixel electrode etc. forming step S17 of FIG.
Using the photoresist film as a mask, the ITO film is dry-etched for a reason described later. Then, as shown in FIG. 7, in the formation region of the thin film transistor 8 and the like, the pixel electrode 7 is formed at a predetermined position on the upper surface of the overcoat film 41 by being connected to the source electrode S via the contact hole 61. In the connection region of the protection ring 12, ITO is provided at a predetermined position on the upper surface of the overcoat film 41.
A jumper line 67 made of a film is formed (see FIG. 8).
In this case, one end of the jumper wire 67 is connected to the protection ring 12a via the contact hole 62, and the other end is connected to the protection ring 12b via the contact hole 63. In the connection pad 19 formation region, a connection pad 19 a made of an ITO film is formed at a predetermined position on the upper surface of the overcoat film 41 so as to be connected to the connection pad 19 via the contact hole 64. Further, wiring 2
In the third formation region, a protective film 68 is formed on the overcoat film 41 on the wiring 23. After this, the fifth
Is peeled off. Thus, the liquid crystal display panel in this embodiment is obtained.

As described above, in the method of manufacturing the liquid crystal display panel according to this embodiment, the overcoat film 41 and the contact holes 62, 65 and 66 formed through the gate insulating film 31 are provided. On the pixel electrode 41, a jumper line 67 connecting the blocking portion of the protection ring 12, the connection pad 19 a connected to the connection pad 19, and the protection film 6 corresponding to the wiring 23.
8 can be formed of the same material. Therefore, the jumper line 67, the connection pad 19a, and the protective film 68 are formed of the same material as the pixel electrode 7 using the same material as the pixel electrode 7.
Can be formed at the same time as the formation, and the number of manufacturing steps can be reduced correspondingly. In particular,
As shown in FIG. 1, a photoresist film is used in five steps, that is, a step of forming a scanning line and the like, a step of forming a blocking layer, and a step of forming a data line and the like and eliminating the need for a semiconductor film and the like. A photoresist film is used only in five steps of a step of removing unnecessary parts (device area forming step), a step of forming contact holes in the overcoat film, and a step of forming pixel electrodes and the like. The number of steps can be reduced.

Here, the reason why the ITO (indium-tin oxide) film is dry-etched when forming the pixel electrode 7 and the like in FIG. 7 will be described. In the case of wet etching, the contact pads 17 made of Al-based metal exposed through the contact holes 65 and 66, the external connection terminals 22, and the ITO film and the ITO etchant coexist. The connection pad 17 and the external connection terminal 22 are oxidized and the ITO film is reduced (Al-ITO battery reaction) by the current generated by the generated oxidation-reduction potential difference, and both of them are severely corroded. Then, it is in order to avoid such a thing. In the connection pad 19 forming region,
The uppermost connection pad 19a made of ITO may not be formed.

As shown in FIG. 7, in the region where the wiring 23 is formed, the protective film 6 made of ITO is formed on the overcoat film 41 on the wiring 23 made of Al-based metal.
Since 8 is formed, even if the overcoat film 41 and the gate insulating film 31 on the wiring 23 have a defect for some reason, the protective film 68 exists on the defective portion. As a result, when the pixel electrode 7 is formed, the etching solution of ITO is applied to the overcoat film 41 and the gate insulating film 3.
1 can be prevented from penetrating into the defective portion, and furthermore, disconnection due to the Al-ITO battery reaction can be prevented from occurring in the wiring 23 made of Al-based metal, and the yield can be improved accordingly. Further, since the protective film 68 is formed simultaneously with the formation of the pixel electrode 7 using the same material as the pixel electrode 7, the number of manufacturing steps can be prevented from increasing. Further, the moisture in the air is reduced by the overcoat film 41.
In addition, since the protective film 68 can prevent the defective portion of the gate insulating film 31 from penetrating, the disconnection due to the corrosion of the wiring 23 made of the Al-based metal can be prevented.

In the above embodiment, the IT is formed on the overcoat film 41 on the wiring 23 made of Al-based metal.
Although the case where the protective film 68 made of O is formed has been described, the present invention is not limited to this. For example, although not shown, referring to FIG. 8, in the scanning line 9 forming area 9a in the non-display area 6, the ITO is formed on the overcoat film 41 on the scanning line (wiring) 9 made of Al-based metal. May be formed. Further, in the above embodiment, the n ⁺ silicon film region serving as the source / drain region of the thin film transistor is formed by the plasma C shown in the n ⁺ silicon film forming step S7 in FIG.
Although the case where the film is formed by the film formation by the VD method or the like has been described, the invention is not limited thereto, and the semiconductor film 51 may be formed by doping n-type ions such as phosphorus ions by the ion doping method using the blocking layers 32 and 33 as a mask. You may.

[0029]

As described above, according to the present invention, by forming a contact hole penetrating the overcoat film and the gate insulating film, the pixel electrode and at least the protection ring are cut off on the overcoat film. One of the jumper line connecting the parts, the top layer of the data line connection pad, and the wiring protection film is formed of the same material, so the jumper line is formed of the same material as the pixel electrode at the same time as the formation of the pixel electrode Therefore, the number of manufacturing steps can be reduced correspondingly. That is, in the manufacturing process of the display panel according to the present invention, a photoresist film is used only in five processes, that is, a process of forming a scanning line and the like, a process of forming a blocking layer, and a process of forming a data line and the like. In addition, a photoresist film is used only in five steps of a step of removing unnecessary portions such as a semiconductor film, a step of forming a contact hole in an overcoat film, and a step of forming a pixel electrode. The number can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a liquid crystal display panel according to an embodiment of the present invention.

FIG. 2 is a sectional view showing an initial step of FIG. 1;

FIG. 3 is a sectional view showing a step following FIG. 2;

FIG. 4 is a sectional view showing a step following FIG. 3;

FIG. 5 is a sectional view showing a step following FIG. 4;

FIG. 6 is a sectional view showing a step following FIG. 5;

FIG. 7 is a sectional view showing a step following FIG. 6;

FIG. 8 is an equivalent circuit plan view in a state where pixel electrodes and the like are formed on a glass substrate having a size corresponding to a plurality of liquid crystal display panels in the embodiment.

FIG. 9 is an equivalent circuit plan view showing a conventional example in which pixel electrodes and the like are formed on a glass substrate having a size corresponding to a plurality of liquid crystal display panels.

10 is a cross-sectional view of a part of a specific structure of the liquid crystal display panel shown in FIG.

FIG. 11 is a view showing a manufacturing process of the liquid crystal display panel shown in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 7 Pixel electrode 8 Thin film transistor 9 Scan line 10 Data line 11 Auxiliary capacitance line 12 Protective ring 13, 14 Protective element 17, 19, 20, 21 Connection pad 22 External connection terminal 23 Wiring 31 Gate insulating film 41 Overcoat film 67 Jumper wire

Claims (8)

[Claims] 1. A plurality of pixel electrodes arranged in a matrix, a plurality of switching elements respectively connected to the pixel electrodes, and a plurality of scans arranged in a row direction and supplying a scanning signal to the switching elements. Lines, a plurality of data lines arranged in the column direction to supply a data signal to the switching element, a protection ring arranged around the plurality of pixel electrodes and interrupted on the way, and the protection ring and each of the protection rings. A plurality of scan line-side protection elements respectively interposed between the scan lines, and a plurality of data line-side protection elements respectively interposed between the protection ring and each of the data lines; Are covered with an overcoat film, the pixel electrode is provided on the overcoat film, and a blocking portion of the protection ring is A jumper line to be connected or a top layer of a connection pad connected to the data line is provided, and at least one of the jumper line or the top layer of the connection pad is formed of the same material as the pixel electrode. A display panel characterized by the following. 2. The invention according to claim 1, further comprising a wiring provided under the overcoat film and for supplying the data signal or the scanning signal to the pixel electrode,
A display panel, wherein a protective film is provided on the overcoat film on the wiring, and the protective film is formed of the same material as the pixel electrode. 3. The display panel according to claim 2, wherein the wiring is a single layer and is formed of an aluminum-based metal. 4. A plurality of pixel electrodes arranged in a matrix, a plurality of switching elements respectively connected to the pixel electrodes, and a plurality of scans arranged in a row direction and supplying a scanning signal to the switching elements. Lines, a plurality of data lines arranged in the column direction to supply a data signal to the switching element, a protection ring arranged around the plurality of pixel electrodes and interrupted on the way, and the protection ring and each of the protection rings. A plurality of scan line side protection elements respectively interposed between the scan lines, a plurality of data line side protection elements respectively interposed between the protection ring and each of the data lines, and arranged in a non-display area. In the manufacture of a display panel having predetermined wiring, elements other than the pixel electrodes among the above elements are formed on a substrate, and these elements are overlaid. Cover layer, forming the pixel electrode on the overcoat film, and forming a top layer of a jumper line connecting a blocking portion of the protection ring, or a connection pad connected to the data line, and forming at least the A method of manufacturing a display panel, wherein either a jumper line or an uppermost layer of the connection pad is formed simultaneously with the same material as the pixel electrode. 5. The invention according to claim 4, further comprising a wiring provided under the overcoat film, the wiring being related to the supply of the data signal or the scanning signal to the pixel electrode,
A method of manufacturing a display panel, comprising forming a protective film on the overcoat film on the wiring using the same material as the pixel electrode at the same time as the formation of the pixel electrode. 6. The method according to claim 5, wherein the wiring is a single layer and formed of an aluminum-based metal. 7. A gate electrode, a gate insulating film, a semiconductor film, a data line, a source electrode, and a drain electrode are formed on a substrate, and these elements are covered with an overcoat film. Forming a contact hole penetrating the overcoat film and a contact hole penetrating the overcoat film and the gate insulating film at predetermined locations; and forming a pixel electrode on the overcoat film with the contact hole. And a step of connecting to the source electrode through the same. 8. The invention according to claim 7, wherein a conductive film is formed in a contact hole formed in the overcoat film and in a contact hole formed through the overcoat film and the gate insulating film. A method for manufacturing a display panel, comprising the steps of: