JP2008003134A - Wiring structure and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure capable of reducing display irregularity and to provide a display device having the wiring structure. <P>SOLUTION: The wiring structure relating to one embodiment of the invention includes: a plurality of gate routing wirings 131a which are formed on an array substrate and have different lengths; a plurality of wiring cutting parts 232 which are disposed according to the plurality of gate routing wirings and cut the gate routing wirings; and connection parts 23 which connect the lead wirings which are cut by the wiring cutting parts 232. On the connection part 23, a connection conductive film 233 which allows the lead wirings cut by the wiring cutting parts 232 to conduct electricity are formed and, in accordance with resistance differences between the plurality of gate routing wirings, at least one of width of the connection conductive film 233 and length of the wiring cutting part 232 is changed between the plurality of gate routing wirings. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring structure and a display device, and more particularly to a wiring structure including a plurality of lead wirings and a display device using the wiring structure.

  Conventionally, a liquid crystal display device has a plurality of gate lines (scanning signal lines) and a plurality of source lines (image signal lines) arranged in a matrix. In this liquid crystal display panel, a plurality of liquid crystal cells are formed corresponding to the intersections of these gate lines and source lines. The plurality of gate signal lines are driven by a gate driver IC, and the plurality of source lines are driven by a source driver IC.

  The gate wiring and the source wiring are formed on the liquid crystal surface side of the liquid crystal display panel. The wiring to each wiring is routed from the display area to the driver IC. This wiring is performed using a space around the display area (hereinafter, this space may be referred to as a frame). Therefore, the routing distance of each routing wiring routed to the display area varies depending on the mounting position of the driver IC. Therefore, display unevenness occurs due to the resistance difference between the wirings. In order to suppress this wiring resistance difference, the frame space is used and the wiring length and width are controlled. However, it is difficult to adjust the resistance difference and it is difficult to suppress the occurrence of display unevenness.

  The routing distance of the routing wiring varies depending on the layout of the driver IC and the wiring layout. For example, the lead wiring length may be different between turning the display area clockwise and counterclockwise. In a liquid crystal display panel having a large panel outer size and a small number of display pixels, there is a space in a frame space for routing each wiring connected from the driver IC to the display surface. Therefore, for example, when the source wiring routing distance differs between the left and right of the display as in the arrangement of the source driver IC, the resistance adjustment between the wirings can be performed by adjusting the wiring width and length.

  However, with the recent high-definition display and downsizing of the outer shape of the display panel, it has become difficult to secure a sufficient space for the frame. For this reason, it has become necessary to form a wiring with a wiring width close to the manufacturing limit. In this case, the surplus space becomes narrow and it becomes difficult to adjust the resistance with the wiring width. Therefore, it becomes necessary to adjust the resistance only with the wiring length. In this case, as described above, the wiring length is determined depending on the arrangement of the driver ICs, and thus it is difficult to suppress display unevenness due to the resistance difference between the wirings.

  For example, Patent Document 1 discloses a technique for performing resistance adjustment of resistance between wirings using an empty space in a frame, but recently, with the increase in display definition and downsizing of the outer shape of the display panel. It is difficult to secure a sufficient space for the frame, and as a result, it is difficult to suppress display unevenness.

JP 2000-187451 A

As described above, in the conventional liquid crystal display device, since the wiring distances of the respective wirings are different, there is a problem that a resistance difference occurs between the wirings and display unevenness occurs.
The present invention has been made to solve such a problem, and an object of the present invention is to provide a wiring structure and a display device capable of easily adjusting the resistance between the lead wirings.

  The wiring structure according to the first aspect of the present invention includes a plurality of routing wires having different lengths formed on a substrate, and a plurality of wires provided corresponding to the plurality of routing wires and cutting the routing wires. A cutting portion and a connection portion for connecting the routing wiring cut by the wiring cutting portion, and a connection conductive film for conducting the routing wiring cut by the wiring cutting portion is formed in the connection portion, At least one of the width of the connection conductive film and the length of the wiring cut portion varies between the plurality of routing lines in accordance with the resistance difference between the plurality of routing lines.

  A wiring structure according to a second aspect of the present invention includes a plurality of routing wirings having a first conductive layer formed on a substrate, a second conductive layer provided on the first conductive layer, and the first conductive layer. A lower insulating film disposed between one conductive layer and the second conductive layer, and provided corresponding to the plurality of routing wirings, and a portion of the routing wiring is provided between the first conductive layer and the first conductive layer. A connection portion provided at two locations of the routing wiring so as to have a laminated structure having two conductive layers, and a connection conductive film connecting the first conductive layer and the second conductive layer at the connection portion. And at least one of the width and the length of the second conductive layer is changed between the plurality of routing wires in accordance with a resistance difference between the plurality of routing wires. It is what you are doing.

  ADVANTAGE OF THE INVENTION According to this invention, the wiring structure and display apparatus which can adjust the resistance between routing wiring easily can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. In the following first to eighth embodiments, a liquid crystal display device will be described as a preferred example of the display device according to the present invention. However, the present invention is not limited to this, and scanning signal wiring, image signal wiring, and a driver IC for driving these wiring Any display device may be used. The driver IC is not particularly limited. For example, the driver IC may be a COG (Chip On Glass) type driver in which the driver IC is disposed on the glass substrate of the display panel, or an external TAB driver. In the eighth embodiment, a case where the wiring structure according to the present invention is applied to a test circuit for a display panel will be described. However, the present invention is not limited thereto, and any circuit having the wiring structure according to the present invention may be used. In particular, the wiring structure according to the present invention is suitable for suppressing display unevenness of the display device.

Embodiment 1.
First, the schematic configuration of the liquid crystal display panel according to the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram showing a configuration example of a liquid crystal display panel according to the present invention, and FIG. 1 shows only the main configuration.

  The liquid crystal display panel 1 typically has a display area 11 composed of a plurality of pixels arranged in a matrix, and a frame area 12 that is an outer peripheral area thereof. That is, the non-display area surrounding the outer periphery of the display area 11 becomes the frame area 12. The liquid crystal display panel 1 has an array substrate 2 on which wiring and array circuits are formed and a counter substrate, and liquid crystal is sealed between the two substrates. In FIG. 1, the counter substrate is not shown. Note that a counter electrode made of a transparent conductive film is formed on the counter substrate. An active matrix type liquid crystal panel includes a switching element in which each pixel controls input / output of an image signal. A typical switching element is a TFT (Thin Film Transistor).

  The color liquid crystal display device has an RGB color filter layer on a counter substrate. Each pixel in the display area of the liquid crystal panel 1 displays one of RGB colors. Of course, a black and white display displays either white or black. The array substrate 2 and the counter substrate are formed by forming a predetermined pattern on the transparent glass substrate. A transparent counter electrode is formed on the surface of the counter substrate on the array substrate 2 side. A backlight unit is disposed on the back surface of the liquid crystal panel 1.

  A plurality of source lines 132 and a plurality of gate lines 131 are arranged in a matrix on the array substrate 2 in the display area 11. That is, the array substrate 2 is a wiring substrate on which a plurality of wirings are formed. In FIG. 1, each of the source lines 132 is formed along the vertical direction. A plurality of source wirings 132 formed in the vertical direction are arranged side by side in the horizontal direction. In FIG. 1, source wirings 132 having the same width are formed at the same interval. On the other hand, in the display area 11, each of the gate lines 131 is formed in the horizontal direction. A plurality of gate wirings 131 formed in the horizontal direction are arranged side by side in the vertical direction. In the display area 11, gate lines 131 having the same width are formed at the same interval.

  In the frame region 12, a gate driver IC 141 and a source driver IC 142 are disposed. Here, the gate driver IC 141 and the source driver IC 142 are arranged below the display area 11 in the frame area 12. Here, in the frame region 12, a portion below the display region 11 is set as a lower portion of the frame region 12. Further, in the frame area 12, the side portion of the display area 11 is defined as a side portion of the frame area 12. The side of the frame region 12 has a right side and a left side. Further, the upper part of the display area 11 in the frame area 12 is defined as the upper part of the frame area 12. Therefore, the display area 11 is surrounded by the upper part, the right part, the left part, and the lower part of the frame area 12. Each driver IC is arranged on the lower side of the rectangular display area 11.

  The source wiring 132 and the gate wiring 131 are disposed so as to overlap each other at a substantially right angle through a gate insulating film, and a TFT is disposed in the vicinity of the intersection. For example, a gate insulating film is formed so as to cover the gate wiring 131 and the gate electrode extending from the gate wiring 131. For the gate insulating film, silicon oxide, silicon nitride, or the like can be used. Then, a semiconductor film is formed on the gate insulating film. As the semiconductor film, an a-Si film or a p-Si film can be used. A source electrode extending from the source wiring 132 is formed on the semiconductor film. Thereby, a source voltage can be supplied to the source region of the semiconductor film. Furthermore, a drain electrode is formed on the drain region of the semiconductor film. The source electrode and the drain electrode can be formed in the same process as the source wiring. For the gate wiring and the source wiring, for example, a low-resistance metal material such as Al or Cr can be used. Thus, the gate wiring 131 and the source wiring 132 are formed with different wiring layers.

  An interlayer insulating film is formed on the drain electrode. Further, a pixel electrode is formed on the interlayer insulating film. A pixel electrode is connected to the drain electrode through a contact hole provided in the interlayer insulating film. In the case of the transmissive liquid crystal display panel 1, the pixel electrode is formed of a transparent conductive film such as ITO. Accordingly, when a gate signal is supplied to the gate wiring, a gate voltage is applied to a predetermined gate electrode. Thereby, the TFT is turned on, and the image display signal voltage is supplied from the source electrode to the pixel electrode via the drain electrode.

  External control signals and display data are supplied to the gate driver IC 141 and the source driver IC 142. The gate driver IC 141 and the source driver IC 142 perform display based on the control signal and display data. That is, each pixel selected by the gate voltage input from the gate driver IC 141 applies an electric field to the liquid crystal based on the image display signal voltage input from the source driver IC 142. As a result, the alignment direction of the liquid crystal changes and the amount of transmitted light is controlled. A source driver IC 142 that supplies an image display signal voltage to the source line 132 and a gate driver IC 141 that supplies a gate voltage to the gate line 131 are connected to the frame area 12 of the array substrate 2 provided on the outer periphery of the display area.

  A gate routing wiring 131a is formed between the gate wiring 131 and the gate driver IC 141. A plurality of gate routing lines 131 a are provided corresponding to the plurality of gate lines 131. That is, the same number of gate routing lines 131 a as the gate lines 131 are formed on the array substrate 2. A plurality of gate routing wirings 131 a are formed in the frame region 12. The gate driver IC 141 and the gate wiring 131 are connected via the gate routing wiring 131a. That is, a gate signal is supplied from the gate driver IC 141 through the gate routing wiring 131a.

  A source lead-out wiring 132 a is formed between the source wiring 132 and the source driver IC 142. A plurality of source routing lines 132 a are provided corresponding to the plurality of source lines 132. That is, the same number of source routing wires 132 a as the source wires 132 are formed on the array substrate 2. A plurality of source routing wirings 132 a are formed in the frame region 12. The source driver IC 142 and the source wiring 132 are connected via this source routing wiring 132a. That is, a source signal is supplied from the source driver IC 142 via the source routing wiring 132a.

  Each routing wiring 131 a and 132 a is routed in the frame area 12 outside the display area 11. The gate line 131 and the source line 132 in the display area 11 are connected to each other. In the configuration shown in FIG. 1, the gate driver IC 141 is disposed below the display area 11. Therefore, the gate routing wiring 131 a is connected to the gate wiring 131 in the display area 11 from the side of the frame area 12. That is, the gate routing wiring 131a is formed from the lower part of the frame region 12 to the side part. The gate lead-out wiring 131a is connected to the gate wiring 131 at the side of the frame area. Note that the gate wiring 131 and the gate routing wiring 131a are formed of the same conductive film. As described above, the gate wiring 131 and the gate driver IC 141 are connected by the gate routing wiring 131 a routed to the frame region 12.

  Furthermore, about half of the plurality of gate routing lines 131 a are provided on the right side of the frame region 12. The remaining gate routing wiring 131a among the plurality of gate routing wirings 131a is provided on the left side of the frame region 12. That is, a part of the gate routing wiring 131 a is formed from the lower part of the frame area 12 to the right side, and is connected to the gate wiring 131 at the right end side of the display area 11. The remaining gate routing wiring 131 a is formed from the lower part to the left side of the frame area 12 and is connected to the gate wiring 131 at the left end side of the display area 11. Thereby, the frame area | region 12 can be narrowed.

  In the liquid crystal display panel 1 shown in FIG. 1, for example, the left side gate routing wiring 131 a and the right side gate routing wiring 131 a are alternately connected to the plurality of gate wirings 131. For example, the odd-numbered gate wiring 131 is connected to the gate routing wiring 131 a provided on the right side, and the even-numbered gate wiring 131 is connected to the gate routing wiring 131 a provided on the left side. In this way, the plurality of gate wirings 131 are alternately connected to the gate routing wiring 131a from both sides. When the gate lead-out wiring 131a is divided into the left and right sides of the display area 11 in this way, there is a possibility that a deviation occurs between the pixel line input from the left side and the pixel line input from the right side. In particular, in the case of the above configuration, since the left and right are alternately input, there is a risk that fine horizontal band-like unevenness for each line is likely to be visually recognized.

  The source driver IC 142 is also disposed below the display area 11. Accordingly, the source routing wiring 132a is provided only in the lower part of the frame region 12. The source routing wiring 132 a and the source wiring 132 are connected at the lower end side of the display area 11. Note that the source wiring 132 and the source routing wiring 132a are formed of the same conductive film. As described above, the source wiring 132 and the source driver IC 142 are connected by the source routing wiring 132 a routed to the frame region 12. These lead wirings 131a and 132a are formed on the array substrate 2 in a necessary number with a predetermined width. The lead wirings 131 a and 132 a are formed so as to be accommodated in the frame region 12.

  As described above, the plurality of gate wirings 131 are formed at a certain distance in the vertical direction. Therefore, in the liquid crystal display panel 1, the distance that the gate routing wiring 131a is routed differs depending on the arrangement of the gate driver IC 141 and the way the gate wiring 131 is routed. The plurality of gate routing lines 131a have different wiring lengths.

  Specifically, as shown in FIG. 1, the gate driver IC 141 is arranged on the left side of the source driver IC 142 in the frame region 12. Therefore, the gate driver IC 141 is located on the left side of the center of the array substrate 2 in the left-right direction. Therefore, the routing distance of the gate routing wiring 131a connected to the right side of the display area 11 (hereinafter referred to as the right routing gate routing wiring 131a) is the gate routing wiring 131a connected to the left (hereinafter referred to as this). It is longer than the routing distance of the counterclockwise gate routing wiring 131a. Therefore, there is a possibility that the wiring resistance of the clockwise gate routing wiring 131a may be higher than the wiring resistance of the counterclockwise gate routing wiring 131a. If the wiring resistance is different between the right-handed gate lead-out wiring 131a and the left-handed gate lead-out wiring 131a, fine horizontal band-like unevenness for each line is likely to be visually recognized in the display of the liquid crystal display panel. In the present embodiment, an effective configuration is adopted to reduce the above-described horizontal band unevenness.

  Then, the structure of a connection part is demonstrated using FIG. FIG. 2 is a plan view showing the configuration of the connecting portion 23. In the present embodiment, the connection portion 23 is formed in the vicinity of the location where the gate driver IC 141 of the array substrate 2 is connected. Specifically, the connection portion 23 is disposed below the frame region 12. On the array substrate 2, a gate driver IC 141, a COG terminal 22, and a connection portion 23 are provided. A plurality of connection portions 23 are provided corresponding to the plurality of gate routing wires 131a. Then, the connection unit 23 connects the gate routing wiring 131a and corrects the resistance value between the wirings. The COG terminal 22 is a terminal for connecting the gate routing wiring 131a and the gate driver IC 141. That is, the gate driver IC 141 is COG mounted with the COG terminal 22 exposed on the array substrate 2.

  A connection portion 23 is provided in the vicinity of the COG terminal 22. The connection portion 23 is connected between the gate driver IC 141 and the gate wiring 131. The connecting portion 23 is disposed on a part of the gate routing wiring 131a. For example, the connecting portion 23 is formed between the COG terminal 22 and the gate routing wiring 131a or a part of the gate routing wiring 131a. In the present embodiment, the connection portion 23 is disposed inside the outer edge of the gate driver IC 141. Therefore, the connection unit 23 is disposed immediately below the gate driver IC 141. As a result, the surplus space immediately below the gate driver IC 141 can be used, so that an increase in the frame area 12 can be prevented.

  The connection portion 23 has a function of correcting a resistance difference between the wiring resistance of the left-turned gate routing wiring 131a and the wiring resistance of the right-turning gate routing wiring 131a. For example, the connecting portion 23 is disposed only in one of the left-handed gate wiring 131 and the right-handed gate routing wiring 131a, and corrects the resistance difference between the gate routing wirings 131a routed left and right. Specifically, in the liquid crystal display panel 1 shown in FIG. 1, the connection portion 23 is provided for the counterclockwise gate lead-out wiring 131a having a low wiring resistance. Of course, in order to correct the wiring resistance difference between the upper and lower stages of the display area 11, a connection portion may be formed in all the gate routing wirings 131a.

  Subsequently, the connection portion 23 of the gate driver IC 141 according to the present invention will be specifically described with reference to FIG. FIG. 3 is a schematic diagram showing a specific configuration of the connecting portion 23. 3A is a top view showing the configuration of the connecting portion 23, and FIG. 3B is a cross-sectional view taken along the line AA of FIG. 3A. As shown in FIG. 3, the connection part 23 is provided with a gate wiring film 231, a wiring cutting part 232, a connection conductive film 233, a contact hole 234, and an insulating film 236. In this connection portion 23, the wiring layer is once converted.

  The gate wiring film 231 is a conductor constituting the gate routing wiring 131a, and a part thereof is divided. In other words, the gate routing wiring 131a is partially divided. The wiring cutting part 232 is a divided part of the gate wiring film 231 and electrically cuts the gate wiring film 231. That is, the gate routing wiring 131 a is cut by the wiring cutting portion 232. Since the gate routing wiring 131a and the gate wiring 131 are formed of the same layer, they have substantially the same material and the same film thickness.

  The connection conductive film 233 is made of a conductor having a higher resistance than the conductor constituting the gate wiring film 231. The connection conductive film 233 connects the gate wiring films 231 that are insulative with each other by the wiring cutting part 232. That is, the connection conductive film 233 is formed on both sides of the cut gate wiring film 231. The connection conductive film 233 is formed at a position overlapping with a part of the gate wiring film 231. The connection conductive film 233 has a substantially rectangular pattern shape. Note that the connection conductive film 233 is not limited to a rectangular shape. The dimension a (width a) in the short direction of the connection conductive film 233 is appropriately designed depending on the resistance difference between the gate wirings 131 routed to the left and right. At the same time, the dimension b (length b) in the longitudinal direction of the wiring cutting part 232, that is, the interval between the divided gate wiring films 231 is also appropriately designed based on the resistance difference between the gate wirings 131 routed left and right. Is done. By setting at least one dimension of the width a and the length b, the resistance difference between the gate routing wires 131a in which the connection portion 23 is routed left and right is corrected. That is, the resistance of the connection portion 23 is increased in the left-handed gate lead-out wiring 131a. Thereby, the resistance value of the left gate routing wiring 131a can be adjusted.

  Specifically, the dimensions of the gate routing wiring 131a having a short wiring length are set so that the connection portion 23 has a high resistance. For example, since the gate driver IC 141 is arranged on the left side, the wiring length of the counterclockwise gate routing wiring 131a is shortened. Therefore, the length b of the wiring cutting part 232 provided in the counterclockwise gate leading wiring 131a is increased. Alternatively, the width a of the connection conductive film 233 is reduced. Of course, only one of the length b and the width a may be changed, or both may be changed. More specifically, the length b is increased as the wiring length of the gate routing wiring 131a is shortened. Alternatively, the width a is reduced as the wiring length becomes shorter. The disconnected gate routing wiring 131a is connected in series by the connection conductive film 233. Accordingly, the dimensions can be determined so that the connection conductive film 233 has a resistance value based on the resistance difference of the gate routing wiring 131a. For example, the dimension of the connection conductive film 233 can be set so as to match the gate routing wiring 131a having the highest resistance value.

  An insulating film 236 is formed on the gate wiring film 231. The insulating film 236 is formed so as to cover the gate wiring film 231. A contact hole 234 is formed in part of the insulating film 236. The contact hole 234 is provided to connect the gate wiring film 231 and the connection conductive film 233. Therefore, the gate wiring film 231 and the connection conductive film 233 are connected through the contact hole 234. The contact hole 234 is formed near the end of the gate wiring film 231 on the wiring cutting part 232 side. Here, two contact holes 234 are formed on both sides of the cut portion of the gate wiring film 231. Thereby, even when a connection failure occurs in one contact hole 234, the connection can be made reliably.

  As shown in FIG. 3B, the gate wiring film 231 is patterned on the array substrate 2 in a cut state. An insulating film 236 is formed on the gate wiring film 231. The contact hole 234 is formed in the insulating film 236. The gate wiring film 231 is partially exposed at the contact hole 234. The gate wiring film 231 is divided at the wiring cutting part 232. An insulating film 236 is formed on the array substrate 2 from above the wiring cutting portion 232. The connection conductive film 233 is formed on such an insulating film 236 and is connected to the gate wiring film 231 through the contact hole 234. The length of the connection conductive film 233 is longer than that of the wiring cutting part 232. Further, a part of both sides of the divided gate wiring film 231 and a part of the connection conductive film 233 are formed to overlap each other.

  As described above, in the present invention, the connecting portion 23 can correct the wiring resistance of the left-handed gate routing wiring 131a and the wiring resistance of the right-handed gate routing wiring 131a, and make these wiring resistances substantially the same. Therefore, the resistance difference between the upper and lower pixels of the display region 11 can be made substantially the same as the resistance difference between the wirings on one side. Therefore, in the display of the liquid crystal display panel 1, it is possible to reduce the horizontal band-like unevenness that is easily visible due to the resistance difference of the gate wiring 131 of the even-odd pixel. In this way, the resistance between the routing wires can be adjusted, and the resistance difference can be improved. Accordingly, a resistance difference between wirings can be reduced, and display unevenness can be reduced. Further, in the present invention, not only the display unevenness due to the resistance difference between the wirings of the gate lead-out wiring 131a is reduced, but also the size of the connection conductive film 233 of the connection portion 23 only needs to be adjusted. It is possible to shorten the layout design study time of the wiring routing for obtaining.

  Here, the gate wiring film 231 can be patterned when the gate wiring 131 is formed. The insulating film 236 can be patterned in the same process as the gate insulating film. Further, the connection conductive film 233 can be patterned in the same process as the pixel electrode. In this case, the connection conductive film 233 is formed of a high-resistance transparent conductive film such as ITO. That is, the connection conductive film 233 for correcting the resistance difference is formed of a conductive film having a higher resistance than the gate wiring film 231. Thereby, the increase in a manufacturing process can be prevented. Further, the contact hole 234 can be formed in the patterning process of each insulating film. Thereby, the increase in a manufacturing process can be prevented.

  The connecting portion 23 can also be used for the source routing wiring 132a. In other words, a resistance difference is generated between the source routing wirings 132a according to the position of the source driver IC 142. For example, in FIG. 1, the source driver IC 142 is arranged on the right side of the center of the display area in the left-right direction. Therefore, the leftmost source routing wiring 132a has the longest wiring length. As described above, when the resistance value of the source routing wiring 132a is different, the connection portion 23 can be formed also for the source routing wiring 132a. Thereby, in the display of the display panel, it is possible to prevent the occurrence of vertical strip unevenness caused by the difference in resistance between the left and right of the source routing wiring 132a.

  Furthermore, depending on the arrangement of each driver IC, the source routing wiring 132 a may be formed above and below the display area 11. In this case, the resistance value between the wirings can be corrected by forming the connection portion 23 in the source routing wiring 132a. Thereby, display unevenness can be reduced.

  In this case, the connecting portion 23 is as shown in FIG. The source routing wiring 132a is formed of a conductive layer between the upper insulating film 236b and the lower insulating film 236a. Therefore, a transparent conductive film in the same layer as the pixel electrode can be used as the connection conductive film 233. The connection portion 23 can be formed in the vicinity of the source driver IC 142. Thereby, the resistance difference between wirings can be reduced and display unevenness can be reduced.

  Next, for example, a method for determining the dimensions of the connection conductive film 233 in the gate routing wiring 131a will be described. First, a pattern and the number of gate routing wirings 131a not provided with the wiring cutting portion 232 are determined in accordance with the wiring layout, and the resistance value of each gate routing wiring 131a is calculated. Then, a difference in resistance value between the plurality of gate routing wires 131a is obtained. The length of the wiring cut portion 232, the width of the connection conductive film 233, and the like are determined according to the difference in resistance value. Thereby, the difference in resistance value between the routing wirings can be reduced. Similarly, the dimensions of the connection portion 23 can be determined for the source lead-out wiring 132a.

  The position of the connecting portion 23 is not limited to the vicinity of the gate driver IC 141 or the source driver IC 142 shown in FIG. In the following, variations of the configuration and arrangement of the connecting portion 23 will be described as different embodiments. In addition, since the basic structure of the connection part 23 is the same as that of said structure, description is abbreviate | omitted. Therefore, also in the following embodiments, the connection conductive film 233 can be formed of, for example, a high-resistance transparent conductive film made of the same material as the pixel electrode.

  Further, on only one of the left and right sides of the display area 11, the gate wiring 131 a disposed on the lower side of the display area 11 and the gate wiring 131 disposed on the upper side have different lengths of the gate lead-out wiring 131 a. Yes. That is, the gate line 131 disposed below the display area 11 is closer to the gate driver IC 141 than the gate line 131 disposed above. Therefore, the length of the gate routing wiring 131a connected to the gate wiring 131 arranged on the lower side is shorter than that of the gate routing wiring 131a connected to the gate wiring 131 arranged on the upper side. In other words, the wiring length becomes longer as the outer gate routing wiring 131a. Thus, the plurality of gate routing wirings 131a have different lengths. Therefore, the resistance between the upper and lower wirings may be adjusted by the connection portion 23 described above.

Embodiment 2. FIG.
In the present embodiment, the connecting portion 23 is provided in the vicinity of the side edge of the display area 11 in the frame area 12. For example, the connection part 23 can be provided in the vicinity of the display area 11 as shown in FIG. As shown in FIG. 4A, the connection portion 23 is disposed outside the common CS wiring 71 beside the display area 11. The connection portion 23 is connected between the gate wiring 131 on the pixel 16 side and the gate routing wiring 131a. For example, when the connection part 23 does not fit between the outer edge of the gate driver IC 141 and the COG terminal 22, the connection part 23 can be arranged beside the display area 11. As a result, the connection portion 23 can be easily arranged without changing the size of the gate driver IC 141.

  As described above, even when the connection portion 23 does not fit between the outer end of the gate driver IC 141 and the COG terminal 22, the resistance between the wirings can be adjusted. As shown in the present embodiment, the connecting portion 23 may be formed in the middle of the gate routing wiring 131a extending from the lower portion of the frame region 12 to the side portion. That is, the connection portion 23 may be provided between the terminal for connecting to the gate driver IC 141 and the gate wiring 131. Of course, in this case, the connection portions 23 are respectively formed on the left and right gate routing lines 131a. That is, when the drawing is performed from both sides of the display area 11, the connection portions 23 are arranged on both the left and right sides of the display area 11. Further, when the connection portion 23 of the source lead-out wiring 132a is provided in the vicinity of the lower end side of the display area 11, the result is as shown in FIG. Thereby, the resistance difference between wirings can be reduced and display unevenness can be reduced.

Embodiment 3 FIG.
In the present embodiment, the connection portion 23 is provided both directly below the gate driver IC 141 and in the vicinity of the side edge of the display area 11. That is, when the difference in resistance is large and the size of the connection portion 23 becomes large, the connection portion 23 may be provided both directly below the gate driver IC 141 and in the vicinity of the side edge of the display region 11. In this way, the connection portions 23 may be formed at two or more locations of the single gate routing wiring 131a. The connection conductive film 233 of the connection portion 23 is connected in series to the gate routing wiring 131a. Here, the connection portion 23 is provided both near the gate driver IC 141 shown in the first embodiment and near the side edge of the display area 11 shown in the second embodiment. As a result, the resistance value can be reliably corrected. That is, the margin for correcting the resistance value can be widened. In the present embodiment, the resistance value can be corrected by at least one connection portion 23.

  For example, as shown in FIG. 5B, the dimension of the connection portion 23 near the side edge of the display region 11 is constant, and the resistance at the connection portion 23 near the gate driver IC 141 as shown in FIG. The value may be adjusted. Here, the connection portion 23 in the vicinity of the side edge of the display area 11 is formed in the same shape between the gate routing lines 131a.

  Alternatively, as an opposite configuration, the connection portion 23 in the vicinity of the gate driver IC 141 may be constant, and the resistance value may be adjusted by the dimension of the connection portion in the vicinity of the side edge of the display region 11. Thus, the layout design time can be shortened by making one connection portion constant and adjusting the other connection portion.

  The above configuration can also be applied to the source routing wiring 132a. For example, when the connection portions 23 of the source lead-out wiring 132a are provided in series at two locations, the results are as shown in FIGS. 5 (a) and 5 (c). As a result, the resistance difference between the wirings can be reduced, and the margin for correcting the resistance value can be widened. Accordingly, display unevenness can be reduced.

Embodiment 4 FIG.
Furthermore, as shown in FIG. 6, the connecting portion 23 may be arranged in parallel with respect to one gate routing wiring 131a. For example, the gate wiring film 231 is branched and patterned. Thereby, as shown in FIG. 6, two lines parallel to a part of one gate routing line 131a are formed. And the wiring cutting part 232 is formed in a branch location. Two connection conductive films 233 are respectively formed on the branched gate wiring films 231. Thereby, the connection conductive film 233 can be connected in parallel. Therefore, the adjustment margin of the resistance value can be widened. Here, the total resistance value of the parallel connection portions 23 can be half of the resistance value of the single connection portion 23.

  For example, when the resistance value of the connection conductive film 233 provided in the connection portion 23 is higher than the resistance difference of the gate routing wiring 131a, the resistance cannot be adjusted by the wiring width and wiring length of the left and right gate routing wiring 131a. In this case, the above configuration is preferable. Thereby, resistance adjustment can be performed reliably. That is, when the minimum resistance of the connection conductive film 233 formed in one connection portion 23 is determined, it is possible to adjust to a smaller resistance difference by connecting the two connection portions 23 in parallel. Here, the two connecting portions 23 connected in parallel have the same dimensions. Thus, by arranging the connecting portions 23 in parallel, the resistance value corrected between the wirings can be halved. The connecting portion 23 is formed in parallel to at least a part of the plurality of gate routing lines 131a. Thereby, further fine adjustment becomes possible. Therefore, a smaller resistance difference can be corrected, and display unevenness can be reduced. Further, the parallel number may be three or more. Of course, the parallel connection portion 23 can also be provided for the source routing wiring. Thereby, the same effect can be acquired.

Embodiment 5. FIG.
In the present embodiment, as shown in FIG. 7, the gate lead-out wiring 131a has a two-layer wiring. FIG. 7A is a plan view showing the configuration of the connection portion 23, and FIG. 7B is a cross-sectional view showing the configuration of the connection portion 23. The gate lead-out wiring 131 a is not provided with the wiring cutting part 232. In this embodiment, the gate lead-out wiring 131 a is converted into a stacked structure including the first conductive layer 135 and the second conductive layer 136 in the connection portion 23. That is, the gate lead-out wiring 131a formed by the first conductive layer 135 is constituted by two layers of the first conductive layer 135 and the second conductive layer 136 from the middle. In other words, a part of the gate routing wiring 131a is routed by the first conductive layer 135 and the second conductive layer 136 that are connected in parallel vertically. Then, a second connection portion 23 is provided on the gate lead-out wiring 131a having the laminated structure, and the single-layer structure is restored. In this way, the connection portions 23 are formed at two locations with respect to one gate routing wiring 131a. As a result, a part of the gate routing wiring 131 a has a laminated structure in which the first conductive layer 135 and the second conductive layer 136 are included. That is, between the connection portions 23 provided at two locations, the gate routing wiring 131a has a laminated structure. The second conductive layer 136 is disposed on the first conductive layer 135 via a lower insulating film 236a. A connection conductive film 233 is used to connect the first conductive layer 135 and the second conductive layer 136. That is, a contact hole 234 to the second conductive layer 136 is formed in a portion where the first conductive layer 135 and the second conductive layer 136 overlap. That is, the connection conductive film 233 and the second conductive layer 136 are connected through the contact hole 234 provided in the upper insulating film 236b. Further, contact holes 234 to the first conductive layer 135 are formed in the upper insulating film 236b and the lower insulating film 236a. Therefore, the first conductive layer 135 and the second conductive layer 136 formed in different layers can be connected through the connection conductive film 233. Here, in the insulating film 236, the lower insulating film 236a is the same layer as the gate insulating film, and the upper insulating film 236b is the same layer as the interlayer insulating film.

  As described above, a part of the gate routing wiring 131 a has a stacked structure including the first conductive layer 135 and the second conductive layer 136. That is, the gate lead-out wiring 131 a that was a single layer structure of the first conductive layer 135 is converted into a stacked structure of the first conductive layer 135 and the second conductive layer 136 at the connection portion 23. Here, the first conductive layer 135 can be formed using the same layer as the gate wiring 131, and the second conductive layer 136 can be formed using the same layer as the source wiring 132. Further, a lower insulating film 235a that is the same layer as the gate insulating film is disposed between the first conductive layer 135 and the second conductive layer 136. An upper insulating film 236b that is the same layer as the interlayer insulating film is formed on the second conductive layer. The connection conductive film 233 and the first conductive layer 135 are connected through the contact hole 234 provided in the lower insulating film 236a and the upper insulating film 236b, and the second conductive film is connected through the contact hole provided in the upper insulating film 236b. The conductive layer 136 is connected to the connection conductive film 233. The resistance can be adjusted by the size of the second conductive layer 136. For example, by increasing the distance between the two connecting portions 23, the distance of the stacked structure increases. That is, if the distance between the connecting portions 23 is increased, the second conductive layer 136 is increased, and thus the resistance of the entire gate routing wiring 131a can be reduced. Thus, the wiring resistance can be adjusted by the distance between the connecting portions 23. Alternatively, the width of the second conductive layer 136 is adjusted between the two connection portions 23. Thereby, the resistance of the laminated structure section is reduced, and the resistance of the entire gate routing wiring 131a can be reduced. Thus, resistance adjustment can be easily performed by adjusting the length and width of the second conductive layer 136 in the stacked structure. Accordingly, the resistance difference can be improved by the width and length of the second conductive layer 136. Furthermore, resistance adjustment may be performed according to the length and width of the connection conductive film 233 as in the first to third embodiments. In this way, the first conductive layer 135 and the second conductive layer 136 that have been converted to the stacked structure in the connection portion 23 are connected again on the terminal side and the gate wiring 131 side. Thereby, a part of the gate routing wiring 131a has a laminated structure, and the resistance value can be reduced.

  As shown in FIGS. 8A and 8B, the connection portion 23 can be disposed in the vicinity of the side edge of the display region 11 and in the vicinity of the gate driver IC 141. Then, the length and width of the second conductive layer 136 in the stacked structure between the connection portions 23 formed in two places, the vicinity of the side edge of the display region 11 and the vicinity of the gate driver IC 141 are changed. Adjust the resistance. Here, the connection portion 23 is formed outside the outer edge of the gate driver IC 141. Then, resistance adjustment is performed according to the position of the connecting portion 23 on the gate driver IC 141 side. Thereby, the resistance difference between wirings can be reduced and display unevenness can be reduced. Of course, the resistance may be adjusted according to the position of the connecting portion 23 on the edge side of the display area 11. And resistance adjustment is performed with the length of the 2nd conductive layer 136 in the laminated structure between the two connection parts 23, and a width | variety. The above configuration can also be applied to the source routing wiring 132a. That is, as shown in FIGS. 8B and 8C, the connecting portions 23 are arranged at two locations. The resistance can be adjusted by the length and width of the second conductive layer 136. Thus, resistance adjustment can be performed with a simple configuration by the wiring structure according to the present embodiment.

  By applying the wiring structure described in any of Embodiments 1 to 5 to a display device, display unevenness can be reduced. The above wiring structure is suitable not only for liquid crystal display devices but also for flat panel displays such as organic EL display devices. Further, the present invention may be applied to a wiring board other than the array substrate 2. It is possible to apply the wiring structure described in the first to fifth embodiments to the routing wiring to the scanning signal wiring or the image signal wiring. Thereby, display unevenness can be reduced.

  The first to fifth embodiments may be used in combination, and may be applied only to a part of a plurality of routing wires. The first to fifth embodiments can also be applied to a liquid crystal display panel 1 different from the configuration shown in FIG.

Embodiment 6 FIG.
The configuration of the liquid crystal display panel according to this embodiment will be described with reference to FIG. FIG. 9 is a plan view showing another configuration example of the liquid crystal display panel to which the first to fifth embodiments are applicable. As shown in FIG. 9, in order to make the frame area 12 narrower, the gate lead-out wiring 131a may be formed on different sides on the lower side and the upper side of the display area 11. For example, the gate routing wiring 131 a corresponding to the lower gate wiring 131 of the display area 11 passes through the left side of the frame area 12. On the other hand, the gate routing wiring 131 a corresponding to the gate wiring 131 on the upper side of the display area 11 passes through the right side of the frame area 12. Even in such a configuration, display unevenness easily occurs at the boundary between the upper side and the lower side of the display region 11. Also for the liquid crystal display panel 1 having such a configuration, display unevenness can be reduced by applying the wiring structures of the first to fifth embodiments. For example, the connection portion 23 is provided on the side of the left-hand routing wiring 131 before and after the gate wiring 131 at the boundary. Then, the wiring resistance of the counterclockwise routing wiring 131a is increased so that the resistance values of the counterclockwise routing wiring 131a and the clockwise routing wiring 131a match. Alternatively, as shown in the fifth embodiment, the connection portions 23 are formed at two locations of the left-handed routing wiring 131. Then, the length and width of the second conductive layer 136 in the laminated structure section are adjusted so that the resistance values of the left-handed routing wire 131a and the right-handed routing wire 131a are matched. In addition, although the case where the display area 11 is divided into two parts on the upper side and the lower side is shown here, the display area 11 is not limited to the configuration in which the display area 11 is divided at the same ratio. For example, the upper side 1/3 and the lower side 2/3 may be divided.

  Furthermore, it is also possible to adjust the wiring resistance on each of the upper side and the lower side of the display area 11 divided in the vertical direction. Here, the gate driver IC 141 is formed below the frame region 12. Accordingly, the gate wiring 131 on the upper side of the display area 11 is separated from the gate driver IC 141. In the gate routing wiring 131 with respect to the upper gate wiring 131, the wiring length becomes long and the wiring resistance becomes high. Here, the resistance value of the connection portion 23 is changed in order from the gate wiring 131 located near the gate driver IC 141. That is, as the distance between the gate wiring 131 and the gate driver IC 141 becomes shorter, the resistance value of the connection portion 23 of the gate routing wiring 131a may be increased. In this case, the dimensions of the connection portion 23 may be set so that the resistance increases toward the outer side of the right gate routing wiring 131a. Also in this case, the connection part 23 shown in Embodiments 1 to 5 can be applied. Thereby, the wiring resistance of the routing wiring 131a on the upper side or the lower side can be matched. Accordingly, display unevenness can be reduced.

Embodiment 7 FIG.
The configuration of the liquid crystal display panel according to this embodiment will be described with reference to FIG. FIG. 10 is a plan view showing another configuration example of the liquid crystal display panel to which the first to fifth embodiments are applicable. As shown in FIG. 10, when the gate driver IC 141 and the source driver IC 142 are formed by a common driver IC, the same problem as described above occurs. As shown in FIG. 10, the liquid crystal display panel 1 includes a single driver IC 150 to which wirings 131 and 132 are connected. In the liquid crystal display panel 1, the gate wiring 131 is disposed in the same manner as the liquid crystal display panel 1 of FIG. 9, whereas the source wiring 132 is disposed symmetrically at the center. Therefore, the wiring length of the source wiring 132 on the outer side (left and right sides of the driver IC 150) is longer than the wiring length of the source wiring 132 on the inner side (center side of the driver IC 150). Therefore, the wiring resistance of the outer source wiring 132 is higher than the wiring resistance of the inner source wiring 132. Also for the liquid crystal display panel 1 having such a configuration, display unevenness can be reduced by applying the wiring structures of the first to fifth embodiments.

Embodiment 8.
In the first to fifth embodiments, the case where the wiring structure according to the present invention is applied to the gate routing wiring or the source routing wiring of the liquid crystal display panel has been described. However, in this embodiment, the above wiring structure is connected to the inspection circuit. A case where the present invention is applied to an inspection routing wiring will be described. The inspection circuit is used for a simple lighting inspection used in a display inspection after the display panel is assembled.

  FIG. 11 is a diagram schematically showing the configuration of the inspection terminal group 62 and the inspection circuit 510. As shown in FIG. 11, a clockwise gate wiring inspection circuit 511, a counterclockwise gate wiring inspection circuit 512, and a source wiring inspection circuit 513 are arranged immediately below the driver IC 150. Here, the driver IC 150 is, for example, a combination of the gate driver IC 141 and the source driver IC 142 described above. The clockwise circuit 511 for turning clockwise, the gate inspection circuit 512 for turning counterclockwise, and the source wiring inspection circuit 513 are formed on the array substrate 2.

  The clockwise gate inspection circuit 511, the counterclockwise gate wiring inspection circuit 512, and the source wiring inspection circuit 513 have a layout separated from the inspection terminal group 62. That is, the inspection terminal group 62 is disposed outside the inspection circuit 510.

  The inspection circuit 510 has a clockwise gate wiring inspection circuit 511, a counterclockwise gate wiring inspection circuit 512, and a source wiring inspection circuit 513. The test terminal group 62 includes a TEST-right-turn gate terminal 521, a TEST-left-turn gate terminal 522, a TEST-R terminal 523 for inputting an R test signal, a TEST-G terminal 524 for inputting a G test signal, and a B test terminal B. It has a TEST-B terminal 525 for inputting a test signal, a switch terminal 526 for inputting a switch signal for turning on / off the inspection circuit, and a COMMON terminal 527. The right turn gate wiring inspection circuit 511 is connected to the TEST-right turn gate terminal 521 and the switch terminal 526. The counterclockwise gate wiring inspection circuit 512 is connected to the TEST-counterclockwise gate terminal 522 and the switch terminal 526. The source wiring inspection circuit 513 is connected to the TEST-R terminal 523, the TEST-G terminal 524, the TEST-B terminal 525, and the switch terminal 526. The COMMON terminal 527 is connected to a COMMON signal system such as the common CS wiring 71 of the display area 11 and the counter electrode of the counter substrate.

  Between the source wiring inspection circuit 513 and each of the TEST-R terminal 523, the TEST-G terminal 524, and the TEST-B terminal 525, the wiring routing distances are almost the same and there is no significant difference. On the other hand, the wiring routing distance between the left-turned gate wiring inspection circuit 512 and the TEST-left-turned gate terminal 522 is set between the right-turned gate wiring inspection circuit 511 and the TEST-right-turned gate terminal 521. Long compared to the wiring routing distance. Therefore, the wiring resistance between the left-turned gate wiring inspection circuit 512 and the TEST-left-turned gate terminal 522 is compared with the wiring resistance between the right-turned gate wiring inspection circuit 511 and the TEST-right-turned gate terminal 521. Become higher.

  Conventionally, due to the difference in wiring resistance, for example, in the configuration of FIG. In order to suppress this resistance difference, the wiring width between the right-turn gate wiring inspection circuit 511 and the TEST-right-turn gate terminal 521 and the left-turn gate wiring inspection circuit 512 and the TEST-left-turn gate terminal 522 The wiring resistance was adjusted by controlling the wiring width between them.

  However, recently, along with the shrinking of the driver IC 150, the shrinking of the test circuit 50 has progressed, and the space for controlling the wiring width and adjusting the wiring resistance has been reduced. For this reason, in the display inspection, the simple lighting inspection is performed in the upper and lower divided uneven state of the display area 11. As in the first to fifth embodiments, the present invention can be arranged between the gate wiring inspection circuit 511 and the TEST-clockwise gate terminal 521 by turning the connecting portion 23 clockwise. Accordingly, the wiring resistance between the counterclockwise gate wiring inspection circuit 512 and the TEST-counterclockwise gate terminal 522 can be adjusted. For example, unevenness in the upper and lower parts of the display area 11 during the simple lighting inspection can be improved. Thereby, the display inspection can be reliably performed.

  The connection portion 23 shown in the first to eighth embodiments is disposed in a region where the counter electrode of the counter substrate is not formed. Alternatively, the counter electrode of the counter substrate is removed in a region facing the portion where the connection portion 23 is provided. Thus, the connection part 23 is made not to be opposed to the counter electrode. That is, the connecting portion 23 is formed in a region where no corresponding electrode is provided. Thereby, a short circuit and corrosion can be prevented, and the fall of reliability can be prevented. Furthermore, the above-described first to eighth embodiments can be appropriately combined according to the wiring layout. Further, the connection portion 23 may be formed only on a part of the routing wiring. In the above wiring structure, since the frame region 12 is used, a simple configuration can be achieved. Note that the number of driver ICs may be two or more.

  In this manner, display unevenness can be reduced by adjusting the resistance value of the lead wiring between the terminal and the signal line.

It is a top view which shows the example of 1 structure of the liquid crystal display panel concerning this invention. It is a top view which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 1 of this invention. It is a schematic diagram which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 1 of this invention. It is a schematic diagram which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 2 of this invention. It is a schematic diagram which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 3 of this invention. It is a schematic diagram which shows the example of 1 structure of the connection part of the liquid crystal display panel concerning Embodiment 4 of this invention. It is a schematic diagram which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 5 of this invention. It is a schematic diagram which shows one structural example of the connection part of the liquid crystal display panel concerning Embodiment 5 of this invention. It is a top view which shows the structural example of the liquid crystal display panel which concerns on Embodiment 6 of this invention. It is a top view which shows the structural example of the liquid crystal display panel which concerns on Embodiment 7 of this invention. It is a figure which shows the structure of the test | inspection circuit of the liquid crystal display panel which concerns on Embodiment 8 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel, 2 Array board | substrate, 11 Display area | region, 12 Frame area | region, 16 pixels, 22 COG terminal, 23 Connection part, 62 Inspection terminal group, 71 Common CS wiring,
131 gate wiring, 131a gate routing wiring, 132 source wiring,
132a source routing wiring, 141 gate driver IC,
142 source driver IC, 150 driver IC,
231 gate wiring film, 232 wiring cutting part, 233 connection conductive film,
234 contact hole, 236 insulating film, 236a lower insulating film,
236b upper-layer insulating film 510 inspection circuit, 511 right-turn gate wiring inspection circuit,
512 Left turn gate wiring inspection circuit 522 TEST-left turn gate terminal 527 COMMON terminal 513 Source wiring inspection circuit 523 TEST-R terminal 524 TEST-G terminal 525 TEST-B terminal

Claims (11)

A plurality of lead wires of different lengths formed on the substrate;
A plurality of wiring cutting portions provided corresponding to the plurality of routing wirings, and cutting the routing wirings;
A connection part for connecting the routing wiring cut by the wiring cutting part,
In the connection portion, a connection conductive film is formed that conducts the routing wiring cut by the wiring cutting portion,
A wiring structure in which at least one of a width of the connection conductive film and a length of the wiring cut portion is changed between the plurality of routing wirings in accordance with a resistance difference between the plurality of routing wirings. A plurality of routing wires having a first conductive layer formed on the substrate;
A second conductive layer provided on the first conductive layer;
A lower insulating film disposed between the first conductive layer and the second conductive layer;
Provided corresponding to the plurality of routing wirings, and provided in two locations of the routing wiring so that a part of the routing wiring has a laminated structure including the first conductive layer and the second conductive layer. A connection,
A connection conductive film connecting the first conductive layer and the second conductive layer in the connection portion;
In the connection portion provided at the two locations, at least one of the width and the length of the second conductive layer varies between the plurality of routing wires in accordance with a resistance difference between the plurality of routing wires. Wiring structure.   3. The connection conductive film according to claim 2, wherein at least one of a width and a length of the connection conductive film changes between the plurality of lead wirings according to a resistance difference between the plurality of lead wirings. Wiring structure.   4. The wiring structure according to claim 1, wherein the connection conductive film is formed of a material having a higher resistance than the routing wiring.   The wiring structure according to any one of claims 1 to 4, wherein the connection conductive film is connected in parallel to one lead wiring. A plurality of signal wirings formed in the display area and connected to the routing wirings;
A drive circuit that is provided in a frame area outside the display area and that supplies a signal to the signal wiring;
The plurality of routing wires are formed in the frame region;
The wiring structure according to claim 1, wherein the connection conductive film is formed in the vicinity of the drive circuit. A plurality of signal lines formed in the display area and connected to the plurality of routing lines;
The plurality of routing wirings are formed in a frame region disposed outside the display region,
The wiring structure according to claim 1, wherein the connection conductive film is formed in the vicinity of an edge of the display region.   The wiring structure according to claim 7, wherein the connection conductive film is disposed in the vicinity of two opposing sides of the display region. A transparent pixel electrode provided in the display area;
The wiring structure according to claim 6, wherein the connection conductive film is formed of the same transparent conductive film as the transparent pixel electrode. A counter substrate disposed opposite to the substrate and having a counter electrode;
The wiring structure according to claim 6, wherein the connection portion is formed in a region other than the region where the counter electrode is provided.   A display device comprising a wiring board provided with the wiring structure according to claim 1.

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