CN109148479A - A kind of array substrate, display panel and preparation method thereof - Google Patents
A kind of array substrate, display panel and preparation method thereof Download PDFInfo
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- CN109148479A CN109148479A CN201810945490.0A CN201810945490A CN109148479A CN 109148479 A CN109148479 A CN 109148479A CN 201810945490 A CN201810945490 A CN 201810945490A CN 109148479 A CN109148479 A CN 109148479A
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 238000009413 insulation Methods 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 52
- 239000010409 thin film Substances 0.000 claims description 17
- 238000005538 encapsulation Methods 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 241000209140 Triticum Species 0.000 claims 1
- 235000021307 Triticum Nutrition 0.000 claims 1
- 235000013312 flour Nutrition 0.000 claims 1
- 230000002035 prolonged effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 193
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000012044 organic layer Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention provides a kind of array substrate, display panel and preparation method thereof, and the array substrate includes: underlay substrate；Tft layer, it is prepared on the underlay substrate, the tft layer includes the first area of corresponding display area, and the second area on the outside of the first area, and tft layer part corresponding with the second area includes GOA circuit；Insulating layer is prepared on the tft layer；Power signal line, the corresponding second area is prepared on the insulating layer, to provide supply voltage；Wherein, the power signal line is Chong Die with described GOA circuit at least part, and the power signal line and tft layer SI semi-insulation corresponding with the GOA circuit.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate, display panel and preparation method thereof.
Background technique
With the development of display industry technology, requirement of the people to display panel is higher and higher, such as some high-end aobvious
Show that panel may require that the design of narrow frame, pursues effective display area domain and maximize.And the design of existing display panel needs on side
Frame position reserves one fixed width to place other signal wires such as GOA driving circuit and VSS signal wire.Cause as a result, existing
The left and right side frame of display panel (AMOLED panel) is larger.If reduce GOA driving circuit to reduce border width, it will cause
The decline of GOA driving capability；And if reduction VSS signal wire will lead to the display area VSS of display panel to reduce border width
Potential uniformity is poor, line voltage signal drop (IR drop) phenomenon it is more serious, thus influence display panel show it is uniform
Property.Therefore, the narrow frame design for realizing display panel is a great problem.
Therefore, the prior art is defective, needs to improve.
Summary of the invention
The present invention provides a kind of array substrate, display panel and preparation method thereof, can reduce the two sides of display panel
Frame achievees the purpose that display panel narrow frame.
To solve the above problems, technical solution provided by the invention is as follows:
The present invention provides a kind of array substrate, comprising:
Underlay substrate；
Tft layer is prepared on the underlay substrate, and the tft layer includes corresponding display area
First area, and the second area on the outside of the first area, the tft layer and the second area pair
The part answered includes GOA circuit；
Insulating layer is prepared on the tft layer；
Power signal line, the corresponding second area is prepared on the insulating layer, to provide supply voltage；
Wherein, the power signal line is Chong Die with GOA circuit at least part, and the power signal line with it is described
Tft layer SI semi-insulation corresponding with the GOA circuit.
According to one preferred embodiment of the present invention, the array substrate further includes planarization layer and metal contact layer, described flat
Smoothization layer is prepared on the power signal line, and the position of the correspondence power signal line is provided with the first via hole；It is described
Metal contact layer is prepared on the planarization layer, and is overlapped by first via hole and the power signal line.
According to one preferred embodiment of the present invention, the array substrate further includes pixel defining layer, the pixel defining layer system
It is standby on the metal contact layer, and the position of the correspondence power signal line is provided with the second via hole.
The invention also includes a kind of display panels, comprising:
Underlay substrate；
Tft layer is prepared on the underlay substrate, and the tft layer includes corresponding display area
First area, and the second area on the outside of the first area, the tft layer and the second area pair
The part answered includes GOA circuit；
Insulating layer is prepared on the tft layer；
Power signal line, the corresponding second area is prepared on the insulating layer, to provide supply voltage；
Planarization layer is prepared on the power signal line；
Pixel defining layer is prepared on the planarization layer, and defines pixel region；
Pixel unit layer, the corresponding pixel region are prepared on the planarization layer；
Wherein, the power signal line is Chong Die with GOA circuit at least part, and the power signal line with it is described
Tft layer SI semi-insulation corresponding with the GOA circuit.
According to one preferred embodiment of the present invention, the planarization layer surface of the corresponding second area is prepared with metal and connects
Contact layer, and the planarization layer is provided with the first via hole in the position of the correspondence power signal line, the metal contact layer is logical
It crosses first via hole and the power signal line overlaps.
According to one preferred embodiment of the present invention, the pixel defining layer is provided in the position of the correspondence power signal line
Second via hole, the pixel unit layer include cathode layer, and the cathode layer passes through second via hole and the metal contact layer
Overlap joint.
According to one preferred embodiment of the present invention, the display panel further includes thin-film encapsulation layer, is prepared in the pixel list
On first layer, the thin-film encapsulation layer extends to the second area, and for wrapping up the power signal line and GOA electricity
Road.
The invention also includes a kind of preparation methods of display panel, the described method comprises the following steps:
Step S10 provides a underlay substrate, prepares tft layer on the underlay substrate, wherein the film
Transistor layer includes the first area of corresponding display area, and the second area on the outside of the first area, described thin
Film transistor layer part corresponding with the second area includes GOA circuit；
Step S20 is sequentially prepared insulating layer and metal layer on the tft layer, patterns the metal layer
The power signal line of the corresponding GOA circuit is formed, the power signal line is to provide supply voltage；
Step S30 is sequentially prepared planarization layer, pixel defining layer and pixel unit layer on the metal layer；
Wherein, the power signal line is Chong Die with GOA circuit at least part, and the power signal line with it is described
Tft layer SI semi-insulation corresponding with the GOA circuit.
According to one preferred embodiment of the present invention, the step S30 the following steps are included:
Step S301, prepares planarization layer on the metal layer, is formed described in corresponding to the planarization layer pattern
First via hole of power signal line；
Step S302, prepares metal contact layer on the planarization layer of the correspondence second area, and the metal connects
Contact layer is overlapped by first via hole and the power signal line；
Step S303 prepares the pixel defining layer on the metal contact layer and the planarization layer, to described
Pixel defining layer carries out the second via hole that patterning forms the corresponding power signal line；
Step S304 prepares the pixel unit layer in the pixel defining layer, wherein the pixel unit layer includes
Cathode layer, the cathode layer are overlapped by second via hole and the metal contact layer.
According to one preferred embodiment of the present invention, further comprising the steps of after the step S30:
Step S40, prepares thin-film encapsulation layer in the pixel unit layer, and the thin-film encapsulation layer is to the second area
Extend, and wraps up the power signal line and the GOA circuit.
The invention has the benefit that compared to existing display panel, array substrate provided by the invention, display panel
And preparation method thereof, by increasing the system of a layer insulating and one layer of metal layer in the preparation process of existing display panel
Journey changes the VSS signal wire (power signal line) made in the left and right side frame of existing design with SD1 layers using SD2 layers of (metal into
Layer) production, and be superimposed upon above GOA circuit, the insulating layer that centre is arranged one layer thicker carries out signal and directly completely cuts off.It can be real
While not reducing the width of GOA circuit now and also do not reduce the width of VSS signal wire, reach reduction panel left and right side frame
Purpose.Further, since power signal line of the invention and cathode layer overlap, can be provided more for the cathode layer of display area
Uniform current potential (VSS current potential) helps to improve asking for display panel non-uniform light to further increase display effect
Topic.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is array base-plate structure schematic diagram provided in an embodiment of the present invention；
Fig. 2 is display panel structure schematic diagram provided in an embodiment of the present invention；
Fig. 3 is the preparation method flow chart of display panel provided in an embodiment of the present invention.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention is directed to the display panel of the prior art, and it is wider that there are frames, is unfavorable for the design of display panel narrow frame
The technical issues of, the present embodiment is able to solve the defect.
As shown in Figure 1, being array base-plate structure schematic diagram provided in an embodiment of the present invention.The array substrate, comprising: substrate
Substrate 10；Tft layer (does not indicate) in figure, is prepared on the underlay substrate 10, and the tft layer includes pair
Answer the first area 11 of display area, and the second area positioned at 11 outside of first area, the tft layer
Part corresponding with the second area includes GOA circuit 12；Insulating layer (does not indicate) in figure, is prepared in the thin film transistor (TFT)
On layer；Power signal line 13, the corresponding second area is prepared on the insulating layer, to provide supply voltage；Wherein, institute
It states power signal line 13 and the GOA circuit 12 is be overlapped at least partially；Preferably, the region where the power signal line 13
It is corresponding to be located in the range of 12 region of GOA circuit.The power signal line 13 and the tft layer and institute
State the corresponding SI semi-insulation of GOA circuit 12.
In addition, the array substrate further includes planarization layer and metal contact layer, the planarization layer is prepared in the electricity
On source signal line 13, and the position of the correspondence power signal line 13 is provided with the first via hole；The metal contact layer preparation
It is overlapped on the planarization layer, and by first via hole and the power signal line 13.
The array substrate further includes pixel defining layer, and the pixel defining layer is prepared on the metal contact layer, and
The position of the correspondence power signal line 13 is provided with the second via hole.The array substrate further include: flip chip 14, binding
In the one side edge position of the array substrate；Printed circuit board 15 is bound with the flip chip 14.
In addition, illustrating the power signal line 13 with the width of the GOA circuit 12 only for the two position is clear
Statement, herein not as restriction, the specific width of the two is subject to width needed for practical processing procedure.
As shown in Fig. 2, being display panel structure schematic diagram provided in an embodiment of the present invention, which includes: substrate
Substrate 20；Tft layer 21 is prepared on the underlay substrate 20, and the tft layer 21 includes corresponding viewing area
The first area 210 in domain, and the second area positioned at 210 outside of first area, the tft layer 21 and institute
Stating the corresponding part of second area includes GOA circuit 211；Insulating layer 22 is prepared on the tft layer 21；Power supply letter
Number line 23, the corresponding second area is prepared on the insulating layer 22, to provide supply voltage；Planarization layer 24, preparation
In on the power signal line 23；Pixel defining layer 25 is prepared on the planarization layer 24, and defines pixel region；Picture
Plain elementary layer, the corresponding pixel region are prepared on the planarization layer 24；Wherein, described in the power signal line 23 corresponds to
GOA circuit 211 is set to the insulating layer 22, i.e., the described power signal line 23 is overlapped with the GOA circuit 211 insulation.
It may be implemented in the width for not reducing the GOA circuit 211 and also not reducing the power signal line 23 (VSS signal wire)
While width, achieve the purpose that the reduction display panel left and right side frame.
24 surface of the planarization layer of the corresponding second area is prepared with metal contact layer 28, and the planarization layer
24 are provided with the first via hole 240 in the position of the correspondence power signal line 23, and the metal contact layer 28 passes through described first
Via hole 240 and the power signal line 23 overlap.The pixel defining layer 25 is set in the position of the correspondence power signal line 23
Be equipped with the second via hole 250, the pixel unit layer includes cathode layer 26, the cathode layer 26 by second via hole 250 with
The metal contact layer 28 overlaps.Since the power signal line 23 is taken by the metal contact layer 28 with the cathode layer 26
It connects, realizes that the power signal line 23 of bezel locations is connected to the cathode in the display area of the display panel
Layer 26 can provide more uniform current potential (VSS current potential) for the cathode layer 26, to further increase display effect, have
Help the problem of improving display panel non-uniform light.
The display panel further includes thin-film encapsulation layer 27, is prepared in the pixel unit layer, the thin-film encapsulation layer
27 extend to the second area, and for wrapping up the power signal line 23 and the GOA circuit 211.The film envelope
Fill the inorganic layer and organic layer that layer 27 includes multilayer laminated setting.
The present invention also provides the preparation methods of above-mentioned display panel, as shown in figure 3, the described method comprises the following steps:
Step S10 provides a underlay substrate, prepares tft layer on the underlay substrate, wherein the film
Transistor layer includes the first area of corresponding display area, and the second area on the outside of the first area, described thin
Film transistor layer part corresponding with the second area includes GOA circuit；
Specifically, the tft layer is formed on flexible base board or glass substrate first, including described in correspondence
The GOA circuit etc. of the pixel-driving circuit of display area and the corresponding second area.Including: in the underlay substrate
Upper formation polysilicon layer；Gate insulation layer is formed on the polysilicon layer；The polysilicon layer is corresponded on the gate insulation layer
Position formed grid；Insulating layer between being formed on the grid；Then source-drain electrode is re-formed；At the same time, secondth area
The GOA circuit is formed in domain.
Step S20 is sequentially prepared insulating layer and metal layer on the tft layer, patterns the metal layer
The power signal line of the corresponding GOA circuit is formed, the power signal line is to provide supply voltage；
Specifically, the insulating layer can be organic insulator or inorganic insulation layer；The insulating layer is for completely cutting off institute
The signal for stating GOA circuit Yu the power signal line avoids that signal cross-talk occurs between each other.The material of the metal layer can be with
For Ti/Al/Ti etc., herein with no restrictions.
Preferably, the power signal line is low potential source line, provides low potential source voltage for the display area.
Wherein, the power signal line is Chong Die with described GOA circuit at least part；Preferably, the power signal line
Region is overlapped with GOA circuit region.The power signal line is located at GOA circuit top position,
The power signal line and tft layer SI semi-insulation corresponding with the GOA circuit.
Step S30 is sequentially prepared planarization layer, pixel defining layer and pixel unit layer on the metal layer；
Specifically, the step S30 the following steps are included:
Step S301, prepares planarization layer on the metal layer, to the planarization layer pattern, is formed described in corresponding to
First via hole of power signal line；
Wherein, the planarization layer is formed in the first area and the second area.
Step S302, prepares metal contact layer on the planarization layer of the correspondence second area, and the metal connects
Contact layer is overlapped by first via hole and the power signal line；
Wherein, the metal contact layer can by being formed after anode metal pattern layers, i.e., the described metal contact layer with
Anode layer passes through the light shield technique with along with and is made.It is big that first via hole can be designed aperture according to the demand of manufacturing process
It is small.
Step S303 prepares the pixel defining layer on the metal contact layer and the planarization layer, to described
Pixel defining layer carries out the second via hole that patterning forms the corresponding power signal line；
Wherein, the pixel defining layer defines pixel region in the correspondence first area；Second via hole can be with
Aperture size is designed according to the demand of manufacturing process.
Step S304 prepares the pixel unit layer in the pixel defining layer, wherein the pixel unit layer includes
Cathode layer, the cathode layer are overlapped by second via hole and the metal contact layer.
Wherein, the pixel unit layer further includes anode layer and organic luminous layer；Since the power signal line passes through institute
It states metal contact layer and the cathode layer overlaps, realize that the power signal line of bezel locations is connected to the display panel
The cathode layer in the display area can provide more uniform current potential (VSS current potential) for the cathode layer, thus into
One step improves display effect, facilitates the problem of improving display panel non-uniform light.
In addition, further comprising the steps of after the step S30:
Step S40, prepares thin-film encapsulation layer in the pixel unit layer, and the thin-film encapsulation layer is to the second area
Extend, and wraps up the power signal line and the GOA circuit.
Specifically, the thin-film encapsulation layer includes the inorganic layer and organic layer of multilayer laminated setting, the thin-film encapsulation layer
The power signal line and the GOA circuit be can protect not by the erosion of water oxygen.
The display panel of the invention may also include other conventional films, such as buffer layer, touch control layer and polaroid
Deng this programme applies also for other different types of display panels, herein with no restrictions.
Array substrate provided by the invention, display panel and preparation method thereof, pass through the preparation work in existing display panel
In skill, increase the processing procedure of a layer insulating and one layer of metal layer, by what is made in the left and right side frame of existing design with SD1 layers
VSS signal wire (power signal line) changes into be made of SD2 layers (metal layer), and is superimposed upon above GOA circuit, centre setting one
The thicker insulating layer of layer carries out signal and directly completely cuts off.It may be implemented in the width for not reducing GOA circuit and also not reduce VSS
While the width of signal wire, achieve the purpose that reduce panel left and right side frame.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate characterized by comprising
Underlay substrate；
Tft layer is prepared on the underlay substrate, and the tft layer includes the first of corresponding display area
Region, and the second area on the outside of the first area, the tft layer are corresponding with the second area
Part includes GOA circuit；
Insulating layer is prepared on the tft layer；
Power signal line, the corresponding second area is prepared on the insulating layer, to provide supply voltage；
Wherein, the power signal line is Chong Die with described GOA circuit at least part, and the power signal line and the film
Transistor layer SI semi-insulation corresponding with the GOA circuit.
2. array substrate according to claim 1, which is characterized in that the array substrate further includes planarization layer and metal
Contact layer, the planarization layer are prepared on the power signal line, and are provided in the position of the correspondence power signal line
First via hole；The metal contact layer is prepared on the planarization layer, and passes through first via hole and the power supply signal
Line overlap joint.
3. array substrate according to claim 2, which is characterized in that the array substrate further includes pixel defining layer, institute
It states pixel defining layer to be prepared on the metal contact layer, and the position of the correspondence power signal line is provided with the second mistake
Hole.
4. a kind of display panel characterized by comprising
Underlay substrate；
Tft layer is prepared on the underlay substrate, and the tft layer includes the first of corresponding display area
Region, and the second area on the outside of the first area, the tft layer are corresponding with the second area
Part includes GOA circuit；
Insulating layer is prepared on the tft layer；
Power signal line, the corresponding second area is prepared on the insulating layer, to provide supply voltage；
Planarization layer is prepared on the power signal line；
Pixel defining layer is prepared on the planarization layer, and defines pixel region；
Pixel unit layer, the corresponding pixel region are prepared on the planarization layer；
Wherein, the power signal line is Chong Die with described GOA circuit at least part, and the power signal line and the film
Transistor layer SI semi-insulation corresponding with the GOA circuit.
5. display panel according to claim 4, which is characterized in that the planarization layer table of the corresponding second area
Wheat flour has metal contact layer, and the planarization layer is provided with the first via hole, institute in the position of the correspondence power signal line
Metal contact layer is stated to overlap by first via hole and the power signal line.
6. display panel according to claim 5, which is characterized in that the pixel defining layer is in the correspondence power supply signal
The position of line is provided with the second via hole, and the pixel unit layer includes cathode layer, the cathode layer by second via hole with
The metal contact layer overlap joint.
7. display panel according to claim 4, which is characterized in that the display panel further includes thin-film encapsulation layer, system
Standby in the pixel unit layer, the thin-film encapsulation layer extends to the second area, and for wrapping up the power supply signal
Line and the GOA circuit.
8. a kind of preparation method of display panel, which is characterized in that the described method comprises the following steps:
Step S 10 provides a underlay substrate, prepares tft layer on the underlay substrate, wherein the film is brilliant
Body tube layer includes the first area of corresponding display area, and the second area on the outside of the first area, the film
Transistor layer part corresponding with the second area includes GOA circuit；
Step S20 is sequentially prepared insulating layer and metal layer on the tft layer, patterns the metal layer and is formed
The power signal line of the corresponding GOA circuit, the power signal line is to provide supply voltage；
Step S30 is sequentially prepared planarization layer, pixel defining layer and pixel unit layer on the metal layer；
Wherein, the power signal line is Chong Die with described GOA circuit at least part, and the power signal line and the film
Transistor layer SI semi-insulation corresponding with the GOA circuit.
9. preparation method according to claim 8, which is characterized in that the step S30 the following steps are included:
Step S301, prepares planarization layer on the metal layer, forms the corresponding power supply to the planarization layer pattern
First via hole of signal wire；
Step S302 prepares metal contact layer, the metal contact layer on the planarization layer of the correspondence second area
It is overlapped by first via hole and the power signal line；
Step S303 prepares the pixel defining layer on the metal contact layer and the planarization layer, to the pixel
Definition layer carries out the second via hole that patterning forms the corresponding power signal line；
Step S304 prepares the pixel unit layer in the pixel defining layer, wherein the pixel unit layer includes cathode
Layer, the cathode layer are overlapped by second via hole and the metal contact layer.
10. preparation method according to claim 8, which is characterized in that further comprising the steps of after the step S30:
Step S40, prepares thin-film encapsulation layer in the pixel unit layer, and the thin-film encapsulation layer is prolonged to the second area
It stretches, and wraps up the power signal line and the GOA circuit.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109658824A (en) * | 2019-02-28 | 2019-04-19 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111223439A (en) * | 2020-03-12 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
| WO2020232916A1 (en) * | 2019-05-21 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN112114701A (en) * | 2020-09-07 | 2020-12-22 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US11847967B2 (en) | 2020-10-19 | 2023-12-19 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and preparation method therefor, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109658824A (en) * | 2019-02-28 | 2019-04-19 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109658824B (en) * | 2019-02-28 | 2021-07-09 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2020232916A1 (en) * | 2019-05-21 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111223439A (en) * | 2020-03-12 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit applied to array substrate, array substrate and manufacturing method of GOA circuit |
| CN112114701A (en) * | 2020-09-07 | 2020-12-22 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US11847967B2 (en) | 2020-10-19 | 2023-12-19 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and preparation method therefor, and display device |
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