JPH05109913A - Wiring structure of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate wiring design limits, permit dense wiring and provide a wiring structure whose strokes of an analog signal and a digital signal are suppressed for a semiconductor integrated circuit which has both the analog signal and digital signal. CONSTITUTION:On a semiconductor integrated circuit, two pieces of analog wiring 2 and 5, which pass an analog signal, are permitted to cross digital wiring 8, which passes a digital signal. Wiring layers (a semiconductor substrate 1 and a grounding metal wiring layer 6) which ground on the top and bottom of a wiring layer 2 (a part of the analog wiring) are formed and a wiring layer 8 is permitted to cross the grounding wiring layers at the top or bottom of the layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit, and more particularly to a wiring structure in which crosstalk between wirings is eliminated.

[0002]

2. Description of the Related Art With the recent increase in the density of semiconductor integrated circuits, the wiring structure tends to be multi-layered, or the distance between adjacent wirings tends to be reduced. Therefore, in a semiconductor integrated circuit in which analog signals and digital signals (including clock signals) are mixed, wiring for passing analog signals (hereinafter referred to as analog wiring) and wiring for passing digital signals (hereinafter referred to as digital wiring) intersect. Often or adjacent to each other.

[0003]

In such a semiconductor integrated circuit, at the intersection of the analog wiring and the digital wiring, the voltage fluctuation when the digital signal changes affects the analog signal, and the waveform of the analog signal collapses. There is a possibility that so-called crosstalk, which causes a malfunction of the circuit, may occur. Similarly, in the adjacent portion of the analog wiring and the digital wiring, the voltage fluctuation of the digital signal may affect the analog signal.

For this reason, conventionally, when the wiring is laid out, the design is such that the analog wiring and the digital wiring do not intersect, or the two wirings are not adjacent to each other. There is a problem that it becomes an obstacle to high density and it is difficult to obtain a highly integrated semiconductor integrated circuit. An object of the present invention is to suppress crosstalk between analog and digital signals,
An object of the present invention is to provide a wiring structure in which restrictions on wiring design are eliminated and wiring density can be increased.

[0005]

According to the wiring structure of the present invention, a grounded wiring layer is formed above and below one wiring layer of analog wiring and digital wiring, and the other wiring layer is formed above these ground wiring layers. Or cross at the bottom. Also, grounded wiring is provided along both sides of one wiring, and the other wiring is arranged outside these ground wirings.

[0006]

According to the present invention, one wiring layer is ground-shielded between the other wiring by the ground wiring layers formed on the upper side and the lower side, so that the voltage fluctuation of the digital signal in one wiring can be prevented in the other wiring layer. Affecting the analog signal is avoided. Similarly, one wiring is grounded and shielded from the other wiring provided on the outer side by the ground wiring provided on both sides, and the fluctuation of the voltage of the digital signal is prevented from affecting the analog signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B show a first embodiment in which the present invention is applied to a multilayer wiring structure. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line AA. A diffusion wiring layer 2 composed of an N-type semiconductor diffusion layer is provided on the grounded P-type semiconductor substrate 1. An insulating film 3 is formed on the P-type semiconductor substrate 1, and metal that is connected to both ends of the diffusion wiring layer 2 is formed on the insulating film 3 through contact holes 4 formed in the insulating film 3. The wiring layer 5 is provided. At the same time as the metal wiring layer 5, a ground metal wiring layer 6 is provided in the upper region of the diffusion wiring layer 2 so as to cover it. The ground metal wiring layer 6 is connected to the P-type semiconductor substrate 1 at a portion not shown in the drawing and is grounded.

An interlayer insulating film 7 is formed on the metal wiring layers 5 and 6, and the diffusion wiring layer 2 is formed on the interlayer insulating film 7.
A metal wiring layer 8 intersecting with is formed. A protective insulating film 9 is formed on the metal wiring layer 8. Then, the metal wiring layer 5 connected to each other in the diffusion wiring layer 2 is configured as an analog wiring, and the metal wiring layer 8 is configured as a digital wiring.

According to this structure, the analog wiring formed by the metal wiring layer 5 and the diffusion wiring layer 2 is located at the lower P-type semiconductor at the intersection with the metal wiring layer 8 formed as a digital wiring. Substrate 1 and upper ground metal wiring layer 6
It is sandwiched between and and will be grounded in the vertical direction. Therefore, even if a voltage fluctuation occurs in the digital signal passed through the digital wiring, the influence thereof hardly affects the analog signal passed through the analog wiring, and the crosstalk can be suppressed. As a result, it is possible to allow the crossing arrangement of the analog wiring and the digital wiring, and it is possible to increase the degree of freedom in wiring design and to increase the wiring density to achieve high integration of the semiconductor integrated circuit.

When actually designing such wiring, as shown in FIG. 1, the diffusion wiring layer 2, the metal wiring layer 5, the ground metal wiring layer 6, and the intersecting metal wiring layer 8 are formed. Register the structure as one cell as part of the database. When the wiring layer recognized as an analog wiring in the netlist and the wiring layer recognized as a digital wiring intersect at the time of placement and routing, the design in which the cells are placed may be performed. Good. If the wiring is analog wiring, the placement and wiring means should recognize it by, for example, setting the initial letter of the net name on the netlist to a specific character string. Good.

FIG. 2 shows a second embodiment of the present invention,
The figure (a) is a top view and the figure (b) is the BB sectional drawing. In this embodiment, a polycrystalline silicon wiring layer 10 is formed on a base insulating film 11 provided on the P semiconductor substrate 1, and the polycrystalline silicon wiring layer 10 is used to connect the metal wiring layer 5. .. Then, the ground metal layer 6 is formed on the polycrystalline silicon wiring layer 10, and the intersecting metal wiring layer 8 is formed thereon.

Also in this embodiment, the polycrystalline silicon wiring layer 10 is grounded and shielded from the intersecting metal wiring layer 8 by the lower P-type semiconductor substrate 1 and the upper ground metal wiring layer 6. .. Therefore, the voltage fluctuation of the digital signal passed through the metal wiring layer 8 does not affect the analog signal passed through the metal wiring layer 5 and the polycrystalline silicon wiring layer 10.

FIG. 3 is a plan view showing a third embodiment of the present invention. The cell 22 of the semiconductor integrated circuit 21 and the clock input / output pin 23 are connected by a wiring (hereinafter, referred to as a clock wiring) 24 for passing a clock signal, and the other signal input / output pin 25 and the cell 22 are connected by an analog signal. Connect with wiring 26. Further, narrow ground wirings 27 are provided on both sides of the clock wiring 24, and the ground wirings 27 are partially grounded.

According to this structure, the clock wiring 24 is shielded to the ground on both the left and right sides, so that even if a voltage fluctuation occurs in the clock signal, the analog signal passing through the adjacent analog wiring 26 on the outer side of the clock signal is not detected. There is no adverse effect. Further, even in the case of this wiring structure, at the time of placement and wiring, the wiring recognized as the clock wiring in the netlist (the distinction between the clock wiring and the wiring is that if the wiring is the clock wiring, If the placement / wiring means is made to recognize in advance by, for example, making the initial letter of the net name a certain character string, the ground wiring fixed to the ground potential can be arranged so as to always sandwich the clock wiring.

4A and 4B are views showing a fourth embodiment of the present invention. FIG. 4A is a plan view, and FIGS. 4B and 4C are sectional views taken along the lines CC and DD, respectively. Is. Semiconductor integrated circuit 21
In the place where the clock wiring 24 and the analog wiring 26 provided in the above are laminated, ground wirings are formed above and below the clock wiring 24. That is, as shown in FIGS. 2B and 2C, the clock wiring 24 formed in the insulating film 32 of the semiconductor substrate 31.
Ground metal wiring layer layers 33 and 34 are formed above and below, respectively, and the clock wiring 24 is vertically shielded by the ground metal wiring layers 33 and 34.

Therefore, even when the analog wiring 26 is arranged above the clock wiring 24 as shown in FIG. 2B, the analog wiring 26 is arranged below the clock wiring 24 as shown in FIG. Even when they are arranged, it is possible to prevent the voltage variation in the clock wiring 24 from affecting the analog signal of the analog wiring 26.

[0017]

As described above, according to the present invention, the ground wiring layer is formed on the upper side and the lower side of one wiring layer, and the other wiring layer is crossed on the upper side or the lower side thereof. One wiring layer is grounded shielded to the other wiring layer, and it is possible to prevent the voltage fluctuation of the digital signal on one wiring from affecting the analog signal on the other wiring. Further, since the ground wiring is provided along both sides of one wiring and the other wiring is adjacently arranged on the outer side of the one wiring, the ground shield is provided between one wiring and the other wiring provided outside, and the digital wiring is provided. The voltage fluctuation of the signal is prevented from affecting the analog signal. As a result, crosstalk between wirings can be suppressed even if the wirings are allowed to be crossed and adjacently arranged, and the degree of freedom in wiring design can be increased and high integration of semiconductor integrated circuits can be realized. is there.

[Brief description of drawings]

FIG. 1 shows a first embodiment of a wiring structure of the present invention, (a)
Is a plan view and (b) is a sectional view taken along line AA.

FIG. 2 shows a second embodiment of the wiring structure of the present invention, (a)
Is a plan view and (b) is a cross-sectional view taken along the line BB.

FIG. 3 is a plan view of a third embodiment of the wiring structure of the present invention.

FIG. 4 shows a fourth embodiment of the wiring structure of the present invention, (a)
Is a plan view, (b) is a sectional view taken along the line CC, and (c) is a sectional view taken along the line DD.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 Diffusion wiring layer 5 Metal wiring layer 6 Ground metal wiring layer 8 Metal wiring layer 24 Clock wiring 26 Analog wiring 27 Ground wiring 33, 34 Ground metal wiring layer

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which analog wirings for passing analog signals and digital wirings for passing digital signals are cross-arranged, and grounded wiring layers are formed above and below one of the wiring layers, A wiring structure for a semiconductor integrated circuit, characterized in that the other wiring layer is crossed above or below these ground wiring layers. 2. In a semiconductor integrated circuit in which an analog wiring for passing an analog signal and a digital wiring for passing a digital signal are arranged adjacent to each other, a grounded wiring is provided along both sides of the one wiring, and the other wiring is provided. A wiring structure of a semiconductor integrated circuit, which is arranged outside these ground wirings.