JPH03177066A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent malfunction from occurring due to crosstalk and enable an improved digital/analog hybrid circuit to be formed by placing a slit part at a power supply line or a ground line and by placing an analog signal line or a digital signal line into this slit. CONSTITUTION:A slit 92 for placing an analog signal line is formed between VSS ground lines 91 of a basic cell array. Then, analog input signal lines 11 and 11s of an analog cell 10 are connected to an I/O cell (IN) through slits 92 and 42 which are placed between the VSS ground line 91 of the basic cell array and a main VSS ground line 41. Thus, since the analog signal line 11 is shielded between the analog cell 10 and the I/O cell (IN) by the VSS lines 91 and 41, the line capacity is only Cg which is formed with the VSS line. Also, since a digital signal line 12 is always placed sandwiching the VSS line, mixture of noise from there can be prevented by the VSS lines 91 and 41.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and in particular to crosstalk when forming an analog/digital mixed circuit by applying a master slice method. Regarding the reduction of

(Prior Art) As shown in FIG.
lo) Human output (Ilo) cells 3 having pads 2 are disposed, and basic cells 6 consisting of transistors, resistors, etc. are regularly arranged as element regions with wiring channel regions 7 in between, and these element regions A master slicing method in which a desired circuit is formed by creating a wiring mask to connect the transistors and resistors as necessary, and connecting transistors and resistors to the VDD power supply line 8 and the vSS ground line 9 using wiring patterns. Semiconductor integrated circuit devices have become widely used.

In such a master slice type semiconductor integrated circuit device, a VDD power supply line 8 and a vSS ground line 9 made of a first aluminum layer are connected in parallel to each column of basic cells 4.
These VDD power supply lines 8
and VSS ground line 9 are connected via through-hole contacts 13 to main VDD power supply line 5 and VSS ground line 4, which are made of a second aluminum layer disposed around the periphery of the chip.

For example, when forming a circuit including analog cells 10 such as operational amplifiers, at least the signal line connecting between the input and output cells of the operational amplifier is the analog signal line 1.
1, therefore, in order to prevent crosstalk due to parasitic capacitance with other digital signal lines 12, it is necessary to avoid disposing digital signal lines that may be noise sources near the analog signal line. However, since the layout design of the gate array IC is performed by automatic placement and wiring processing by a computer, the wiring is routed without distinction between analog lines and digital lines, and as a result, the analog signal line 11 and the digital signal line
A proximal portion 14 may be formed.

Such close portions cause malfunctions due to crosstalk. For this reason, when a close portion 14 between the analog signal line 11 and the digital signal line 12 is created, a method is used in which the pattern data after automatic layout is manually corrected, but the wiring is complicated and it is difficult to determine a route change. Not only is this difficult, it takes a lot of time to correct it, and it also causes connection errors.

FIG. 2(a) and FIG. 2(b) are equivalent circuit diagrams of the circuit near the operational amplifier and a cross-sectional view of the part near the signal line. The shorter the distance between the aluminum layer and the thicker the thickness T of the aluminum layer, the larger the line capacitance C becomes, and the more easily crosstalk occurs.

In addition, in the case of automatic layout, if the horizontal direction is the first aluminum layer, the vertical direction is processed so that it becomes the second aluminum layer, so analog signal line 1 and digital signal line 12 are Although the first and second aluminum wiring layers intersect at right angles, crosstalk between the first and second aluminum wiring layers can be ignored because they are not extended while overlapping each other.

Furthermore, the line capacitance jlcl formed at the intersection with the second aluminum layer 15 also causes crosstalk, but generally there are few intersections and the intersection area is narrow, so the line capacitance ff1c+ can be ignored. I can do it.

Other parasitic capacitances include substrate 1 and analog signal line 1.
There is a capacitance Cf between 1 and 1. This is the board and VDD or V
Since this is capacitive coupling between the SS and SS, it affects the delay time regardless of crosstalk, and the line width W-2
µ, dielectric film thickness Tf'-1 µ as interlayer insulating film 16
It is known that a wiring length of L-101 has a capacitance of about 2 pF.

Considering the line capacitance C based on this, the line spacing D−
In 2μ countries, the aluminum film thickness is about T-1μm,
C-1/4. The capacitance was approximately Cr-0.5 pF, a value that could not be ignored in terms of crosstalk generation.

(Problem to be solved by the invention) As described above, in conventional gate array ICs, when attempting to incorporate digital and analog mixed circuits using the master slice method, the automatic layout randomly routes digital and analog signal lines. Due to the processing, it is not possible to restrict the route of analog signal lines or prohibit close wiring of thin wires, resulting in close proximity of digital and analog signal lines, resulting in crosstalk where digital signal noise mixes into analog signal lines. However, there was a problem that malfunctions occurred.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to prevent malfunctions due to crosstalk in a master slice type semiconductor integrated circuit device, and to form a good digital/analog mixed circuit.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, when realizing a digital/analog mixed circuit in a master slice type semiconductor integrated circuit device, at least one slit portion is provided in the power supply line or the ground line, and this An analog signal line or a digital signal bus line is disposed within the slit.

(Function) According to the above configuration, the routing paths of the analog signal line and the digital signal line are separated to prevent adjacent wiring and provide a noise shielding effect. digital·
It becomes possible to form an analog mixed circuit.

(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of wiring of a gate cell array according to an embodiment of the present invention. The configuration of the gate array is the same as the conventional example shown in FIG.
I10) Cells 3 are provided, and basic cells 6 consisting of transistors, resistors, etc. are regularly arranged as element regions with wiring channel regions 7 in between.

In this method, a VDD power supply line 81 of the basic cell column made of the first aluminum layer is provided in parallel to the column of each basic cell 4.
A slit 82 for arranging an analog signal line is formed between them. In addition, the vSS ground line 91 of the basic cell row
A slit 92 for arranging an analog signal line is also formed in between.

In addition, these VDD power supply line 81 and vSS ground line 91 are connected via through-hole contacts 13 to the main VDD power supply line 51 and vSS ground line 41 made of a second aluminum layer disposed around the periphery of the chip.
However, these VDD power supply line 51 and VSS ground line 41 are also connected to slits 42 and 5.
2 are formed over the entire circumference of the chip.

And analog human power signal line 1 of analog cell 10
1 and 11s are the vSS ground lines 91 of the basic cell row.
and is connected to the human output cell (IN) through slits 92 and 42 disposed between the main vSS ground line 41.

Here, the horizontal analog input signal line 11 is formed of a first aluminum layer, while the vertical analog input signal line 11s is formed of a second aluminum layer.

Here, 12 and 12s are digital signal lines arranged at arbitrary positions. However, analog human power signal line 11. VSS ground line 4 around IIs
1 and 81, other signal lines, ie, digital signal lines, are not placed close to each other.

During actual automatic layout, signal lines that are susceptible to crosstalk can be provisionally placed inside the slits before automatic layout processing is performed, or the wiring can be moved inside the slits after automatic layout. .

Figure 2 shows the equivalent circuit of the digital/analog mixed integrated circuit after wiring and the cross section of the analog signal line arrangement section (
a) and FIG. 2(b). Analog signal line 1
1 is shielded from the analog cell 10 to the human output cell (IN) by the vSS lines 91 and 41, so the line capacitance is only Cg formed between it and the Vss line.

Furthermore, since the digital signal line 12 is always placed across the Vss line, noise from there will not be mixed in with the Vss line.
This can be prevented by the s line 91.41. Note that Cn is the digital signal line 12 and the Vss line 91.
is the capacity between.

In this way, a digital/analog mixed integrated circuit with good characteristics and no crosstalk can be formed very easily.

Note that the analog signal lines are VDD lines 81 and 5.
A similar effect can be obtained by forming the slit 82.52 in the slit 82.52 formed in 1.

In addition, among the digital signal lines, clock signal lines and the like that are sources of noise are connected to the VDD lines 81 and 51.
It may also be formed within the slits 82, 52, 92, 42 formed within the vSS lines 91 and 41.

This shields the digital signal line, which is a source of noise, and prevents crosstalk with the analog signal line.

Further, the slit width may be any width that allows one line to be formed, and if necessary, a plurality of slits may be formed. The unused slit portion can also be used as part of the normal wiring area.

Thus, according to the present invention, it is possible to wire digital analog circuits using the master slice method while ensuring the characteristics of the analog circuits. In particular, when forming digital/analog mixed integrated circuits that include analog cells such as operational amplifiers, this problem can be easily prevented without requiring special technology or increasing the size of the chip, and provides design freedom. can greatly improve the degree of

Note that the cell arrangement and wiring are not limited to those shown in FIG. 1, and can be modified as appropriate without departing from the spirit of the present invention.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, at least one slit portion is provided in the power supply line or the ground line, and the analog signal line or digital signal line is provided within this slit. Therefore, it is possible to easily form a good digital/analog mixed circuit using automatic wiring without malfunctions due to the occurrence of crosstalk.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a gate array according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are cross-sectional views of an equivalent circuit and an analog signal line arrangement portion of the same digital/analog mixed integrated circuit, respectively. 3 is a diagram showing a conventional gate array, and FIGS. 4(a) to 4(b) are an equivalent circuit and a cross section of an analog signal line arrangement part of the same digital/analog mixed integrated circuit, respectively. FIG. 1... Board, 2... Input/output cell, 3... Input/output (
Ilo) Cell, 4...vSS ground line, 5...V
DD? K [line, 6...basic cell, 7...wiring channel region, 8...VDD power supply line, 9...
vSS ground line, 10... operational amplifier, 11. ll
s...Analog input signal line, 12.12s...
Digital signal line 13...Through hole contact, 14...Next part, 15...Second aluminum layer, 16...Interlayer insulating film, 41...VSS ground line, 42...Slit, 51...VDD power line, 52...Slit, 81...VI) DI source line 82...Slit, 91...VSS ground line, 92...Slit.

Claims (1)

[Claims] Basic cells each having at least a p-channel MOS transistor or an n-channel MOS transistor are arranged in a plurality of columns across a wiring region, and an analog circuit is formed in at least a part of the wiring region by master slice wiring, In a semiconductor integrated circuit device in which a digital circuit is formed using master slice wiring in another area, at least one slit is provided in the power supply line or the ground line, and an analog signal line or digital signal is inserted into the slit. A semiconductor integrated circuit device characterized in that a wire is arranged.