JPH0430452A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0430452A JPH0430452A JP13604090A JP13604090A JPH0430452A JP H0430452 A JPH0430452 A JP H0430452A JP 13604090 A JP13604090 A JP 13604090A JP 13604090 A JP13604090 A JP 13604090A JP H0430452 A JPH0430452 A JP H0430452A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- main wiring
- integrated circuit
- pair
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 230000000295 complement effect Effects 0.000 claims abstract description 24
- 230000002452 interceptive effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 46
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000010985 leather Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体集積回路装置に関し、特に高速性が要
求され且つ微細化配線構造を備えた半導体集積回路装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device that requires high speed performance and has a miniaturized wiring structure.
（従来の技術）
従来の半導体集積回路装置においては、クロック信号線
又はデータ配線は、単一層のアルミ配線等からなる導電
性層を用いて配線されていた。また、より高速性を必要
とする信号配線においては、容量結合等による信号波形
の劣化を防止するために、第４図の平面図及び第５図の
波形図に示すように、一対の信号を相補信号にして差動
信号にすることがある。(Prior Art) In conventional semiconductor integrated circuit devices, clock signal lines or data lines are wired using a conductive layer made of a single layer of aluminum wiring or the like. In addition, in signal wiring that requires higher speed, in order to prevent signal waveform deterioration due to capacitive coupling, etc., a pair of signals is Complementary signals may be used as differential signals.
第４図において、５１．５２は集積回路内の一対のクロ
ック信号配線又はデータ配線であって、５１は正相信号
線、５２は逆相信号線である。また、同図において、５
３．５４は他の一対のクロック信号線又はデータ配線で
あって、５３は正相信号線、５４は逆相信号線である。In FIG. 4, 51 and 52 are a pair of clock signal lines or data lines in the integrated circuit, 51 is a positive phase signal line, and 52 is a negative phase signal line. Also, in the same figure, 5
3.54 is another pair of clock signal lines or data lines, 53 is a positive phase signal line, and 54 is a negative phase signal line.
また、第５図は、上記信号線５１，５２，５３．５４の
波形図である。FIG. 5 is a waveform diagram of the signal lines 51, 52, 53, and 54.
尚、第４図においては、二対の信号配線しか示していな
いが、大容量メモリー集積回路やマイクロプロセッサに
おいては、多数の信号配線が同一基板上に配線されるこ
とになる。Although only two pairs of signal wirings are shown in FIG. 4, in large-capacity memory integrated circuits and microprocessors, a large number of signal wirings are wired on the same substrate.
（発明が解決しようとする課題）
しかるに、前記のような単一層の構成では、取り扱う信
号が益々高速になり且つ高集積化された半導体集積回路
においては、配線同士の間隔が短くなるに伴って、信号
同士が干渉して信号劣化が増大するという問題を有して
いる。(Problem to be Solved by the Invention) However, in the single-layer configuration as described above, in highly integrated semiconductor integrated circuits in which signals handled are becoming increasingly faster, as the spacing between interconnections becomes shorter, However, there is a problem in that signals interfere with each other and signal deterioration increases.
本発明はかかる点に鑑み、サブミクロン以下のデゼイン
ルールを用いる微細構造の集積回路の配線においても信
号同士が干渉を起こさず、これにより大容量メモリーや
高性能マイクロプロセッサ等におけるＬＳＩＣ大規模集
積回路）を実現するデータ配線方式を有する半導体集積
回路装置を提供することを目的とする。In view of this point, the present invention prevents signals from interfering with each other even in the wiring of integrated circuits with microstructures using design rules of submicron or less, thereby making it possible to prevent interference between signals (LSIC large-scale integrated circuits used in large-capacity memories, high-performance microprocessors, etc.) An object of the present invention is to provide a semiconductor integrated circuit device having a data wiring method that realizes the following.
（課題を解決するための手段）
前記の目的を達成するため、請求項（１）の発明は、一
対の相補信号配線の主要配線部分同士が上下の位置で互
いに並行に配線されている構成とするものである。(Means for Solving the Problem) In order to achieve the above object, the invention of claim (1) provides a configuration in which the main wiring portions of a pair of complementary signal wirings are wired in parallel to each other at upper and lower positions. It is something to do.
また、請求項（２）の発明は、請求項（１）の発明にお
いて、一対の相補信号配線の主要配線部分は二層導電性
配線構造に形成されている構成とするものである。Further, the invention of claim (2) is the invention of claim (1), in which the main wiring portions of the pair of complementary signal wirings are formed in a two-layer conductive wiring structure.
また、請求項（３）の発明は、請求項（１）の発明にお
いて、一対の相補信号配線の主要配線部分同士は少なく
とも１回捻転されて互いの位置が上下に交代している構
成とするものである。Further, the invention of claim (3) is the invention of claim (1), wherein the main wiring portions of the pair of complementary signal wirings are twisted at least once to alternate their positions vertically. It is something.
また、請求項（４）の発明は、信号配線の主要配線部分
と電源配線又はグランド配線の主要配線部分とが上下の
位置で互いに並行に配線されてなる一対の配線を備え、
該一対の配線の主要配線部分同士は少なくとも１回捻転
されて互いの位置が上下に交代している構成とするもの
である。Further, the invention of claim (4) includes a pair of wirings in which the main wiring part of the signal wiring and the main wiring part of the power supply wiring or the ground wiring are wired in parallel to each other at upper and lower positions,
The main wiring portions of the pair of wirings are twisted at least once so that their positions are alternated vertically.
さらに、請求項（５）の発明は、請求項（４）の発明に
おいて、一対の配線の主要配線部分は二層導電性配線構
造に形成されている構成とするものである。Furthermore, the invention of claim (5) is such that, in the invention of claim (4), the main wiring portions of the pair of wirings are formed in a two-layer conductive wiring structure.
（作用）
請求項（１）の発明の構成により、相補信号配線を少な
い配線領域で形成できるため、微細間隔を有する高密度
半導体集積回路における配線間の信号干渉という問題が
減少する。(Function) According to the structure of the invention as claimed in claim (1), complementary signal wirings can be formed in a small wiring area, so that the problem of signal interference between wirings in a high-density semiconductor integrated circuit having minute intervals is reduced.
請求項（３）の発明の構成により、半導体集積回路内の
クロック信号配線やデータ配線を容易にツイストペア線
の形にすることができるので、正相信号と逆相信号によ
るキャンセル効果を簡易に得ることができる。According to the configuration of the invention as claimed in claim (3), the clock signal wiring and data wiring in the semiconductor integrated circuit can be easily formed into twisted pair wires, so that the canceling effect of the positive phase signal and the negative phase signal can be easily obtained. be able to.
請求項（４）の発明の構成により、信号配線と電源配線
又はグランド配線とからなる一対の配線を少ない配線領
域で形成することかできるため、微細間隔を有する高密
度半導体集積回路における配線間の信号干渉という問題
が減少する。According to the configuration of the invention as claimed in claim (4), a pair of wirings consisting of a signal wiring and a power supply wiring or a ground wiring can be formed in a small wiring area, so that it is possible to form a pair of wirings consisting of a signal wiring and a power supply wiring or a ground wiring in a small wiring area. Signal interference problems are reduced.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図は本発明の一実施例に係る半導体集積回路装置の
構成図であって、第１図（ａ）はその平面構造、第１図
（ｂ）は第１図（ａ）におけるＩｂ−１ｂ線の断面構造
、第１図（Ｃ）は第１図（ａ）におけるＩｃ−１ｃ線の
断面構造を示している。FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, in which FIG. 1(a) shows its planar structure, and FIG. 1(b) shows the Ib- 1b line, and FIG. 1(C) shows the sectional structure taken along Ic-1c line in FIG. 1(a).
第１図において、１．３．７は上層の配線の主要部であ
る上層主要配線部分、２，４．８は下層の配線の主要部
である下層主要配線部分であって、５は上層主要配線部
分１と下層主要配線部分４とを接続するコンタクト部、
６は上層主要配線部分３と下層主要配線部分２とを接続
するコンタクト部である。また、同図において、９は半
導体基板であって、１０は配線同士の間及び配線と半導
体基板９との間を絶縁する酸化膜等の絶縁膜である。In Figure 1, 1.3.7 is the upper layer main wiring part which is the main part of the upper layer wiring, 2, 4.8 is the lower layer main wiring part which is the main part of the lower layer wiring, and 5 is the upper layer main wiring part. a contact portion connecting the wiring portion 1 and the lower main wiring portion 4;
Reference numeral 6 denotes a contact portion that connects the upper layer main wiring portion 3 and the lower layer main wiring portion 2. Further, in the figure, 9 is a semiconductor substrate, and 10 is an insulating film such as an oxide film that insulates between wirings and between the wirings and the semiconductor substrate 9.
第１図に示すように、上層主要配線部分１は下層主要配
線部分２の上側において該下層主要配線部分２と平行に
配線されており、上層主要配線部分３は下層主要配線部
分４の上側において該下層主要配線部分４と平行に配線
されている。そして、上層主要配線部分１はコンタクト
部５で下層主要配線部分４と接続されているため、信号
は上層主要配線部分１から下層主要配線部分４へと伝達
される。また、上層主要配線部分１の下側に配線されて
いた下層主要配線部分２はコンタクト部６で上層主要配
線部分３と接続されているため、信号は下層主要配線部
分２から上層主要配線部分３へと伝達される。As shown in FIG. 1, the upper layer main wiring portion 1 is wired above the lower layer main wiring portion 2 in parallel with the lower layer main wiring portion 2, and the upper layer main wiring portion 3 is wired above the lower layer main wiring portion 4. It is wired parallel to the lower main wiring portion 4. Since the upper main wiring section 1 is connected to the lower main wiring section 4 through the contact section 5, the signal is transmitted from the upper main wiring section 1 to the lower main wiring section 4. Further, since the lower layer main wiring portion 2 wired below the upper layer main wiring portion 1 is connected to the upper layer main wiring portion 3 at the contact portion 6, the signal is transmitted from the lower layer main wiring portion 2 to the upper layer main wiring portion 3. transmitted to.
このように、上層主要配線部分１と下層主要配線部分４
、及び下層主要配線部分２と上層主要配線部分３は互い
に一回捻転するツイストペア配線に形成されており、隣
接する信号配線同士の間に生じる容量結合による信号間
の干渉、或いは輻射による干渉は従来構造に比べて大幅
に減少する。In this way, the upper layer main wiring portion 1 and the lower layer main wiring portion 4
, the lower layer main wiring portion 2 and the upper layer main wiring portion 3 are formed into twisted pair wiring that is twisted once with respect to each other, and interference between signals due to capacitive coupling occurring between adjacent signal wirings or interference due to radiation is conventionally prevented. It is significantly reduced compared to the structure.
第２図は前記半導体集積回路装置を適用した第１具体例
の平面構成図である。同図において、１０１及び１０２
はφ１及び岡１の相補信号配線、１０３及び１０４はφ
ｚ、Ｊｚの相補信号配線、１０５及び１０６はφ３．革
３の相補信号配線であって、これら相補信号配線１０１
〜１０６はクロック配線或いはデータ配線を構成してい
る。FIG. 2 is a plan view of a first specific example to which the semiconductor integrated circuit device is applied. In the same figure, 101 and 102
is complementary signal wiring of φ1 and Oka 1, 103 and 104 are φ
Complementary signal wirings 105 and 106 of z and Jz are φ3. Complementary signal wiring of the leather 3, these complementary signal wiring 101
106 constitute clock wiring or data wiring.
第２図において、１０１を正相信号線とすると、１０２
は逆相信号線であって、正相信号線１０１と逆相信号線
１０２とは、上層と下層とにおいて交互に配線されてい
る。また、相補信号線１０３と１０４及び相補信号線１
０５と１０６も、相補信号線１０１と１０２と同様に配
線されている。In FIG. 2, if 101 is a positive phase signal line, then 102
is a negative phase signal line, and the positive phase signal line 101 and the negative phase signal line 102 are alternately wired in the upper layer and the lower layer. In addition, complementary signal lines 103 and 104 and complementary signal line 1
05 and 106 are also wired in the same way as complementary signal lines 101 and 102.
また、同図において、２１及び２５は正相信号線１０１
の上層主要配線部分、２３は逆相信号線１０２の上層主
要配線部分、２４は正相信号線１０１の下層主要配線部
分、２２及び２６は逆相信号線１０２の下層主要配線部
分であって、上層主要配線部分２１と下層主要配線部分
２４とはコンタクト部２７で、下層主要配線部分２２と
上層主要配線部分２３とはコンタクト部２８で、上層主
要配線部分２３と下層主要配線部分２６とはコンタクト
２９で、下層主要配線部分２４と上層主要配線部分２５
とはコンタクト部３０で各々接続されている。In addition, in the same figure, 21 and 25 are positive phase signal lines 101
23 is the upper layer main wiring portion of the negative phase signal line 102; 24 is the lower layer main wiring portion of the positive phase signal line 101; 22 and 26 are the lower layer main wiring portions of the negative phase signal line 102; The part 21 and the lower main wiring part 24 are connected to a contact part 27, the lower main wiring part 22 and the upper main wiring part 23 are connected to a contact part 28, the upper main wiring part 23 and the lower main wiring part 26 are connected to a contact part 29, Lower layer main wiring portion 24 and upper layer main wiring portion 25
are connected to each other through contact portions 30.
また、同図において、３１は正相信号線１０３の上層主
要配線部分、３２は正相信号線１０３の下層主要配線部
分、３３は逆相信号線１０４の上層主要配線部分、３４
は逆相信号線１０４の下層主要配線部分であって、上層
主要配線部分３１と下層主要配線部分３４とはコンタク
ト部３５で、下層主要配線部分３２と上層主要配線部分
３３とはコンタクト部３６で各々接続されている。Further, in the figure, 31 is an upper layer main wiring portion of the positive phase signal line 103, 32 is a lower layer main wiring portion of the positive phase signal line 103, 33 is an upper layer main wiring portion of the negative phase signal line 104, and 34
is the lower layer main wiring portion of the reverse phase signal line 104, the upper layer main wiring portion 31 and the lower layer main wiring portion 34 are connected to the contact portion 35, and the lower layer main wiring portion 32 and the upper layer main wiring portion 33 are connected to the contact portion 36, respectively. It is connected.
また、同図において、３７，３８，３９，４０゜４１．
４２．４Ｂ、４４．４５．４６は、各々相補信号線１０
５及び１０６の構成部分であって、相補信号線１０１及
び１０２の２１． ２２． ２３゜２４．２５，２６，
２７，２８，２９．３０と対応している。Also, in the same figure, 37, 38, 39, 40°41.
42.4B, 44.45.46 are complementary signal lines 10, respectively.
21.5 and 106 of complementary signal lines 101 and 102. 22. 23゜24.25,26,
27, 28, 29.30.
同図に示されているように、相補信号線１０１と１０２
、相補信号線１０３と１０４、相補信号線１０４と１０
５とが各々対になる配線を構成しており、互いに上下の
位置を交代してツイストペア配線を構成している。この
ため、一対の相補信号線の主要配線部分同士が上層から
下層へ、下層から上層へと交代する毎にコンタクト部を
２が所づつ独立して設けねばならず、２が所のコンタク
ト部からなるコンタクト領域を余分に必要とする。As shown in the figure, complementary signal lines 101 and 102
, complementary signal lines 103 and 104, complementary signal lines 104 and 10
5 constitute a pair of wires, and the upper and lower positions are alternated to form a twisted pair wire. For this reason, each time the main wiring portions of a pair of complementary signal lines are alternated from the upper layer to the lower layer and from the lower layer to the upper layer, contact portions 2 must be provided independently at each location, and 2 requires an extra contact area.
しかし、同図に示すように、コンタクト領域を千鳥状に
ずらして設けることにより、配線スペースは第４図に示
すような従来の単層構造に比べて４分の３で済む。However, as shown in the figure, by providing the contact regions in a staggered manner, the wiring space can be reduced to three-fourths of that in the conventional single-layer structure as shown in FIG.
第３図は前記半導体集積回路装置を適用した第２具体例
の平面構成図であって、同図において、１０７は信号配
線φ１．１０８は信号配線φ１と対になるグランド配線
、１０９は信号配線φ２．１１０は信号配線φごと対に
なるグランド配線、１１１は信号配線φ３．１１２は信
号配線φ３と対になるグランド配線である。また、第３
図における２１〜４６は第２図における２１〜４６と対
応する構成要素である。FIG. 3 is a plan configuration diagram of a second specific example to which the semiconductor integrated circuit device is applied, in which 107 is a signal wiring φ1, 108 is a ground wiring that pairs with the signal wiring φ1, and 109 is a signal wiring. φ2.110 is a ground wire that is paired with each signal wire φ, and 111 is a signal wire φ3.112 is a ground wire that is paired with signal wire φ3. Also, the third
21 to 46 in the figure are components corresponding to 21 to 46 in FIG. 2.
この第２具体例のように、一対の配線の一方をグランド
配線で構成したり、或いは交流的にグランドである電源
配線にすると、隣接信号間の容量結合による干渉の問題
については、ツイストペアを構成する一対の配線が相補
信号配線でないため正相信号と逆相信号によるキャンセ
ル効果は期待できないが、一方がグランド線であるため
にシールド効果が得られ、隣接信号への干渉が大幅に改
善できることになる。As in this second specific example, if one of the pair of wirings is configured with a ground wiring, or if the AC power wiring is grounded, the problem of interference due to capacitive coupling between adjacent signals can be solved by configuring a twisted pair. Because the pair of wires connected to each other are not complementary signal wires, we cannot expect a canceling effect between the positive and negative phase signals, but since one of the wires is a ground wire, a shielding effect can be obtained, and interference with adjacent signals can be significantly reduced. Become.
（発明の効果）
以上説明したように、請求項（１）〜（５）の発明に係
る半導体集積回路装置によると、信号配線を含む一対の
配線を少ない配線領域で形成できるため、微細間隔を有
する高密度半導体集積回路における配線間の信号干渉が
減少するので、高速信号の高密度配線で問題となるデー
タ信号やクロック信号の劣化を防止することができる。(Effects of the Invention) As explained above, according to the semiconductor integrated circuit device according to the invention of claims (1) to (5), a pair of wirings including signal wirings can be formed in a small wiring area, so that fine intervals can be reduced. Since signal interference between wirings in a high-density semiconductor integrated circuit having the present invention is reduced, it is possible to prevent deterioration of data signals and clock signals, which is a problem in high-density wiring for high-speed signals.
このため、請求項（１）〜（５）の発明は、これからの
時代に対応する大容量メモリや高性能マイクロプロセッ
サ及びゲートアレイ等の大規模半導体集積回路の高性能
化を実現することができるので、その実用的効果は極め
て大きい。Therefore, the inventions of claims (1) to (5) can realize high performance of large-scale semiconductor integrated circuits such as large-capacity memories, high-performance microprocessors, and gate arrays that are compatible with the coming era. Therefore, its practical effects are extremely large.
さらに、請求項（３）及び（４）の発明によると、二層
配線を利用したツイストペア線を少ない配線領域で形成
することができるため、微細間隔を有する高密度半導体
集積回路における配線間の信号干渉が一層減少し、デー
タ信号やクロック信号の劣化を一層防止できる。Furthermore, according to the inventions of claims (3) and (4), twisted pair lines using two-layer wiring can be formed in a small wiring area, so that signals between wirings in a high-density semiconductor integrated circuit having fine spacing can be formed. Interference is further reduced, and deterioration of data signals and clock signals can be further prevented.
第１図（ａ）〜（ｃ）は本発明の一実施例に係る半導体
集積回路装置を示し、（ａ）は平面図、（ｂ）は（ａ）
におけるＩｂ−Ｉｂ線断面図、（ｃ）は（ａ）における
Ｉｃ−１ｃ線断面図、第２図は前記一実施例を適用した
第１具体例の平面構成図、第３図は前記一実施例を適用
した第２具体例の平面構成図、第４図は従来の半導体集
積回路装置における配線を示す平面構成図、第５図は相
補信号配線の波形図である。
１．３．７・・・上層主要配線部分
２．４．８・・・下層主要配線部分
５．６−・・コンタクト部
９・・・半導体基板
１０・・・絶縁膜FIGS. 1(a) to 1(c) show a semiconductor integrated circuit device according to an embodiment of the present invention, in which (a) is a plan view, and (b) is a plan view of FIG.
(c) is a cross-sectional view taken along line Ic-1c in (a), FIG. 2 is a plan configuration diagram of a first specific example to which the above embodiment is applied, and FIG. 3 is a cross-sectional view taken along line Ic-1c in (a). FIG. 4 is a plan configuration diagram showing wiring in a conventional semiconductor integrated circuit device, and FIG. 5 is a waveform diagram of complementary signal wiring. 1.3.7... Upper layer main wiring part 2.4.8... Lower layer main wiring part 5.6-... Contact part 9... Semiconductor substrate 10... Insulating film
Claims (5)
位置で互いに並行に配線されていることを特徴とする半
導体集積回路装置。(1) A semiconductor integrated circuit device characterized in that main wiring portions of a pair of complementary signal wirings are wired in parallel to each other in upper and lower positions.
電性配線構造に形成されていることを特徴とする請求項
（１）に記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the main wiring portions of the pair of complementary signal wirings are formed in a two-layer conductive wiring structure.
なくとも１回捻転されて互いの位置が上下に交代してい
ることを特徴とする請求項（１）に記載の半導体集積回
路装置。(3) The semiconductor integrated circuit device according to claim 1, wherein the main wiring portions of the pair of complementary signal wirings are twisted at least once so that their positions are alternated vertically.
配線の主要配線部分とが上下の位置で互いに並行に配線
されてなる一対の配線を備え、該一対の配線の主要配線
部分同士は少なくとも１回捻転されて互いの位置が上下
に交代していることを特徴とする半導体集積回路装置。(4) A pair of wiring is provided in which the main wiring part of the signal wiring and the main wiring part of the power supply wiring or ground wiring are wired in parallel to each other in upper and lower positions, and the main wiring parts of the pair of wirings have at least one A semiconductor integrated circuit device characterized in that it is rotated and its positions alternate vertically.
構造に形成されていることを特徴とする請求項（４）に
記載の半導体集積回路装置。(5) The semiconductor integrated circuit device according to claim 4, wherein the main wiring portions of the pair of wirings are formed in a two-layer conductive wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13604090A JPH0430452A (en) | 1990-05-25 | 1990-05-25 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13604090A JPH0430452A (en) | 1990-05-25 | 1990-05-25 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430452A true JPH0430452A (en) | 1992-02-03 |
Family
ID=15165775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13604090A Pending JPH0430452A (en) | 1990-05-25 | 1990-05-25 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430452A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236704A (en) * | 1995-02-28 | 1996-09-13 | Nec Kyushu Ltd | Semiconductor intergrated circuit |
| JP2008244179A (en) * | 2007-03-27 | 2008-10-09 | Nec Corp | Multilayer wiring board |
| JP2014013794A (en) * | 2012-07-03 | 2014-01-23 | Canon Inc | Solid state image pickup device and camera |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202941A (en) * | 1987-02-18 | 1988-08-22 | Nec Corp | Wiring path for semiconductor device |
| JPH0215655A (en) * | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | Semiconductor device |
-
1990
- 1990-05-25 JP JP13604090A patent/JPH0430452A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202941A (en) * | 1987-02-18 | 1988-08-22 | Nec Corp | Wiring path for semiconductor device |
| JPH0215655A (en) * | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236704A (en) * | 1995-02-28 | 1996-09-13 | Nec Kyushu Ltd | Semiconductor intergrated circuit |
| JP2008244179A (en) * | 2007-03-27 | 2008-10-09 | Nec Corp | Multilayer wiring board |
| JP2014013794A (en) * | 2012-07-03 | 2014-01-23 | Canon Inc | Solid state image pickup device and camera |
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