KR20000003885A - Semiconductor devices having decoupling capacitor - Google Patents

Abstract

PURPOSE: A semiconductor device having decoupling capacitor is provided to increase a capacitance of the decoupling capacitor formed between power wires of multi-layer package). CONSTITUTION: The layout of the decoupling capacitor comprises: a semiconductor substrate(200); a plurality of insulating layers(20a,20b,20c) arranged in a row direction on the semiconductor substrate(200); a plurality of metal layers(22) used as a first power wire and arranged between the insulating layers(20a,20b,20c); and a plurality of metal layers(24) used as a second power wire and arranged between the insulating layers and the first power wire, wherein the width between the first and the second power wires(22,24) is smaller than the height of the insulating layers(20a,20b,20c).

Description

SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR

The present invention relates to a decoupling capacitor, and more particularly to a decoupling capacitor formed between power wires on a multi layer package.

As VLSIs become faster and the density of semiconductor memory devices and the number of input and output pins increase, noise on power lines increases. Decoupling capacitors are often used in semiconductor packages to reduce noise in the power lines. The decoupling capacitance between the supply and ground can reduce transient voltage transients in the supply. The transient voltage is generated by current spikes generated when transistors in a semiconductor circuit are switched on or off. The closer the decoupling capacitor is to the chip, the greater the effect. In addition, a technology for embedding a decoupling capacitor inside the chip is also used.

FIG. 1 is a view showing a layout structure inside a chip, in which there are a circuit area where a circuit is formed and an unused area, and power and ground lines are formed in different layers around the areas. In addition, pads are shown to connect the internal and external signals.

The decoupling capacitor may be formed using a transistor or a metal film in a region not used in the chip, or may be formed in a corner region of the chip. Thus, forming a capacitor inside the chip must have a region that is not used for other purposes as long as the capacitor can be formed.

If the size of the chip is increased to form the capacitor inside the chip, the manufacturing cost increases. In addition, since the corner area in the chip is often used as an area for storing information of a block or chip, it is difficult to set a fixed area for a decoupling capacitor. One of the other methods is formed in parallel with the package outside the chip, but this also increases the manufacturing cost.

Referring to FIG. 1, A is a circuit area, B is an unused area, C is a power line, and D is an I / O pad area. D serves to connect the power distribution of the entire chip and the signal between the outside and inside of the chip. The power and ground metal rings use wide metals because they carry large amounts of current. The metal ring is then connected directly to an external power supply and ground pin.

FIG. 2 is a cross-sectional view illustrating the structure of D in detail, in which a plurality of insulating layers 10a, 10b and 10c are arranged on a semiconductor substrate 100, and between the insulating layers 10a, 10b and 10c. The metal layers 12, 14, 16 to which the power supply and the ground voltage are supplied are arranged. Above and below each metal layer, metal layers to which the same power is supplied are arranged. In addition, C _T of FIG. 2 serves as a decoupling capacitor by overlapping the metal layers using the power and ground voltages on the upper and lower portions of the metal layers with each metal layer interposed therebetween.

However, the decoupling capacitor formed as described above increases as the power and ground lines overlap, but the process technology is increasing the distance between the metal layers in order to reduce the parasitic capacitance between the metal layers. This causes a problem that the value of the decoupling capacitor is reduced.

It is an object of the present invention to provide a layout structure for forming a decoupling capacitor inside a chip without increasing manufacturing costs.

1 shows a layout of a semiconductor device viewed from above;

2 is a partial cross-sectional view of a package according to the prior art;

3 is a cross-sectional view of a package according to the present invention;

4 is a partial cross-sectional view of a package according to the present invention.

* Explanation of symbols on main parts of the drawings

100 and 200: semiconductor substrate 22: first power line

24: second power line

(Configuration)

According to an aspect of the present invention, a decoupling capacitor includes a semiconductor substrate, a plurality of insulating layers arranged on the semiconductor substrate, and a plurality of first power supply metal layers arranged between the insulating layers. And a plurality of second power supply metal layers arranged between the insulating layers and between each of the first power supply wires, wherein a width between the first and second power supply metal layers arranged on the insulating layer is insulated from each other. It is relatively smaller than the height of the layers.

In a preferred embodiment, the second power supply metal layers are arranged on both sides of the first power supply metal layers with the insulating layers spaced apart from each other.

In a preferred embodiment, the first power supply metal layers are arranged on both sides of the second power supply metal layers, and the first power supply metal layers are disposed on both sides of the second power supply metal layers.

According to another feature of the invention, the decoupling capacitor layout structure is a semiconductor substrate, a plurality of insulating layers arranged on the semiconductor substrate, a plurality of first power wires arranged between the insulating layer, the insulating layers And second power wires arranged between the first power wires with a width relatively smaller than each height.

With this structure, the decoupling capacitor can be increased only by adjusting the distance between the power supply and the ground line.

(Example)

Hereinafter, the present invention will be described with reference to FIGS. 3 and 4.

Referring to FIG. 4, the present invention forms a decoupling capacitor using a metal layer ring for power and ground. With the development of process technology, the thickness of the insulating layer is made thick to reduce the parasitic capacitance, and the capacitance between the metal layers between the metal layers is getting smaller. Therefore, according to the present invention, there is provided a decoupling capacitor using a metal layer as an electrode for power and ground.

3 shows an arrangement of metal layers for forming a decoupling capacitor in a chip according to the invention. Insulating layers 20a, 20b, 20c are disposed on the semiconductor substrate 200 and the metal layer used as the first and second power wires 22, 24 between the insulating layers 20a, 20b, 20c. Are placed alternately.

4 is a cross-sectional view of FIG. 3 in accordance with the present invention.

Referring to FIG. 4, a plurality of insulating layers 20a, 20b, and 20c are arranged in a column direction in an I / O pad area on the semiconductor substrate 200. Metal layers 22 and 24 used as first and second power wires are alternately arranged between the insulating layers 20a, 20b and 20c. In this case, the power supplies are power and ground voltage.

Hereinafter, the structure of the decoupling capacitor according to the present invention will be described in detail with reference to three insulating layers. Insulating layers 20a, 20b, and 20c are arranged in the transverse direction. Metal layers 22 for a first power source are arranged between the insulating layers 1a, 1b and 1c. The metal layers 24 for the second power source are arranged between the metal layers 22 for the first power source. The metal layers 24 for the second power source are arranged at both sides with a predetermined distance on the basis of the metal layer 24 for the second power source arranged between the insulating layers 20b and 20c (1b), and the insulating layers 20b and 20c are arranged. The metal layer 22 for the first power source is also arranged on the upper and lower sides with the gap therebetween. That is, the periphery of the metal layer 24 for the second power source is surrounded by the metal layers 22 for the first power source. On the contrary, even with reference to the metal layer 22 for the first power source, the metal layer 24 for the second power source is surrounded on both sides and above and below.

Metal layers 22 and 24 for the first and second power sources are used as electrodes of the capacitor to serve as decoupling capacitors. The metal layers for the first and second power sources are different metal layers.

Referring to FIG. 4, Ls is a gap between first and second power supply metal layers adjacent to the same layer and Lt represents a thickness of an insulating layer. Cud is the capacitance between the insulating layers, and Clr is the capacitance between the same power supply metal layers. When arranging the insulating layer in the chip, the once defined Lt is difficult to change again. On the contrary, since Ls is a gap between the power metal layers, it can be made sufficiently small, so that Clr is generally larger than Cud. The present invention can provide a decoupling capacitor more than twice as large as compared with the case of considering only capacitance between metal layers for insulation, in addition to capacitance between upper and lower capacitances between adjacent metal layers on the same layer.

As described above, when the decoupling capacitor is formed using the metal layers using different power sources on the same insulating layer, the spacing between the metal layers should be more secured than in the prior art. Securing the spacing between the metal layers is not a big problem because the I / O area is going to increase the trend.

According to the present invention, as the metal layers using different power sources are alternately arranged up, down, left and right, high capacitance can be obtained.

Claims (4)

A semiconductor substrate; A plurality of insulating layers arranged on the semiconductor substrate; A plurality of first power metal layers arranged between the insulating layers; A plurality of second power supply metal layers arranged between the insulating layers and between each of the first power supply wires, A decoupling capacitor layout structure in which a width between the first and second power supply metal layers arranged on the insulating layer is relatively smaller than a height of each of the insulating layers. The method of claim 1, A decoupling capacitor layout structure in which the second power supply metal layers are arranged on both sides of the first power supply metal layers with the insulating layers spaced apart from each other by a predetermined width. The method of claim 1, A decoupling capacitor layout structure in which the first power supply metal layers are arranged on both sides of the second power supply metal layers, respectively, on both sides of the second power supply metal layers with the insulating layer spaced apart from each other. A semiconductor substrate; A plurality of insulating layers arranged on the semiconductor substrate; A plurality of first power wires arranged between the insulating layers; And a second power wire arranged between the first power wires with a width relatively smaller than a height of each of the insulating layers.