JPS61270849A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring capacity by a method wherein a floating conductor layer not directly impressed with potential is provided between the first wiring conductor layer and the second wiring conductor layer. CONSTITUTION:A floating conductor 16, an upper layer wiring 15 are formed on an Si substrate 11. Assuming the parasitic capacity per unit length to be CA between the wiring 15 and the conductor 16 and CB between the conductor 16 and the substrate 11, the total parasitic capacity of wiring 15 shall be CAXCB /(CA+CB), making it feasible to reduce the parasitic capacity of wiring 15 by restricting the width of conductor 15 to 10mum or less to accelerate an IC device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present BA relates to integrated circuit devices, and particularly to a method for laying wiring thereof.

[Conventional technology]

Generally, an integrated circuit device is composed of a plurality of semiconductor chips formed on a semiconductor substrate and wiring interconnecting the plurality of semiconductor elements. In conventional integrated circuits, the size of individual semiconductor elements is relatively large, and the wiring interconnecting these multiple semiconductor elements is also relatively small.
M@ thick wiring is used. This is because the formation of wiring patterns on a semiconductor substrate is determined by constraints on manufacturing technology and process technology.

The parasitic capacitance of semiconductor elements used in conventional integrated circuit devices is large, and the operating speed of basic circuits constructed using semiconductor elements with such large parasitic capacitances is relatively slow, and the wiring Due to the large width, the parasitic capacitance of the wiring was large, and the delay due to the parasitic capacitance of the wiring was also relatively large.

In recent years, advances in fabrication technology and process technology have enabled even finer processing of semiconductor elements in wire integrated circuit devices. By using this microfabrication technique, it is possible to reduce the size of the hemispherical elements, and it is possible to reduce the parasitic capacitance of each hemispherical element. Similarly, it is possible to narrow the wiring width of the wiring interconnecting semiconductor elements, which reduces the parasitic capacitance per unit length of the wiring. The operating speed is relatively fast and the delay due to parasitic capacitance of wiring is relatively small. However, as the operating speed of semiconductor elements themselves becomes faster and faster, the delay due to the parasitic capacitance of wiring becomes relatively larger, and it is becoming difficult to increase the operating speed of integrated circuit devices. There is.

[Problems that the invention attempts to solve]

For this reason, there is an increasing need to reduce the parasitic capacitance of wiring, and the general method for reducing the parasitic capacitance of wiring is to reduce the width of the wiring. Shorten the wiring length. The thickness of the interlayer insulating film of the eight wires is increased to widen the mutual spacing between the wires. There are four methods that use a material with a low dielectric constant for the interlayer insulating film. Problems with each method are discussed below.

The first method of narrowing the wiring width is a method that has become possible due to advances in manufacturing technology.As in the past, when the wiring width is relatively thick, K is dominated by the parasitic capacitance on the bottom or top surface of the wiring. There is almost no need to consider the side capacitance due to the edge effect of the wiring, and as the wiring width is made thinner, the parasitic capacitance of the wiring decreases in approximately proportion to the rate of thinning. As the wiring width becomes thinner and the parasitic capacitance on the bottom or top surface of the wiring decreases, the parasitic capacitance on the sides due to the edge effect of the wiring will appear relatively larger. Even if the unit length is increased, the parasitic capacitance of the O wiring does not decrease. The influence of the parasitic capacitance on the side surface of the wiring will be explained using a specific example.

FIG. 3 is a cross-sectional view of a conventional wiring without using the present invention. The second interlayer insulating film, 35 is the wiring of interest, and 34 is a protective film. Although not shown in Figure 3, it is assumed that another wiring or resistor is arranged between the THL interlayer insulating film 32 and the second interlayer insulating film 33 to form a circuit. still.

A semiconductor substrate is a general term that also includes an epitaxial layer.

In Figure 3, 1. Second interlayer Ij7 & film 3233
The film thickness was reduced to 05 μm%, respectively.1. Second interlayer insulating film 3
2,330 relative permittivity both 4.0 wiring width 35
If the capacitance of the wiring per unit length is taken as the standard value when the length of the wiring 35 is 1 μm, the wiring width of the wiring 35 is 1.6
When all other conditions are the same, the parasitic capacitance of a wire with a unit length is reduced by 23% compared to the reference value, and when the width of the wire 35 is 1 μm and all other conditions are the same, The parasitic capacitance of long wiring is 33% compared to the standard value.
It only decreases. Even if the wiring width of the wiring is reduced in this way, the rate of decrease in the parasitic capacitance of the wiring due to the side capacitance due to the edge effect of the wiring is small compared to the rate of decrease in the wiring width. As processing technology advances and the wiring width of the wiring can be made even thinner, the wiring width will be further reduced so that it does not significantly contribute to reducing the parasitic capacitance of the wiring.

Also, if the power consumption is low, such as in a circuit made up of MOS (MOS) transistors, there is no harm in making the wiring width thinner, but it is a pibora transistor.

In cases where there is a large amount of dissipation force, such as in a circuit composed of stars, it is necessary to maintain the current density flowing through the wiring below a certain value, so if the wiring width is made thinner, there will be a limit to K. It is difficult to reduce the parasitic capacitance of the wiring by narrowing the width of the wiring.

The method of shortening the wiring length of the second wiring is an effective method within an integrated circuit device, especially in the case of products where circuit parts that are subject to increased speed can be laid out so that the wiring length is shortened. However, due to the circuit configuration, it may not be possible to shorten the length of the wiring for master slice products that are available in multiple products by changing the wiring process.

The third method of increasing the thickness of the interlayer insulating film is that the step of the contact opening for connecting the semiconductor element and the wiring formed on the semiconductor substrate becomes steep, making the wiring more likely to break. Reliability issues arise. Alternatively, it becomes necessary to use a new process technique such as providing a taper around the contact opening in order to reduce the level difference in the contact opening.

The method of using a material with a low dielectric constant for the 40th interlayer insulating film is as follows:
At present, many interlayer insulating films with low dielectric constants have reliability problems such as insulation, moisture resistance, heat resistance, etc., and are not suitable for practical use.

[Means for solving problems]

In particular, the present invention aims to reduce the parasitic capacitance of interconnects without making any changes in manufacturing technology or process technology, thereby reducing the delay due to the parasitic capacitance of interconnects and achieving higher speed integrated circuit devices. It is something.

Unexploded BA Hiro A third conductor (hereinafter referred to as a floating conductor) to which a potential is not directly applied to the third wiring layer between the first conductor of the first wiring layer and the second conductor of the second wiring layer. do.

) [Examples] The present invention will be described below using Examples. FIG. 1 shows an embodiment in which the present invention is used. jollij: semiconductor substrate, 12 and 12 are the first . Second interlayer & membrane, 15
is the wiring of interest, and 16 is a floating conductor.

As shown in Figure 1, the floating conductor 16 exists between the wiring 15 and the semiconductor substrate 11, so the parasitic capacitance between the wiring 15 and the semiconductor substrate 11 is equivalent to If the parasitic capacitance per unit length between the wiring conductor 15 and the 70-ring conductor 16 is C, and the parasitic capacitance per unit length between the floating conductor 16 and the semiconductor substrate 11 is CII, then CA@ The total parasitic capacitance of the CI wiring 150 is "per unit length" = CA + CB. In FIG.
The film thickness of 3 was 0.5 μm%, respectively. The first and second interlayer insulating films were 12.130 and the dielectric constants were both 4.0. When the width of the wiring @15 is 3 μm, the thickness of the wire 15 is 1 μm, the width of the floating conductor 16 is 3 μm, and the thickness of the floating conductor 16 is 1 μm, the unit long time is 3 μm compared to the standard value when the present invention is not used. The parasitic capacitance of the wiring is reduced by 30%, and furthermore, when the wiring width of placement 1115 is 1.0 μm and all other conditions are the same, the parasitic capacitance of the unit length of wiring @15 is reduced by 40%. ing.

〔Effect of the invention〕

As described above, when the present invention is used, the parasitic capacitance of wiring can be reduced compared to the case where the present invention is not used.

Furthermore, as shown in FIG. 4, the floating conductor 46 should not be placed around the contact opening between the wiring 45 and the semiconductor element 47 on the semiconductor substrate. 1st with the case where it is not used. If the film thicknesses of the second interlayer insulating films are the same, the height differences in the contact openings will be the same, but by using the present invention, the height difference in the contact openings will be particularly steep. This will prevent the wiring from breaking. Further, since no current flows through the floating conductor, a polysilicon resistor or the like may be used instead of the metallic material.

As explained in detail above, unexploded BAK deflection can reduce the parasitic capacitance of the wiring per unit length, so the delay due to the parasitic capacitance of the wiring is reduced, and the speed of the integrated circuit device can be increased.
Moreover, compared to conventional manufacturing techniques, no special manufacturing process is required.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of wiring using the present invention, Figure 2 is an equivalent circuit diagram of Figure 1, Figure 3 is a cross-sectional view of wiring that does not use the present invention, and Figure 4 is a cross-sectional diagram of wiring using the present invention. FIG. 2 is a cross-sectional view of a connection portion between wiring and a semiconductor element on a semiconductor substrate. 11.31.41... Semiconductor substrate, -12,3
2,42...First interlayer 111! ! lamina, 13
,33.43...IK2 interlayer insulating film, 14,
34.44...Protective film%15゜35.45...
...K-line, 16.46...Floating conductor, 47...Semiconductor element formed on semiconductor substrate, C-line...Connection between wiring and floating conductor Capacitance per unit length, CB: Capacitance per unit length between the 70-ring conductor and the semiconductor substrate. Agent: Patent attorney Susumu Uchihara 7゛.
X〈No. Jl! 1

Claims (4)

[Claims] (1) The first conductor of the first wiring layer and the second conductor of the second wiring layer
An integrated circuit device characterized in that there is a third conductor to which a potential is not directly applied to a third wiring layer between the conductor and the third conductor. (2) The integrated circuit device according to claim 1, wherein the first conductor is a semiconductor substrate. (3) The integrated circuit device according to claim 1, wherein the width of the third conductor is less than 10 μm. (4) The integrated circuit device according to claim 2, wherein the width of the third conductor is less than 10 μm.