JPH07263631A - Wiring structure of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make small the area, which is occupied by power wirings, by a method wherein a plurality of the power wirings for conducting a power supply to a hard macro consisting of a plurality of elements on a semiconductor substrate are formed in parallel to each other on the same layer along the outer periphery of the hard macro. CONSTITUTION:A first power-supply ring 2, which is used as a power wiring, is formed on the outer periphery of a hard macro 1 and a second power-supply ring 3, which is used as a power wiring, is formed on the outer periphery of the ring 2. The rings 2 and 3 are respectively formed on a first wiring layer which is the lowest wiring layer on a semiconductor substrate 5. The rings 2 and 3 are respectively formed in a wiring width W1, the interval between the rings 2 and 3 is a prescribed interval (alpha) and the rings 2 and 3 are formed in parallel to each other. The prescribed width (c() is a width, in which the rings 2 and 3 do not come into contact to each other in a manufacturing process or the like, and is formed narrower than the wiring width W1 of the rings 2 and 3. Thereby, the area, which is occupied by a power-supply ring 4 consisting of the rings 2 and 3, is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit device, and more particularly to a power wiring structure.

In recent years, in a system using a semiconductor integrated circuit device such as a computer, it has been required to speed up the system and shorten a development period. In response to the demand, the semiconductor integrated circuit device can be speeded up and highly integrated. Fast delivery is desired. Then, speeding up, high integration of the semiconductor integrated circuit device,
Standard cells, gate arrays, and the like are prepared in order to shorten the delivery period, and standard cells are used in fields where higher speed and higher integration are required. In this standard cell, cells other than the standard cells prepared in advance are prepared as custom cells called hard macros to meet system requirements. by the way,
Since this hard macro is generally larger than an ordinary cell, it is required to design the power supply wiring in consideration of its size and layout position.

[0003]

2. Description of the Related Art FIG. 5 is a plan view showing a chip of a semiconductor integrated circuit device. A plurality of standard cells 11 are arranged on the chip 10. The standard cell 11 is a plurality of circuit elements (for example, an inverter circuit) prepared in advance, and a semiconductor integrated circuit device is configured by connecting and combining the standard cells 11 with wiring (not shown).

A hard macro 12 is provided on the chip 10.
Are arranged. The hard macro 12 is a cell pre-designed with a plurality of circuit elements other than the standard cell 11 according to user's request, etc.
It is formed larger than 1. A power ring 13 for supplying power to the hard macro 12 is provided around the hard macro 12. By designing the power supply system in the hard macro 12 in the power supply ring 13, the power supply design is simplified and the delivery time of the semiconductor integrated circuit device is shortened. The structure of the power supply ring 13 is shown in FIGS.

FIG. 4 shows a hard macro 12 and a power supply ring 1.
It is a top view which shows 3. The hard macro 12 is designed to be driven by, for example, the high potential side power source Vcc and the low potential side power source Vss, and the high potential side power source Vcc and the low potential side power source Vss.
The first and second power supply rings 14 and 15 are provided corresponding to the above. Both power supply rings 14 and 15 have a multi-layer wiring structure in accordance with higher integration of semiconductor integrated circuit devices.

FIG. 3 is a partial cross-sectional view of both power supply rings 14 and 15. A plurality of wiring layers are provided on the semiconductor substrate 16. The first power ring 14 is formed on the first wiring layer. A second power supply ring 15 is formed as a second wiring layer on the first power supply ring 14 with an insulating layer 17 interposed therebetween. And both power supply wiring 14,
Reference numeral 15 is connected to the hard macro 12 via a wiring (not shown), and supplies the high potential side power source Vcc and the low potential side power source Vss to the hard macro 12.

In both power supply rings 14 and 15, as wiring layers formed during the manufacture of a semiconductor integrated circuit device become upper layers, steps are formed in the wiring. That is, a step is formed on the surface of the insulating layer 17 by the first power supply ring 14 formed on the first wiring layer. As a result, there occur portions where the thickness of the second power supply ring 15 of the second wiring layer is different. That is, in FIG. 3, the thickness B of the second power supply ring 15 is smaller than the thickness A of the flat portion and the thickness B of the stepped portion.

Generally, the coverage rate of the wiring is represented by the ratio of the film thickness B of the step portion to the film thickness A of the flat portion thereof.
The coverage ratio C2 of the second power supply ring 15 is represented by C2 = (B / A) × 100 (%) by the film thickness A of the flat portion and the film thickness B of the step portion, and is formed in the second wiring layer. The second power ring 1
5 is 30%, for example, the first power ring 14 formed in the first wiring layer is the semiconductor substrate 1
Since it is formed on No. 6, the thickness is constant and the coverage ratio C1 is 100%. If a third power ring is formed on the second wiring layer via an insulating layer on the second wiring layer, the coverage rate of the third power ring is, for example, about 20%.

[0009]

The wiring widths W1 and W2 of both power supply rings 14 and 15 are determined so as not to exceed a preset current density. That is, if the wiring has a thin portion, the width is widened so as not to exceed a predetermined current density according to the thickness. Therefore, if the coverage ratio C2 of the second power supply ring 15 is 30%, the wiring width W2 of the second power supply ring 15 needs to be about three times the wiring width W1 of the first power supply ring 14. To do. Therefore, the width W2 of the power supply ring 13 is determined by the second power supply ring 15, and W2 = 3 × W1.

If the third power supply ring is formed, its wiring width is 5 times the wiring width W1 of the first power supply ring 14 if its coverage ratio is 20%. Then, the width W2 of the power supply ring 13 is determined by the third power supply ring, and W2 = 5 × W1. Therefore, it is necessary to increase the wiring width of the power supply ring as the layers are stacked. As a result, the area required for forming the power supply ring is increased, which is a problem in achieving high integration of the semiconductor integrated circuit device.

The present invention has been made to solve the above problems, and an object thereof is to provide a wiring structure of a semiconductor integrated circuit device in which an area occupied by a power supply wiring can be reduced.

[0012]

In order to achieve the above object, the present invention provides a plurality of power wirings for supplying power to a hard macro 1 formed on a semiconductor substrate 5 and composed of a plurality of predesigned elements. The gist is that the layers 2 and 3 are formed in parallel in the same layer along the outer periphery of the hard macro 1.

[0013]

Therefore, according to the present invention, a plurality of power supply wirings 2,
3 are formed in parallel in the same layer along the outer periphery of the hard macro 1 and no step is formed in the wiring, so that the power supply wirings 2 and 3 have a constant thickness. The coverage rate of each power supply wiring 2 and 3 is 100%.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to FIGS. For the sake of convenience of explanation, the same components as those shown in FIG.

As shown in FIG. 2, a first power supply ring 2 as a power supply wiring is formed on the outer periphery of the hard macro 1.
A second power supply ring 3 as a power supply wiring is formed on the outer periphery of the first power supply ring 2. A power supply ring 4 is formed by the first and second power supply rings 2 and 3.

The first and second power supply rings 2 and 3 are shown in FIG.
As shown in FIG. 5, they are respectively formed on the first wiring layer which is the lowermost wiring layer on the semiconductor substrate 5. Therefore, since the first and second power supply rings 2 and 3 are both formed in the first wiring layer, no step is formed in the wiring. As a result, the film thicknesses of the first and second power supply rings 2 and 3 are constant, so that the coverage rates of the first and second power supply rings 2 and 3 are both 100%.

The first and second power supply rings 2 and 3 are each formed with a wiring width W1 and are formed in parallel at a predetermined interval α. The predetermined interval α is a width such that the first and second power supply rings 2 and 3 do not contact each other due to a manufacturing process or the like, and the first and second power supply rings 2 and 3 are
It is narrower than the wiring width W1 of 3. Therefore, the width W of the power supply ring 4 composed of the first and second power supply rings 2 and 3 is the wiring width W1 of the first and second power supply rings 2 and 3 and the width W of the first and second power supply rings 2 and 3. By the interval α between
It becomes 2 × W1 + α. Since the width W of the power supply ring 4 is formed so that the predetermined interval α is narrower than the wiring width W1 of the power supply rings 2 and 3, the width W2 (= 3 of the conventional power supply ring 14).
XW1). As a result, the area occupied by the power supply ring 4 is reduced, so that the degree of integration of the semiconductor integrated circuit device can be increased.

As described above, in this embodiment, the first and second power supply rings 2 and 3 for supplying power to the hard macro 1 are provided on the lowermost wiring layer on the semiconductor substrate 5 along the outer periphery of the hard macro 1. Formed in parallel. Therefore, since no step is formed in the first and second power supply rings 2 and 3, the coverage ratio is 100%, and it is not necessary to widen the wiring width of each power supply ring 2 and 3.

As a result, the area occupied by the power supply ring 4 composed of the two power supply rings 2 and 3 can be made smaller than that of the conventional power supply ring 13. In addition to the above embodiment, the present invention is provided with, for example, the first and second power supply rings 2 and 3 for supplying power to the hard macro 1. However, a plurality of power supply rings may be provided at predetermined intervals. It may be provided in parallel with α. As a result, the area occupied by the power supply ring 4 can be made smaller than that of the conventional power supply ring 13, which is more effective in increasing the degree of integration of the semiconductor integrated circuit device.

[0020]

As described in detail above, according to the present invention,
There is an excellent effect that the area occupied by the power supply wiring can be reduced.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view illustrating a power ring of a hard macro according to an embodiment.

FIG. 2 is a plan view illustrating a power ring of a hard macro according to an embodiment.

FIG. 3 is a partial cross-sectional view illustrating a conventional hard macro power supply ring.

FIG. 4 is a plan view illustrating a conventional hard macro power supply ring.

FIG. 5 is a plan view illustrating a layout of a semiconductor chip.

[Explanation of symbols]

 1 Hard Macro 2 First Power Ring 3 Second Power Ring 5 Semiconductor Substrate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigenori Ichinose 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. A plurality of power supply wirings (2, 3) for supplying power to a hard macro (1) formed on a semiconductor substrate (5) and composed of a plurality of predesigned elements, said hard macro being provided. A wiring structure of a semiconductor integrated circuit device formed in parallel in the same layer along the outer periphery of (1).