JP2003347405A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with unit cells satisfying a predetermined design rule concerning layout only by arranging in a dummy field in a matrix form. <P>SOLUTION: A cell block 10 that is arranged in a dummy field is provided with unit cells 12A and 12B functioning as a decoupling capacitor and a well fixing part 12C for fixing a well potential. The unit cells 12A and 12B includes a field diffusing region comprising an impurity region 14 and a channel forming region 16 and a gate forming region comprising a gate electrode 18. The well fixing part 12C includes a field diffusing region comprising the impurity region 24. A cell block 10 satisfies a predetermined design rule that is set for the field diffusing region, the gate forming region and the fixation of the potential of the well in the semiconductor device. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of easily designing a layout of a dummy formation region.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor processing technology,
In MOS transistors that are widely used, the minimum processing size has been reduced from 0.18 μm to 0.15 μm. Along with this, the density of layout patterns of elements formed on a semiconductor substrate has been greatly affecting the finished shape of the elements.

[0003] That is, if the layout pattern of the device is sparse and dense, when the resist is applied and etched, the etching of the sparse portion proceeds faster than that of the dense portion, and the shape of the device is uniformly finished. Problem. In addition, the density of the layout pattern causes a step on the surface of the wafer, resulting in an etching residue or a pattern shape defect at the step.

In order to prevent such a problem caused by the sparseness of the layout pattern, a process of filling a sparse portion with a decoupling capacitor or a dummy pattern is performed. Hereinafter, a region where a decoupling capacitor or a dummy pattern is formed to fill a sparse portion is referred to as a dummy field.

FIG. 10 is a diagram schematically showing an overall layout of a conventional semiconductor device having a dummy field.

Referring to FIG. 10, a semiconductor device 100 includes:
Logic forming regions 102A to 102C and dummy fields 104 and 106 are provided. Logic formation area 10
Elements that perform the essential function of this semiconductor device are formed in 2A to 102C. In the dummy field 104,
In order to stabilize a power supply used in the semiconductor device 100, decoupling capacitors configured on a cell basis are arranged in a matrix. The dummy field 106
This is an area where a decoupling capacitor cannot be arranged, and a dummy pattern is individually formed.

As described above, the sparse portion of the layout pattern is formed by the decoupling capacitor and the dummy pattern, thereby solving the above-mentioned problem.

FIG. 11 is a plan view showing a configuration of a unit cell arranged in the dummy field 104.

Referring to FIG. 11, a unit cell 112 includes an impurity region 114, a channel forming region 116, a gate electrode 118, and contact holes 120 and 122. Impurity region 114 is an N-type impurity region provided in a P-type well formed on the main surface of the semiconductor substrate. The channel formation region 116 is a region where a channel is formed in a P-type well when a ground voltage or a negative substrate voltage is applied to the contact hole 120 and a power supply voltage or a boosted voltage is applied to the contact hole 122. Thus, the gate electrode 118 and the electrode of the capacitor are formed via the insulating film.

The gate electrode 118 is formed in the channel formation region 1
16 is formed via an insulating film. Note that, for the sake of explanation, in the figure, the gate electrode 118 is
Although it is shown that it is formed only around the periphery of 16, as will be described later in a cross-sectional view,
The gate electrode 118 is also formed above the channel formation region 116.

The contact hole 120 is formed in the impurity region 1
14, a ground voltage or a negative substrate voltage is applied to the impurity region 114 via the contact hole 120. The contact hole 122 is connected to the gate electrode 118, and is connected to the gate electrode 1 through the contact hole 122.
A power supply voltage or a boosted voltage is applied to 18.

In the above description, the configuration of the unit cell arranged in the dummy field in the P-type well has been described. However, for the unit cell arranged in the dummy field in the N-type well, the impurity region 114 P type, and the impurity region 114
A power supply voltage or a boosted voltage is applied to the gate electrode 118, and a ground voltage or a negative substrate voltage is applied to the gate electrode 118 through the contact hole 122. In the following description, the dummy field will be described as a dummy field in a P-type well. However, since a dummy field in an N-type well has the same basic configuration as described above, the description thereof will be omitted. Do not repeat.

FIG. 12 shows the unit cell 112 shown in FIG.
3 is a cross-sectional view showing a structure of a cross section AA ′ of FIG.

Referring to FIG. 12, a P-type semiconductor substrate 132
A P-type well 134 is provided thereon, and an impurity region 114 and a channel formation region 116 adjacent thereto are provided in the P-type well 134. A gate electrode 118 is provided over the channel formation region 116 with an insulating film 136 therebetween. Impurity region 114 is connected to contact hole 120, and gate electrode 118 is
2 is connected. The capacitor is constituted by the gate electrode 118, the channel formation region 116, and the thin insulating film 36 therebetween.

FIG. 13 shows the unit cell 112 shown in FIG.
FIG. 3 is a diagram showing a state where is arranged in a dummy field 104.

Referring to FIG. 13, dummy field 10
4, the unit cells 112 are arranged in a line. Although not shown, metal wires for applying a power supply voltage or a ground voltage are formed on the contact holes 120 and 122, respectively.

As described above, the unit cells 112 for forming a pattern in the dummy field are arranged to prevent the shape defect of the element caused by the density of the layout pattern. The arrangement is configured and arranged so as to satisfy predetermined layout design rules as described below. In the following description, an element formation region (a region such as the channel formation region 116 and the impurity region 114 shown in FIG. 11) formed in the well is described.
Are generally referred to as a field diffusion region, and a region occupied by a gate electrode formed on a well is referred to as a gate formation region.

(1) Data-free part allowable area rule The pattern must be laid out so that the area where the field diffusion region and the gate forming region are not present is smaller than a predetermined value.

As a result, the density of the layout pattern is eliminated, and the defect of the element shape is prevented.

FIG. 14 is a plan view of the semiconductor device for explaining the rule of the allowable area of the non-data portion.

Referring to FIG. 14, region 152 represents a field diffusion region, and region 154 represents a gate formation region. A region surrounded by a dotted line whose side length is indicated by L11 and L12 is a region where no field diffusion region exists. A region surrounded by a dashed-dotted line whose side length is indicated by L21 and L22 is a region where the gate forming region does not exist. The field diffusion region and the gate forming region are laid out such that the area of each of these regions is smaller than a predetermined value in order to comply with the no-data portion allowable area rule.

[0022]

As mentioned at the beginning,
In recent years, the minimum processing size of a MOS transistor has been set to 0.
In a semiconductor device which has been reduced to 15 μm and has this processing size, the following design rules must be satisfied in addition to the above-described design rule (1).

(2) Area Occupancy Ratio Rule The field diffusion region must be formed so that the area ratio of the field diffusion region in an arbitrary region having a predetermined area is within a predetermined range.

(3) Well Fixing Rule In order to prevent a latch-up phenomenon due to a potential change in the well, the well potential must be fixed at predetermined intervals.

Referring again to FIG. 14, in order to comply with the area occupancy rate rule, in a region having a predetermined area surrounded by a two-dot chain line whose side length is indicated by L3, the field diffusion region The field diffusion region needs to be formed so that the occupied area ratio falls within a predetermined range. Although not shown, in order to comply with the well fixing rule,
It is necessary to form a well fixing region for fixing the well potential at a predetermined interval or less and a contact hole for applying a predetermined voltage to the region.

As described above, as the minimum processing size becomes smaller, the design rules required for the layout design become stricter, and the work load of the designer increases. In particular,
In a large-scale layout such as a semiconductor device having a high function, there is a problem that a work load on the layout is significantly increased and a manufacturing cost is increased.

Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device having a unit cell which satisfies a predetermined layout-related design rule simply by arranging it in a dummy field. To provide.

[0028]

According to the present invention, a semiconductor device includes at least one logic formation region in which at least one transistor is formed, and at least one dummy formation region, and at least one dummy formation region. Each of the regions includes at least one cell block arranged in a matrix, and each of the at least one cell block includes at least one capacitor and at least one well fixing region for suppressing a potential variation of a well. Each of the at least one capacitor and the at least one well fixing region satisfies a predetermined design rule in each of the at least one cell block, and a predetermined design rule for an adjacently disposed cell block. Is satisfied.

In the semiconductor device according to the present invention, each of the cell blocks arranged in the dummy formation region includes at least one capacitor and at least one well fixing region, and the dummy formation region in which the cell blocks are arranged. Then, a predetermined design rule is satisfied.

Therefore, according to the present invention, the work load in the layout design can be reduced, and the manufacturing cost can be reduced.

Preferably, each of the at least one capacitor has first and second electrodes and a first electrode on the first electrode.
And a second contact portion for applying a second power supply voltage to the second electrode. The first electrode is formed on the surface of the well. And a first impurity region provided adjacent to the channel formation region and to which a first power supply voltage is applied through a first contact portion. Each of the at least one well fixing region is provided above the formation region with an insulating film interposed therebetween, and each of the at least one well fixing region has a second impurity region formed on a surface of the well and a predetermined voltage applied to the second impurity region. And a third contact portion.

Preferably, at least one of the first and third contact portions is arranged so as to be aligned in a row direction and / or a column direction when the cell blocks are arranged in a matrix.
One capacitor and one at least one well fixing region.

Preferably, the second contact portion is arranged in each of the at least one capacitor so that the cell blocks are arranged in a row direction and / or a column direction when the cell blocks are arranged in a matrix.

Preferably, the predetermined design rule is such that a channel forming region, a first impurity region, and a region where the second impurity region is not formed on the surface of the well are smaller than the predetermined first area, And a first rule for making a region where the second electrode is not formed on the surface of the well via an insulating film smaller than a predetermined second area;
A second rule for setting the total occupancy of the channel forming region, the first impurity region, and the second impurity region in an arbitrary region having a predetermined third area within a predetermined range;
The third rule is that a second impurity region is provided at predetermined intervals, and the channel forming region, the first impurity region, the second electrode, and the second impurity region satisfy a predetermined design rule. Placed in

Preferably, the second electrode is further arranged on the outer periphery of the second impurity region. Preferably, each of the at least one dummy formation region further includes at least one other cell block having an area smaller than the cell block, and each of the at least one other cell block is formed on a surface of the well. Impurity region,
A contact portion for applying a predetermined voltage for fixing the potential of the well to the impurity region; and an electrode wiring provided on the surface of the well via an insulating film. Each of them is arranged so that a predetermined design rule is satisfied for another cell block arranged adjacently and / or a cell block arranged adjacently.

Preferably, the electrode wiring is arranged on the outer periphery of the impurity region. Preferably, the electrode wires are arranged on both sides of the impurity region.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 schematically shows an overall layout of a semiconductor device according to the present invention.

Referring to FIG. 1, semiconductor device 1 includes logic formation regions 2A to 2C and dummy fields 4 and 6. In the logic forming regions 2A to 2C, elements that fulfill the essential functions of the semiconductor device are formed. In the dummy field 4, cell blocks to be described later are arranged in a matrix so as to satisfy a predetermined design rule regarding layout. The dummy field 6 is an area where a cell block cannot be arranged, and a dummy pattern is individually formed.

FIG. 2 is a plan view showing the structure of a cell block arranged in the dummy field 4.

Referring to FIG. 2, cell block 10 includes 2
It includes two unit cells 12A, a unit cell 12B, and a well fixing part 12C. The unit cells 12A and 12B constitute a decoupling capacitor, and the well fixing portion 12C
It is provided to fix the potential of the P-type well formed on the main surface of the semiconductor substrate. The unit cells 12A and 12B are
Only the arrangement of the contact holes 22 is different, and the configuration of the other parts is the same.

The unit cells 12A and 12B have the impurity region 1
4, a channel formation region 16, a gate electrode 18, and contact holes 20 and 22. Impurity region 14 is an N-type impurity region provided in a P-type well formed on the main surface of the semiconductor substrate. The channel formation region 16 is a region where a channel is formed in the P-type well when a ground voltage or a negative substrate voltage is applied to the contact hole 20 and a power supply voltage or a boosted voltage is applied to the contact hole 22. Thus, the gate electrode 18 and the electrode of the capacitor are formed via the insulating film.

The gate electrode 18 is formed on the channel forming region 16.
It is formed thereover via an insulating film. For the sake of explanation,
Although the gate electrode 18 is shown as being formed only around the channel formation region 16 in the figure, as will be described later in a sectional view, the gate electrode 18 is actually formed above the channel formation region 16. Is also formed.

The contact hole 20 is formed in the impurity region 14
And a ground voltage or a negative substrate voltage is applied to impurity region 14 through contact hole 20. The contact hole 22 is connected to the gate electrode 18, and a power supply voltage or a boosted voltage is applied to the gate electrode 18 via the contact hole 22.

The well fixing portion 12C is provided with an impurity region 24.
And a contact hole 26. Impurity region 24
Is a P-type impurity region provided in a P-type well formed on the main surface of the semiconductor substrate. The impurity region 24
Connected to contact hole 26, contact hole 2
A predetermined well voltage is applied via 6.

In the above description, the configuration of the block cell arranged in the dummy field in the P-type well has been described. However, regarding the block cell arranged in the dummy field in the N-type well, the unit cells 12A, 1
Impurity region 14 in 2B is P-type, a power supply voltage or a boosted voltage is applied to impurity region 14 through contact hole 20, and a ground voltage or a negative substrate voltage is applied to gate electrode 18 through contact hole 22. Applied. Also, corresponding to the N-type well, the well fixing portion 1
Impurity region 24 in 2C is N-type. In the following description, the dummy field will be described as a dummy field in a P-type well. However, since a dummy field in an N-type well has the same basic configuration as described above, the description thereof will be omitted. Do not repeat.

In the cell block 10, the unit cells 12A and 12B and the well fixing portion 12C are configured so as to satisfy the above-described design rules (1) to (3). That is, the well fixing portion 12C is provided to satisfy the design rule (3) (well fixing rule) when the cell blocks 10 are arranged in a matrix. Further, each of the impurity regions 14 of the unit cells 12A and 12B, the channel forming region 16, and the well fixing portion 12
The field diffusion region composed of the C impurity region 24 is
It is formed so that the design rules (1) (data-free part allowable area rule) and (2) (area occupancy ratio rule) are satisfied. Further, the field diffusion region is the cell block 1
When 0s are arranged in a matrix, they are formed such that the design rules (1) and (2) are satisfied in relation to adjacent cell blocks.

After the cell blocks 10 are arranged in a matrix, the contact holes 20 and 26 are
Although it is connected to a metal wiring wired on the zero, it is necessary that this metal wiring also satisfies the design rule (1) described above, and it is desirable that the metal wiring be laid out in order from the viewpoint of layout efficiency. Therefore, in consideration of this, the contact holes 20, 26 are also provided in alignment as shown in the figure. Further, the same applies to the contact hole 22.
Are centrally provided in the central area.

FIG. 3 is a sectional view showing the structure of section AA ′ of the cell block 10 shown in FIG.

Referring to FIG. 3, a P-type well 34 is provided on a P-type semiconductor substrate 32. In P-type well 34, impurity region 14 and channel formation region 16 adjacent thereto are provided. A gate electrode 18 is provided above the channel formation region 16 with an insulating film 36 interposed therebetween. Impurity region 14 is connected to contact hole 20 and gate electrode 18 is connected to contact hole 22 (not shown). Then, the gate electrode 18 and the channel formation region 16
And a thin insulating film 36 therebetween constitutes a decoupling capacitor.

In the P-type well 34, an impurity region 24 of the well fixing portion 12C for fixing the potential of the P-type well is further provided. Impurity region 24 is connected to contact hole 26, and a predetermined well voltage is applied through contact hole 26.

As shown in FIG. 2, the cell block 10
Is slightly larger in area, so dummy field 4
In the case where the cell blocks 10 cannot be arranged in terms of area, cell blocks 50 and 50A having a smaller area than the cell blocks 10 are provided.

FIG. 4 is a plan view showing the structure of a cell block 50 having an area smaller than that of the cell block 10.

Referring to FIG. 4, cell block 50 includes an impurity region 52, a gate electrode 54, and a contact hole 56. Impurity region 52 is a P-type impurity region provided in a P-type well formed on the main surface of the semiconductor substrate. Impurity region 52 is connected to contact hole 56, and a well potential is applied through contact hole 56. Thus, the cell block 50 functions as a well fixing unit, and the above-described design rules (2) and (3) are satisfied by arranging the cell blocks 50. The gate electrode 54 is provided to satisfy the above-described design rule (1).

FIG. 5 is a plan view showing a configuration of a cell block 50A having a smaller area than the cell block 10.

Referring to FIG. 5, cell block 50A also includes
Like the cell block 50, it includes an impurity region 52, a gate electrode 54, and a contact hole 56. The cell block 50A is functionally the same as the cell block 50 except that the arrangement of the impurity region 52 and the gate electrode 54 is different, and functions as a well fixing portion.

The cell blocks 50 and 50A are appropriately selected and arranged in accordance with the place where they are arranged so that the above-described design rule is satisfied when they are arranged.

FIG. 6 is an enlarged plan view showing a part of the semiconductor device 1 shown in FIG. Referring to FIG. 6, cell blocks 10 are arranged in rows and columns in dummy field 4. The metal wiring 62 is a power supply line to which a power supply voltage or a boosted voltage is applied, and is connected to the contact hole 22 of each cell block 10. The metal wiring 64 is a power supply line to which a ground voltage or a negative substrate voltage is applied, and is a contact hole 20, 26 of each cell block 10.
Is connected to

Contact hole 2 of each cell block 10
2 and the contact holes 20 and 26 are arranged in each cell block 10 so that the metal wirings 62 and 64 can be wired in a comb shape, respectively, whereby the metal wirings 62 and 64 are laid out in a comb-like order. ing.

A cell block 50 is arranged where the cell block 10 cannot be arranged. The cell block 50 functions as a well fixing part, and is connected to the same metal wiring 64 as the well fixing part 12C of the cell block 10 via the contact hole 56. A ground voltage or a negative substrate voltage is applied to the gate electrode 54 of the cell block 50 via a contact hole 66 connected to the metal wiring 64.

As described above, in the semiconductor device 1 according to the first embodiment, in the dummy field in which the cell blocks 10 and / or the cell blocks 50 and 50A are arranged, the predetermined design rule regarding the layout is satisfied. Therefore, the work load at the time of layout design is reduced.

[Second Embodiment] The cell block 10 provided in the semiconductor device 1 according to the first embodiment must be designed to have a predetermined size or less.

FIG. 7 is a plan view of the cell block 10 for explaining the allowable size of the cell block 10.

Referring to FIG. 7, impurity region 24 of well fixing portion 12C forms a field diffusion region. However, since the well fixing portion 12C does not include a gate formation region, when the size of the cell block 10 exceeds a predetermined value, the lengths of L1 and L2 shown in the drawing exceed the predetermined value, and the design rule (1) (not The data part allowable area rule) and / or the design rule (2) (area occupancy ratio rule) are not satisfied.

Therefore, the semiconductor device 1 according to the second embodiment
Even if the cell block of A cannot be designed to have a cell block size smaller than a predetermined value, the design rule (1),
(2) can be satisfied.

The overall configuration of the semiconductor device 1A according to the second embodiment is the same as that of the semiconductor device 1 according to the first embodiment shown in FIG.
Is the same as in the overall configuration, and the description thereof will not be repeated.

FIG. 8 shows a semiconductor device 1 according to the second embodiment.
FIG. 3 is a plan view showing a configuration of a cell block arranged in a dummy field 4 of A.

Referring to FIG. 8, in cell block 10A, the periphery of well fixing portion 12C is surrounded by one gate electrode 18 of unit cell 12A, as compared with cell block 10 shown in FIG. . In the gate electrode 18,
The portion provided around the well fixing portion 12C is exclusively for avoiding the violation of the design rules (1) and (2), and the function of the well fixing portion 12C is as follows.
In order to satisfy the design rule (3) (well fixing rule), the potential of the well is fixed.

Since the structure of the other parts of cell block 10A is the same as that of cell block 10 shown in FIG. 2, description thereof will not be repeated.

FIG. 9 shows the cell block 10A shown in FIG.
3 is a cross-sectional view showing a structure of a cross section AA ′ of FIG.

Referring to FIG. 9, a gate electrode 18 is provided on a main surface of a P-type semiconductor substrate 32 with an insulating film 36 interposed therebetween, and a portion of gate electrode 18 surrounding impurity region 24 is a channel forming region. The insulating film is provided with a thickness larger than the thickness of the insulating film in a portion constituting the capacitor together with the region 16. The gate electrode 18 does not overlap with the impurity region 24 in a vertical positional relationship, and the portion surrounding the impurity region 24 is provided on the main surface via a thick insulating film. The impurity region 24 functions as a region for fixing the potential of the P-type well 34 by the well voltage applied through the contact hole 26.

The structure of other portions in the sectional structure of cell block 10A is the same as the sectional structure of cell block 10 shown in FIG. 3, and therefore, description thereof will not be repeated.

As described above, according to the semiconductor device 1A of the second embodiment, even if the size of the cell block 10A is larger than the predetermined value, the predetermined layout-related field is not provided in the dummy field in which the cell blocks 10A are arranged. , The work load during layout design is reduced.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an overall layout of a semiconductor device according to the present invention.

FIG. 2 is a plan view showing a configuration of a cell block arranged in a dummy field of the semiconductor device according to the first embodiment;

FIG. 3 is a sectional view showing a structure of a section AA ′ of the cell block shown in FIG. 2;

FIG. 4 is a plan view showing a configuration of a cell block having an area smaller than that of the cell block shown in FIG. 2;

FIG. 5 is a plan view showing another configuration of a cell block having an area smaller than that of the cell block shown in FIG. 2;

6 is an enlarged plan view showing a part of the semiconductor device shown in FIG. 1;

FIG. 7 is a plan view of a cell block for describing an allowable size of the cell block shown in FIG. 2;

FIG. 8 is a plan view showing a configuration of a cell block arranged in a dummy field of the semiconductor device according to the second embodiment.

FIG. 9 is a cross-sectional view showing a structure of a cross section AA ′ of the cell block shown in FIG. 8;

FIG. 10 is a diagram schematically showing an overall layout of a conventional semiconductor device including a dummy field.

11 is a plan view showing a configuration of a unit cell arranged in a dummy field shown in FIG.

12 is a cross-sectional view showing a structure of a cross section AA ′ of the unit cell shown in FIG. 11;

FIG. 13 is a diagram showing a state where the unit cells shown in FIG. 11 are arranged in a dummy field.

FIG. 14 is a plan view of the semiconductor device for explaining a data-free portion allowable area rule.

[Explanation of symbols]

1, 1A, 100 Semiconductor device, 2A-2C, 102A
〜１０102C logic formation area, 4, 6, 104, 10
6 Dummy field, 10, 10A, 50, 50A
Cell block, 12A, 12B, 112 unit cell, 1
2C well fixing portion, 14, 24, 52, 114 impurity region, 16, 116 channel formation region, 18, 5
4,118 gate electrode, 20, 22, 26, 56, 6
6,120,122 Contact holes, 32,132
P-type semiconductor substrate, 34, 134 P-type well, 36, 1
36 insulating film, 62, 64 metal wiring, 152, 154
region.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hideki Yoneya             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo 3             Rishi Electric Co., Ltd. (72) Inventor Tsutomu Nagasawa             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo 3             Rishi Electric Co., Ltd. (72) Inventor Tadaaki Yamauchi             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo 3             Rishi Electric Co., Ltd. (72) Inventor Masato Suwa             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo 3             Rishi Electric Co., Ltd. (72) Inventor Junko Matsumoto             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo 3             Rishi Electric Co., Ltd. (72) Inventor Masunari Tada             1-132 Ogino, Itami-shi, Hyogo Dai-Oden             Machine Co., Ltd. F term (reference) 5F038 AC03 CA02 CA05 CA17 CA18                       CD14 EZ09                 5F064 CC23 DD02 DD10 DD18 DD19                       DD26 DD50 EE60

Claims (9)

[Claims] 1. A semiconductor device comprising: at least one logic formation region in which at least one transistor is formed; and at least one dummy formation region, each of the at least one dummy formation region being arranged in a matrix. Each of the at least one cell block includes at least one capacitor, and at least one well fixing region for suppressing a potential change of a well, wherein the at least one capacitor and the at least one Each of the well fixing regions is arranged such that a predetermined design rule is satisfied in each of the at least one cell block, and that the predetermined design rule is satisfied for a cell block arranged adjacently. , Semiconductor devices. 2. Each of the at least one capacitor includes a first electrode and a second electrode, and a first electrode for applying a first power supply voltage to the first electrode.
A second contact portion for applying a second power supply voltage to the second electrode;
Wherein the first electrode is provided adjacent to the channel formation region formed on the surface of the well, and the first electrode is provided through the first contact portion. Wherein the second electrode is provided above the channel forming region via an insulating film, and each of the at least one well fixing region is 2. The semiconductor device according to claim 1, comprising: a second impurity region formed on a surface of the well; and a third contact portion for applying a predetermined voltage to the second impurity region. 3. The first and third contact portions,
3. The device according to claim 2, wherein the cell blocks are arranged in each of the at least one capacitor and the at least one well fixing region so as to be aligned in a row direction and / or a column direction when arranged in a matrix. 13. The semiconductor device according to claim 1. 4. The second contact portion is arranged in each of the at least one capacitor so that the cell blocks are arranged in a row direction and / or a column direction when the cell blocks are arranged in a matrix. The semiconductor device according to claim 2. 5. The design rule according to claim 1, wherein the channel formation region, the first impurity region, and the region where the second impurity region is not formed on the surface of the well are smaller than a predetermined first area. Smaller,
A first rule for making a region where the second electrode is not formed on the surface of the well via an insulating film smaller than a predetermined second area; and a predetermined third area. A second region in which the total occupancy of the channel forming region, the first impurity region, and the second impurity region in an arbitrary region is within a predetermined range;
And the third rule of providing the second impurity regions at predetermined intervals. The channel forming region, the first impurity region, the second electrode, and the second impurity region 3. The arrangement is such that the predetermined design rule is satisfied.
3. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 5, wherein said second electrode is further arranged on an outer periphery of said second impurity region. 7. Each of the at least one dummy formation region further includes at least one other cell block having an area smaller than the cell block, and each of the at least one another cell block includes: An impurity region formed on the surface of the well; a contact portion for applying a predetermined voltage for fixing the potential of the well to the impurity region; and an electrode provided on the surface of the well via an insulating film. Each of the at least one other cell block satisfies the predetermined design rule with respect to another adjacently arranged cell block and / or an adjacently arranged cell block. The semiconductor device according to claim 1, wherein the semiconductor device is arranged so as to be disposed. 8. The semiconductor device according to claim 7, wherein said electrode wiring is arranged on an outer periphery of said impurity region. 9. The semiconductor device according to claim 7, wherein said electrode wiring is arranged on both sides of said impurity region.