CN111474980A - Current mirror circuit - Google Patents
Current mirror circuit Download PDFInfo
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- CN111474980A CN111474980A CN202010407181.5A CN202010407181A CN111474980A CN 111474980 A CN111474980 A CN 111474980A CN 202010407181 A CN202010407181 A CN 202010407181A CN 111474980 A CN111474980 A CN 111474980A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The invention provides a current mirror circuit comprising at least one current mirror module, wherein: the current mirror module comprises a sub-module body and a first protection module; the first protection module of at least one current mirror module comprises an enabling transistor and a decoupling capacitor, and the enabling transistor and the decoupling capacitor are distributed on two sides of the sub-module body respectively; the enabling transistors and the decoupling capacitors are replaced in the area occupied by the original virtual transistor, so that the current mirror circuit does not need to occupy more layout resources to place the enabling transistors and the decoupling capacitors, the enabling transistors and the decoupling capacitors are distributed on two sides of the sub-module body, the risks that the edge of the sub-module body is etched excessively and the current of the current mirror circuit is mismatched are avoided, in addition, the enabling transistors and the decoupling capacitors are not matched objects of mirror currents, and the sizes formed after etching do not influence the current matching of the whole current mirror circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a current mirror circuit.
Background
Matching MOS tubes are used in various analog circuits, some circuits mainly use the matching of grid source voltage, and some circuits need the matching of drain current. The current mirror needs to realize the matching of drain current, the size, the shape and the direction of the MOS tube can influence the mutual matching of the MOS tube, and the size mismatch and the threshold mismatch of the MOS tube are reduced through reasonably designing a layout so as to reduce the current imbalance.
The etch rate is not always uniform throughout the process, and this effect may cause over-etching as the etch rate is faster when the openings are larger. As shown in fig. 1, M1, M2, M3 tubes were etched under the same etching conditions to obtain matching MOS tubes of the same size, but the outer edge etching of M1 and M3 was more severe than the edge etching corresponding to M2, and the boundary etching speed is faster as indicated by the arrows in fig. 1, so the gate lengths of M1 and M3 were slightly shorter than that of M2. As shown in fig. 2, in the prior art, a Dummy device (Dummy transistor) is used to prevent the polysilicon gate from being over-etched, and the gate of the Dummy transistor is connected to the source (back gate potential) of the transistor, which helps to ensure that the electrical characteristics of the transistor are not affected by the Dummy channel under the Dummy transistor.
In summary, the current mirror circuit in the integrated circuit design has wide application, and as an important component of the analog design, the high-precision current mirror circuit not only needs parameter matching between MOS transistors, but also needs Dummy transistors around the matched current mirror circuit combination to complete matching tasks. As shown in fig. 3, the source-drain gate of the Dummy tube in the outer ring is electrically connected to the four ports of the substrate in a short circuit manner, which results in a waste of a certain area.
Disclosure of Invention
The invention aims to provide a current mirror circuit to solve the problem that the layout area of an integrated circuit is wasted by Dummy tubes of the existing current mirror circuit.
To solve the above technical problem, the present invention provides a current mirror circuit, which includes at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module of at least one of the current mirror modules comprises an enable transistor and a decoupling capacitor, and the enable transistor and the decoupling capacitor are respectively distributed on two sides of the sub-module body.
Optionally, in the current mirror circuit, the current mirror circuit further includes a reference circuit, and the reference circuit forms a bias voltage according to an input current and provides the bias voltage to the sub-module body.
Optionally, in the current mirror circuit, an enable signal is provided to a gate of the enable transistor, a source and a drain of the enable transistor are electrically coupled between a power supply voltage and the bias voltage, and a substrate of the enable transistor is electrically coupled to the power supply voltage.
Optionally, in the current mirror circuit, the decoupling capacitor is a dummy transistor, a gate of the dummy transistor is electrically coupled to the bias voltage, and a source and a drain of the dummy transistor and the substrate are electrically coupled to the power supply voltage.
Optionally, in the current mirror circuit, each of the sub-module bodies includes an input current transistor and at least one output current transistor, where:
the source and the substrate of the input current transistor are both electrically coupled to the supply voltage, the gate of the input current transistor is electrically coupled to the bias voltage, and the drain of the input current transistor is electrically coupled to the bias voltage;
the source and the substrate of the output current transistor are both electrically coupled to the power supply voltage, the gate of the output current transistor is electrically coupled to the bias voltage, and the drain of the output current transistor outputs a mirror current.
Optionally, in the current mirror circuit, an active area width-to-length ratio of each input current transistor is equal to an active area width-to-length ratio of each output current transistor.
Optionally, in the current mirror circuit, the current mirror circuit further includes a guard ring, and the guard ring surrounds at least one of the current mirror modules in an area center.
Optionally, in the current mirror circuit, the current mirror circuit further includes second protection modules, and the second protection modules are distributed at the top end and the bottom end of the sub-module body.
The present invention also provides a current mirror circuit comprising at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module comprises at least one decoupling capacitor, and the decoupling capacitors are distributed on two sides of the sub-module body.
The present invention also provides a current mirror circuit comprising at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module comprises two decoupling capacitors, and the two decoupling capacitors are distributed on two sides of the sub-module body respectively.
In the current mirror circuit provided by the invention, the first protection module of at least one current mirror module comprises an enabling transistor and a decoupling capacitor, the enabling transistor and the decoupling capacitor are respectively distributed on two sides of the sub-module body, the area occupied by the original virtual device (Dummy tube) is replaced by the enabling transistor and the decoupling capacitor, so that the current mirror circuit does not need to occupy more layout resources to place the enabling transistor and the decoupling capacitor, and the enabling transistors and the decoupling capacitors are distributed on two sides of the sub-module body, thereby avoiding the risks of excessive etching and current mismatch of the current mirror circuit caused by high etching rate of the edge of the sub-module body, in addition, the enabling transistor and the decoupling capacitor are not matched objects of mirror current, and the size formed after etching does not influence the current matching of the whole current mirror circuit.
Drawings
FIG. 1 is a schematic diagram of a current mismatch principle of a MOS transistor of a conventional integrated circuit;
FIG. 2 is a schematic diagram of a current matching principle of a MOS transistor implemented by a Dummy transistor in an existing integrated circuit;
FIG. 3 is a schematic layout of a prior art current mirror circuit;
FIG. 4 is a schematic diagram of a prior art current mirror circuit topology;
FIG. 5 is a schematic layout of a current mirror circuit formed by NMOS according to an embodiment of the present invention;
FIG. 6 is a schematic layout of a PMOS-based current mirror circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a current mirror circuit topology formed by a PMOS in accordance with another embodiment of the present invention;
FIG. 8 is a schematic diagram of a current mirror circuit topology formed by an NMOS of another embodiment of the present invention;
shown in the figure: 10-current mirror module; 11-submodule body; 12-a first protection module; 13-a guard ring.
Detailed Description
The current mirror circuit proposed by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As shown in fig. 3, in the current mirror circuit, the input current transistor M0 is used for generating mirrored currents according to a bias voltage, the output current transistors M1 and M2 respectively output two sets of mirrored currents, and the number of M0, M1 and M2 is plural (2 in the example in fig. 3), plural M0 are connected in parallel (i.e., plural M0 gates are electrically connected, plural M0 sources are electrically connected, plural M0 drains are electrically connected, and plural M0 substrates are electrically connected), plural M1 are connected in parallel, plural M2 are connected in parallel, and the widths and lengths of the active regions of M0, M1 and M2 are equal, so as to implement current matching of the current mirror circuit. According to the working principle of the current mirror circuit, when M0, M1 and M2 work in the saturation region,
wherein Id is source-drain current, unAs the transport rate of carriers, CoxFor gate oxide capacitance per unit area, W/L is the active area width-to-length ratio, Vgs is the gate-source voltage, Vth is the threshold voltage, Vgs-Vth is the overdrive voltage, and because Vgs 0-Vgs 1-Vgs 2 and Vth 0-Vth 1-Vth 2, this is true for the gate oxide capacitance per unit area
The source and drain currents of the M0, M1 and M2 are to be accurately copied in proportion, Dummy tubes are added at the left and right sides of a layout area composed of M0, M1 and M2 even at the upper and lower sides of the layout area to match, and the W and L of the M0, M1 and M2 are consistent under physical conditions, the current mirror circuit in fig. 3 is to realize current matching, the left side of each M1 and the right side of each M2 are required to be provided with the Dummy tubes, so that only six effective tubes are required to be provided with four Dummy tubes dumm, source and drain gates and four ports of a substrate of the four Dummy tubes are in short circuit electrical connection, and compared with a wire which is in short circuit by itself, the layout of an integrated circuit is greatly wasted, bias voltages for pulling up or pulling down are used for enabling or shutting down the current mirror circuit M4 and are placed outside a main layout of the current mirror circuit, so that the current mirror circuit occupies an excessively large layout area and is interfered by high frequency or signals in other circuits, and transient reliability cannot be ensured, and the topology of the M3 is shown as a 2, and the number of the parallel transistors is shown in the schematic diagram 2.
The core idea of the invention is to provide a current mirror circuit to solve the problem that the Dummy transistor of the current mirror circuit wastes the layout area of the integrated circuit.
To achieve the above idea, the present invention provides a current mirror circuit comprising at least one current mirror module, wherein: the current mirror module comprises a sub-module body and a first protection module; the first protection module of at least one of the current mirror modules comprises an enable transistor and a decoupling capacitor, and the enable transistor and the decoupling capacitor are respectively distributed on two sides of the sub-module body.
According to the invention, the enabling transistors are distributed on one side of the sub-module body, so that the area can be saved, the position and the area of the enabling transistors do not need to be found independently, and the typesetting is facilitated. The enabling transistor is closer to the sub-module body, the wiring is shortened, wiring interference is reduced, the enabling transistor is prevented from being far away from the sub-module body, the wiring leads out the current mirror module, the risk of crosstalk is easily caused, and particularly, nearby clock signals exist. The decoupling capacitor increases the stability of the current mirror circuit, and the decoupling capacitor decap is formed by the Dummy tube, so that waste can be changed into valuable, the matching of the current mirror circuit is met, and the stability of the overall electrical performance is also increased.
< example one >
The present embodiment provides a current mirror circuit, as shown in fig. 5 to 6, the current mirror circuit includes at least one current mirror module 10, wherein: the current mirror module 10 comprises a sub-module body 11 and a first protection module 12; the first protection module 12 of at least one of the current mirror modules 10 comprises an enable transistor M4 and a decoupling capacitor decap, wherein the enable transistor M4 and the decoupling capacitor decap are respectively distributed on two sides of the sub-module body 11. The function of the enable transistor M4 includes, when the current mirror circuit does not work, pulling up the bias voltage Vpbias to the power supply voltage VCC (or pulling down the bias voltage Vnbias to the power supply voltage VSS), ensuring the stable state of the gate voltage of each MOS transistor, and releasing the clamp when the current mirror circuit works, without requiring Dummy transistor matching.
As shown in the schematic topology diagrams of fig. 7 to 8, in the current mirror circuit, the current mirror circuit further includes a reference circuit, and the reference circuit forms a bias voltage Vpbias/Vnbias according to the input current I _ in and provides the bias voltage Vpbias/Vnbias to the sub-module body 11. In the current mirror circuit, an enable signal en is provided to a gate of the enable transistor M4, when M0, M1 and M2 are all PMOS, a source drain of the enable transistor M4 is electrically coupled between a power supply voltage VCC and the bias voltage Vpbias, when M0, M1 and M2 are all NMOS, a source drain of the enable transistor M4 is electrically coupled between a power supply voltage VSS and the bias voltage Vnbias, and a substrate of the enable transistor M4 is electrically coupled to the power supply voltage VCC/VSS.
In an embodiment of the present invention, as shown in fig. 6, since the number of the enable transistors M4 in the whole current mirror circuit is generally one, if the number of the current mirror modules 10 is plural, the first protection module 121 of only one current mirror module includes the enable transistor M4 and the decoupling capacitor decap, i.e. the first protection module 121 of the current mirror module above the page as shown in fig. 6, and the first protection module 122 of the remaining current mirror modules includes two decoupling capacitors decap respectively distributed on both sides of the sub-module body 11, i.e. the first protection module 122 of the current mirror module below the page as shown in fig. 6.
As shown in fig. 7 to 8, in the current mirror circuit, the decoupling capacitor decap is a Dummy transistor, a gate of the Dummy transistor is electrically coupled to the bias voltage Vpbias/Vnbias, that is, a transistor structure is formed on a layout, and the gate of the Dummy transistor is electrically coupled to the bias voltage Vpbias/Vnbias to make the Dummy transistor have a characteristic of a capacitor, which is different from a Dummy device (Dummy transistor) only in a connection relationship of the gate; and the source drain and the substrate of the virtual transistor are electrically coupled to the power supply voltage VCC/VSS. In the prior art, the gate of the dummy transistor is electrically connected to the bias voltage Vpbias/Vnbias, which is equivalent to a short-circuited conducting wire, and the decoupling capacitor decap is used to absorb high-frequency or transient interference signals, so that the bias voltage Vpbias/Vnbias is kept stable when interfered by high-frequency or transient signals of other circuits, and the number and size of the decoupling capacitor decap have certain flexibility.
In an embodiment of the present invention, each of the sub-module bodies 11 includes an input current transistor M0 and at least one output current transistor (examples given in this embodiment are M1 and M2), wherein: the source and the substrate of the input current transistor M0 are electrically coupled to the power supply voltage VCC/VSS, the gate of the input current transistor M0 is electrically coupled to the bias voltage Vpbias/Vnbias, and the drain of the input current transistor M0 is electrically coupled to the bias voltage Vpbias/Vnbias; the source and the substrate of the output current transistor (M1 and M2) are electrically coupled to the power supply voltage VCC/VSS, the gate of the output current transistor (M1 and M2) is electrically coupled to the bias voltage Vpbias/Vnbias, and the drain of the output current transistor (M1 and M2) outputs a mirror current I _ out1/I _ out 2. The bias voltage is coupled to a constant current source I3, constant current source I3 providing an input current I _ in. At the moment, M0, M1 and M2 all work in a saturation region, and the source-drain current is determined by a gate-source voltage Vgs and is kept stable; the conditions for the MOS tube to work in the saturation region are as follows: vgs > Vth, Vds > Vgs-Vth, Vds being the source-drain voltage.
Further, in the current mirror circuit, an active area width-to-length ratio of each input current transistor is equal to an active area width-to-length ratio of each output current transistor. The current mirror circuit further comprises a guard ring 13, the guard ring 13 enclosing at least one of the current mirror modules 10 in the area center. The current mirror circuit further includes second protection modules (not shown in the figure), and the second protection modules are distributed at the top end and the bottom end of the sub-module body 11. The second protection module includes a plurality of decoupling capacitors.
Furthermore, the number of MOS transistors of the current mirror module 10 and the matching manner are schematic, and those skilled in the art can perform matching according to specific requirements, the number of MOS transistors of the first protection module 12 is also applied according to actual requirements, and a plurality of virtual transistors can be respectively placed at the top end and the bottom end of the sub-module body 11 as decoupling capacitors to form a second protection module, where the number of virtual transistors in the second protection module corresponds to the number of transistors in the sub-module body 11 one to one. In the embodiment, the principle of replacing the Dummy transistors with the effective MOS transistors is to preferentially replace the Dummy transistors with the MOS transistors which are coupled with the signal lines of the current mirror circuits, are related to routing and have static response, so that the large-current MOS transistors such as clock signal lines and transient response MOS transistors are avoided, other interference signals are avoided, the MOS transistors similar to M4 and decap have no matching requirements, and the size has certain flexibility, so that the corresponding Dummy transistors can be completely replaced by the Dummy transistors. Optionally, the rest Dummy transistors can be replaced by decoupling capacitors decap partially or completely flexibly, and the distance between the left MOS transistor and the right MOS transistor is consistent. The distances between the MOS tubes of the upper layer and the lower layer are consistent.
In addition, the matching pipes (i.e. the dummy transistors and the enable transistors in the first protection module 12 and/or the dummy transistors in the second protection module) may be the same size as the MOS transistors in the sub-module body 11, and when the width and length of the active regions of the MOS transistors in the first protection module 12 and/or the MOS transistors in the second protection module are large, the width and length of the active regions of the matching pipes may be adjusted according to specific situations, and when matching and area trade-off are required, the matching pipes (first protection module) located generally on the left and right of the sub-module body 11 may adjust the gate length L thereof (as shown in fig. 6) during matching, the matching pipes (second protection module) located above and below the sub-module body 11 may adjust the gate width W thereof (as shown in fig. 6), the adjusted size of the matching pipes L is not less than 1 micron, and W is not less than 0.5 micron.
< example two >
The present embodiment further provides a current mirror circuit, which includes at least one current mirror module, wherein: the current mirror module comprises a sub-module body and a first protection module; the first protection module comprises at least one decoupling capacitor, and the decoupling capacitors are distributed on two sides of the sub-module body.
The present embodiment further provides a current mirror circuit, which includes at least one current mirror module, wherein: the current mirror module comprises a sub-module body and a first protection module; the first protection module comprises two decoupling capacitors, and the two decoupling capacitors are distributed on two sides of the sub-module body respectively.
Specifically, the first protection module comprises two decoupling capacitors, or comprises a decoupling capacitor and an enabling transistor. When the current mirror circuit includes only one current mirror module, the current mirror module includes a decoupling capacitor and an enable transistor. When the current mirror circuit comprises a plurality of current mirror modules, one of the current mirror modules comprises a decoupling capacitor and an enable transistor, and the remaining other current mirror modules comprise two decoupling capacitors.
In the current mirror circuit provided by the invention, the first protection module of at least one current mirror module comprises an enabling transistor and a decoupling capacitor, the enabling transistor and the decoupling capacitor are respectively distributed on two sides of the sub-module body, the area occupied by the original virtual device (Dummy tube) is replaced by the enabling transistor and the decoupling capacitor, so that the current mirror circuit does not need to occupy more layout resources to place the enabling transistor and the decoupling capacitor, and the enabling transistors and the decoupling capacitors are distributed on two sides of the sub-module body, thereby avoiding the risks of excessive etching and current mismatch of the current mirror circuit caused by high etching rate of the edge of the sub-module body, in addition, the enabling transistor and the decoupling capacitor are not matched objects of mirror current, and the size formed after etching does not influence the current matching of the whole current mirror circuit.
In summary, the above embodiments have described the different configurations of the current mirror circuit in detail, and it is needless to say that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided by the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A current mirror circuit, comprising at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module of at least one of the current mirror modules comprises an enable transistor and a decoupling capacitor, and the enable transistor and the decoupling capacitor are respectively distributed on two sides of the sub-module body.
2. The current mirror circuit of claim 1, further comprising a reference circuit that forms a bias voltage from an input current and provides the bias voltage to the sub-module body.
3. The current mirror circuit of claim 2, wherein an enable signal is provided to a gate of the enable transistor, a source and drain of the enable transistor being electrically coupled between a supply voltage and the bias voltage, a substrate of the enable transistor being electrically coupled to the supply voltage.
4. The current mirror circuit of claim 3, wherein the decoupling capacitor is a dummy transistor, a gate of the dummy transistor is electrically coupled to the bias voltage, and a source, a drain, and a substrate of the dummy transistor are electrically coupled to the supply voltage.
5. The current mirror circuit of claim 2, wherein each of the sub-module bodies includes an input current transistor and at least one output current transistor, wherein:
the source and the substrate of the input current transistor are both electrically coupled to the supply voltage, the gate of the input current transistor is electrically coupled to the bias voltage, and the drain of the input current transistor is electrically coupled to the bias voltage;
the source and the substrate of the output current transistor are both electrically coupled to the power supply voltage, the gate of the output current transistor is electrically coupled to the bias voltage, and the drain of the output current transistor outputs a mirror current.
6. The current mirror circuit of claim 5, wherein the active area width to length ratio of each input current transistor is equal to the active area width to length ratio of each output current transistor.
7. The current mirror circuit of claim 1, further comprising a guard ring that surrounds at least one of the current mirror modules at an area center.
8. The current mirror circuit of claim 1, further comprising second protection modules distributed at top and bottom ends of the sub-module body.
9. A current mirror circuit, comprising at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module comprises at least one decoupling capacitor, and the decoupling capacitors are distributed on two sides of the sub-module body.
10. A current mirror circuit, comprising at least one current mirror module, wherein:
the current mirror module comprises a sub-module body and a first protection module;
the first protection module comprises two decoupling capacitors, and the two decoupling capacitors are distributed on two sides of the sub-module body respectively.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003347405A (en) * | 2002-05-23 | 2003-12-05 | Mitsubishi Electric Corp | Semiconductor device |
| CN102569400A (en) * | 2011-12-13 | 2012-07-11 | 钜泉光电科技(上海)股份有限公司 | Metal-oxide-semiconductor device |
| CN104867910A (en) * | 2014-02-24 | 2015-08-26 | 新唐科技股份有限公司 | Electrostatic discharge protection circuit and semiconductor device |
| CN105573402A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Current mirror amplifier layout structure and voltage regulator |
| CN110162913A (en) * | 2019-05-30 | 2019-08-23 | 上海华虹宏力半导体制造有限公司 | A kind of capacitor layout design method |
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2020
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003347405A (en) * | 2002-05-23 | 2003-12-05 | Mitsubishi Electric Corp | Semiconductor device |
| CN102569400A (en) * | 2011-12-13 | 2012-07-11 | 钜泉光电科技(上海)股份有限公司 | Metal-oxide-semiconductor device |
| CN104867910A (en) * | 2014-02-24 | 2015-08-26 | 新唐科技股份有限公司 | Electrostatic discharge protection circuit and semiconductor device |
| CN105573402A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Current mirror amplifier layout structure and voltage regulator |
| CN110162913A (en) * | 2019-05-30 | 2019-08-23 | 上海华虹宏力半导体制造有限公司 | A kind of capacitor layout design method |
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Effective date of registration: 20220805 Address after: 201210 floor 10, block a, building 1, No. 1867, Zhongke Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Xiaohua Semiconductor Co.,Ltd. Address before: 201210 8th floor, block a, 1867 Zhongke Road, Pudong New Area, Shanghai Patentee before: HUADA SEMICONDUCTOR Co.,Ltd. |
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