JPH11135724A - Semiconductor integrated circuit, automatic arranging and designing method thereof and manufacture of the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To insert a capacitor for a noise filter into a power-supply wiring using automatic arranging design without the elongation of a designing period and the reduction of accuracy, by providing the capacitor for the noise filter, which is provided at a power-strap part and connected to one of the power supply wiring and a grounding wiring. SOLUTION: In the automatic arranging and designing method of an LSI, capacitor block-pattern data including a capacitor for a noise filter is prepared beforehand at a power strap part 20 for drawing a power supply for cell lines 10, wherein cells are arranged in one line, on an LSI chip. Then, in the cell lines 10, capacitor block patterns are arranged at the specified frequency (adequate frequency computed in consideration of the operating frequency, processes and the like of the intended LSI as the design object). Thus, the capacitor for the noise filter can be inserted to the power supply wiring, by using the automatic arranging design without the elongation of the design period, the reduction of the design accuracy and the increase in chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
More particularly, the present invention relates to a method for automatically arranging capacitors in an LSI (Large Scale Integrated Circuit) using a capacitor for a noise filter, for example, a microcomputer,
Used for microcontrollers, logic LSIs, etc.

[0002]

2. Description of the Related Art In recent years, low power consumption is one of the advantages.
In MOS (complementary insulated gate) LSIs, power consumption and noise are becoming a major barrier to commercialization with the increase in scale and speed. The problem of power consumption and noise is
In each case, the measures are common in that they are caused by the charge / discharge current accompanying the operation of the LSI.

However, while power consumption is a problem of average current, noise is problematic in terms of the sum of currents (peak values of instantaneous currents) flowing during the switching operation of individual gates and the amount of change with time. So different measures are needed. For example, it is generally effective to reduce the element size of a transistor (such as a MOSFET) to reduce the overall current, but it is generally effective as a noise reduction measure. However, noise reduction alone may not be sufficient. Also,
Due to the operating frequency required for the LSI, there is a limit in reducing the current.

As one of effective countermeasures for noise reduction, a CR filter may be inserted as a noise filter for removing noise superimposed on the power supply wiring. The capacitance of the capacitor of the CR filter is very large. , The design effort to insert this capacitor,
The increase in the area occupied by the pattern on the chip and the increase in the chip area due to the insertion of the capacitor cannot be ignored.

[0005] In addition, since a capacitor for a noise filter greatly depends on a peak value of an instantaneous current generated by an LSI and a temporal change thereof, a capacitor is to be inserted in order to determine a capacitance value of the capacitor. It is necessary to determine the current of the part by some means.

[0006] By the way, a normal LSI, especially a logic LS
Automatic design techniques have become common in LSIs in which a desired circuit is formed by a wiring method for cells formed in advance, such as an I, gate array type or standard cell type LSI. Automatic design method 1
For example, software for performing automatic layout design by CAD (computer-aided design) is employed. In the automatic placement design software, gates forming a logic circuit are generally placed and wired using a netlist in which constituent units called individual cells are connected.

When the above-described automatic layout design of the LSI is performed by CAD, the power supply to the cell is usually performed by
As shown in FIG. 1, a basic circuit element or a unit circuit element (hereinafter, referred to as a cell) for realizing a basic logical function is arranged in a row (row direction) in a cell column 10 arranged linearly (one column), for example. The power straps 20 are arranged at both ends and at intermittent positions in the intermediate region.

Conventionally, the power strap 20 is used only for drawing in a power supply, and is not used for any other purpose. Conventionally, the position of the power strap is naturally incorporated into the procedure of automatic placement design.

That is, since the netlist in the conventional automatic placement design software does not include the noise filter capacitor, the noise filter capacitor is excluded from the automatic placement design.

Therefore, at present, a region necessary for disposing a capacitor for a noise filter is provided in advance (opened), and a design for manually inserting the noise filter after automatic layout design by CAD is performed.

However, since the additional insertion of the capacitor for the noise filter is performed near the final step of the chip design, the burden on the design verification is increased and the design period is lengthened.

Further, with the recent progress of CAD technology,
Although a method of calculating a current value of a portion where a capacitor for a noise filter is to be inserted has been realized, it is necessary to minimize the increase in the pattern occupation area and appropriately insert a capacitor having a capacitance value corresponding to the calculated current value. However, there is a concern that it takes considerable time and effort to design, and at the same time causes a decrease in design accuracy.

[0013]

As described above, the noise reduction measure of inserting the CR filter in the power supply wiring in the conventional LSI has a problem that the design period is prolonged, the design accuracy is reduced, and the chip area is increased. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a noise filter can be provided in a power supply wiring by using an automatic placement design without prolonging a design period, reducing design accuracy, and increasing a chip area. It is an object of the present invention to provide a semiconductor integrated circuit capable of inserting a capacitor for use therein and an automatic layout design method thereof.

[0015]

A semiconductor integrated circuit according to the present invention is provided in parallel with a cell row in which cells are arranged in one row and for supplying a power supply voltage and a ground potential to the cell row. A plurality of pairs of power supply wiring and ground wiring formed so as to pass above the cell row; and intermittent positions in the cell row for drawing power from the pair of power supply wiring and ground wiring to the cell row. A power strap portion connected to a first diffusion layer formed in a surface layer portion of a semiconductor substrate of the cell row or a well region in the semiconductor substrate; and a power supply line provided in the power strap portion, A noise filter capacitor connected to one of the ground wirings.

Further, according to the method of the present invention for automatically arranging and designing a semiconductor integrated circuit, a capacitor for a noise filter is included in a power strap portion for drawing in power to a cell row in which cells are arranged in a row on an integrated circuit chip. And a step of arranging the block pattern at a predetermined frequency in the cell row.

Further, in the method of manufacturing a semiconductor integrated circuit according to the present invention, a step of forming a cell row in which cells are arranged in one row on an integrated circuit chip, and a step of forming a power strap portion for drawing in power of the cell row Forming a capacitor for a noise filter in a region, and forming a power supply line and a ground line so as to pass over the cell row and contact the power strap portion and one of the capacitors is in contact with the capacitor. It is characterized by having.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. The present invention provides an LS having a cell row in which basic circuit elements or unit circuit elements (hereinafter, referred to as cells) for realizing a basic logical function are arranged in a single row.
I.

FIG. 1 shows a gate array type or standard cell type LS according to a first embodiment of the present invention.
1 schematically shows an example of a pattern layout on an I chip.

FIG. 2 shows the power supply block (power strap) 20 in FIG. 1 taken out.
In FIG. 1, reference numeral 10 denotes a plurality of internal cell rows arranged in a central area on a semiconductor chip. In this internal cell column, cells are arranged in a straight line (one column) in a row direction (row direction), for example.

The power supply voltage V is applied to the cells on the internal cell row 10.
dd, first power supply wiring 2 for supplying ground potential Vss
4. First ground wirings 25 are formed near both ends in the column direction.

The power supply wiring 24 and the ground wiring 25
The second power supply wiring 21 and the second ground wiring 22 for supplying the power supply voltage Vdd and the ground potential Vss are paired, and a plurality of pairs of the power supply wiring 21 and the ground wiring 22 are connected to the plurality of internal cell columns. 10 above the power supply wiring 24 and the ground wiring 2
5 are formed in parallel with each other so as to pass in a direction intersecting (for example, at right angles) with an appropriate interval between each pair.

The first power supply wiring 24 and the first ground wiring 22 are made of, for example, a first layer metal wiring, and the second power supply wiring 21 and the second ground wiring 22 are made of, for example, a second layer metal wiring. Consists of The second power supply wiring 21 and the first power supply wiring 24 are connected via a via contact 23, and the second ground wiring 22 and the first ground wiring 25 are connected via the via contact 23. Have been.

In a gate array type LSI, each cell has one PMOS transistor and one NM.
A basic circuit element having an OS transistor is formed. In the standard cell type LSI, for example, one cell such as one two-input NAND gate, one two-input NOR gate, or one inverter circuit is formed as each cell.

In a peripheral region on the semiconductor chip where the plurality of internal cell rows 10 are formed in a central region (internal cell region), input / output circuit portions arranged along each side are formed. I have.

In order to arrange the internal cell row 10, the power supply wiring 21, the ground wiring 22, and the like, an automatic layout design by CAD is performed. Then, the power supply wiring 21 and the ground wiring 2
The power strap 20 is arranged at an intermittent position in the region of the internal cell row in order to draw power from the second to the internal cell row 12. This, of course, the position of the power strap is incorporated into the automatic placement design procedure.

The software for performing the automatic placement design by CAD is to place and route the gates forming the cells by using a netlist connecting constituent units called individual cells.

That is, in the method for automatically arranging and designing an LSI according to the above-described embodiment, a capacitor for a noise filter is provided in a power strap section 20 for drawing in power to a cell row 10 in which cells are arranged in one row on an LSI chip. Preparing the included capacitor block pattern data at a predetermined frequency in the cell row 10 (an appropriate frequency calculated in consideration of an operation frequency, a process, and the like of a target LSI to be designed); Arranging a capacitor block pattern, thereby enabling addition of a desired capacitor using automatic arrangement design.

Further, in the method of manufacturing an LSI according to the above-described embodiment, a step of forming a cell row 10 in which cells are arranged in one row on an LSI chip, and a power strap section for drawing in power of the cell row 10 Forming a capacitor for a noise filter in a formation area of 20;
Forming a power supply wiring 21 and a ground wiring 22 so as to pass above the cell row 10 and contact the power strap portion 20 and one of the capacitors is in contact with the capacitor.

Next, different examples of the configuration of the capacitor for the noise filter will be specifically described with reference to FIGS. FIG. 3A shows a plane pattern of a capacitor block according to Configuration Example 1 of a capacitor for a noise filter.
3B and 3C show an example of a cross-sectional structure along the -C line.

3A to 3C, reference numeral 30 denotes a well region (or silicon substrate) in a semiconductor substrate (silicon substrate) in which a cell row is formed, and 31 denotes the second power supply in the cell row. A first diffusion layer 32 formed in a lower portion of the wiring 21 is used for forming the second ground wiring 22 in the cell column.
A second diffusion layer 33 formed in a lower portion of the semiconductor substrate is an insulating layer formed on the semiconductor substrate.

Reference numeral 34a denotes a first conductive layer (first capacitor) made of, for example, polysilicon and having a predetermined width and formed on the first diffusion layer 31 so as to face the gate via a gate insulating film 35. Electrodes) and 34b are formed on the second diffusion layer 32 with a gate insulating film 35 therebetween so as to be opposed to each other with a second conductive layer (for example, polysilicon) having a predetermined width and made of polysilicon. Electrode). The first capacitor electrode 34a and the second capacitor electrode 34b can be formed simultaneously.

Reference numeral 36a denotes a first capacitor contact portion in which the first power supply wiring 24 is in contact with the first capacitor electrode 34a via a contact hole formed in the insulating layer 33.

Reference numeral 36b denotes a first well contact portion (a power supply node of a cell) in which the first power supply wiring 24 is in contact with the second diffusion layer 32 through a contact hole formed in the insulating layer 33. It is.

Reference numeral 37a denotes a second well contact portion (a ground node of a cell) in which the first ground wiring 25 is in contact with the first diffusion layer 31 through a contact hole formed in the insulating layer 33. It is.

Reference numeral 37b denotes a second capacitor contact portion in which the first ground wiring 25 contacts the second capacitor electrode 34b through a contact hole formed in the insulating layer 33.

The first power supply wiring 24 and the first
The ground wiring 25 is patterned after a first-layer metal wiring is formed on the entire surface of the insulating layer 33, and the contact portions 36a, 36b, and 36 are simultaneously formed when the first-layer metal wiring is formed. 37a and 37b are formed.

In the first configuration example, the first gate capacitance C1 exists at a portion where the first capacitor electrode 34a and the first diffusion layer 31 are opposed to each other, and the second capacitor electrode 3
A second gate capacitance C2 exists at a portion where the second diffusion layer 32 and the second diffusion layer 32 face each other.

That is, in the configuration example 1, the capacitor for the noise filter is realized by the gate capacitances C1 and C2 formed in the capacitor block, and the frequency of the arrangement of the capacitor depends on the operating frequency of the LSI and the process. Is determined in consideration of the type and number of logic gates to be arranged.

FIG. 4A shows a plane pattern of a capacitor block according to a configuration example 2 of a capacitor for a noise filter, and is an example of a cross-sectional structure taken along line BB and line CC in FIG. Are shown in FIGS. 4B and 4C.

4A to 4C, FIG.
The same parts as those in (c) are denoted by the same reference numerals. 30
a is a semiconductor substrate on which a cell column is formed, 301 is a first well region for applying a power supply potential formed in the cell column,
302 is a second well region formed in the cell row, 41
Is a first well contact diffusion layer formed in the first well region 301 below the second power supply line 21, and 42 is a second well region below the second power supply line 21. It is a first junction capacitance forming diffusion layer formed in 302.

Reference numeral 303 denotes a third well region formed in the cell column for applying a ground potential, 304 denotes a fourth well region formed in the cell column, and 43 denotes a lower portion of the second ground wiring 22. The second well formed in the third well region 303
Well contact diffusion layer 44 is the second ground wiring 2
2 is a second junction capacitance forming diffusion layer formed in the fourth well region 304 below the second well region 304.

Reference numeral 46a denotes the first power supply wiring 24 via the contact hole formed in the insulating layer 33 formed on the semiconductor substrate to allow the first junction capacitance forming diffusion layer 4 to be formed.
2 is a first capacitor contact portion that is in contact with 2.

Reference numeral 46b denotes a first well contact portion (of a cell) in which the first power supply wiring 24 contacts the first well contact diffusion layer 41 through a contact hole formed in the insulating layer 33. Power supply node).

Reference numeral 47a denotes a second well contact portion (of a cell) in which the first ground wiring 25 contacts the second well contact diffusion layer 43 through a contact hole formed in the insulating layer 33. Ground node).

Reference numeral 47b denotes a second capacitor contact portion in which the first ground wiring 25 is in contact with the second junction capacitance forming diffusion layer 44 via a contact hole formed in the insulating layer 33. .

Each of the contact portions 46a, 46
b, 47a and 47b are formed simultaneously with the formation of the first metal wiring layer. In the above configuration example 2, the first junction capacitance forming diffusion layer 42 and the second well region 30
The second junction capacitance C1 exists at the junction between the second junction capacitance C1 and the second junction capacitance forming diffusion layer 44 and the second fourth well region 304. Exists.

That is, in the configuration example 2, the capacitor for the noise filter is realized by the junction capacitances C1 and C2 of the diffusion layers 42 and 44 formed in the capacitor block. It is determined in consideration of the operating frequency of the LSI, the process, and the type and number of logic gates to be arranged.

FIG. 5A shows a plane pattern of a capacitor block according to a third configuration example of a capacitor for a noise filter, and is an example of a cross-sectional structure along the line BB and line CC in FIG. Are shown in FIGS. 5B and 5C.

5A to 5C, FIG.
The same parts as those in (c) are denoted by the same reference numerals. 51
Is a first insulating film formed on the silicon substrate (or a well region in the silicon substrate) 30.

52a is the second power supply wiring 2 in the cell row.
A first polysilicon layer formed on a portion of the first insulating layer 51 located below the first layer.
(A first capacitor electrode).

52b is the second ground wiring 2 in the cell column.
A second polysilicon layer formed on a part of the first layer insulating film 51 located below the second polysilicon layer 51;
(A second capacitor electrode).

Reference numeral 53a denotes a third conductive film made of a second polysilicon layer having a predetermined width and formed on a part of the first conductive film 52a with a capacitor insulating film 55 interposed therebetween. (Third capacitor electrode).

Reference numeral 53b denotes a fourth conductive film made of a second polysilicon layer having a predetermined width and formed on a part of the second conductive film 52b with a capacitor insulating film 55 interposed therebetween. (Fourth capacitor electrode).

Reference numeral 54 denotes a second layer insulating film formed on the first layer insulating film 51 and on the third conductive film 53a and the fourth conductive film 53b. 56a is the insulating film 5 of the second layer
4 is a first capacitor contact portion in which the first power supply wiring 24 is in contact with the third conductive film (third capacitor electrode) 53a via a contact hole formed in the fourth conductive film.

Reference numeral 56b denotes the first power supply wiring 24 via a contact hole formed in the second-layer insulating film 54.
Is a second capacitor contact portion that is in contact with the second conductive film (second capacitor electrode) 52b.

Reference numeral 57a denotes the first ground wiring 25 via a contact hole formed in the second layer insulating film 54.
Is a third capacitor contact portion which is in contact with the first conductive film (first capacitor electrode) 52a.

Reference numeral 57b denotes the first ground wiring 2 through a contact hole formed in the second layer insulating film 54.
Reference numeral 5 denotes a fourth capacitor contact portion that is in contact with the fourth conductive film (fourth capacitor electrode) 53b.

Each of the contact portions 56a, 56
b, 57a and 57b are formed simultaneously when the first metal wiring layer is formed. In the above configuration example 3, the first capacitor C1 exists in a portion where the first conductive film (first capacitor electrode) 52a and the third conductive film (third capacitor electrode) are opposed to each other. A second junction capacitance C2 exists at a portion where the second conductive film (second capacitor electrode) 52b and the fourth conductive film (fourth capacitor electrode) 53b face each other.

That is, in the above configuration example 3, the capacitor for the noise filter is realized by the interlayer capacitances C1 and C2 of two layers of polysilicon formed in the capacitor block. , LS
It is determined in consideration of the operating frequency of I, the process, and the type and number of logic gates to be arranged.

Note that a plurality of pairs of the second power supply wirings 21 and the second
Are arranged so as to pass above the plurality of internal cell rows, so that contacts can be easily formed directly below power supply wiring 21 and ground wiring 22, respectively. Therefore, it is not necessary to form a special internal wiring for power supply, and the layout of the pattern becomes possible.

According to the automatic placement design method of the above embodiment, when a noise filter capacitor for removing noise superimposed on the power supply wiring is inserted as a noise reduction measure, each of the noise generation sources A capacitor can be arranged in the vicinity of the gate, and the arrangement interval and the sum of the capacitances are mechanically determined by an appropriate calculation method.

As a result, a desired capacity can be produced in a short time without error by using the automatic design method, so that the design efficiency can be greatly improved. Further, since the additional insertion of the capacitor for the noise filter is not performed near the final step of the chip design, it is possible to prevent a burden on the design verification and a prolonged design period.

The above embodiments are only some of the embodiments of the present invention, and the shape and size of the noise filter capacitor formed in the capacitor block are determined by various conditions. However, the present invention is not limited to the above embodiments.

Each of the above embodiments is only a part of the embodiment of the present invention, and the shape and size of the noise filter capacitor formed in the capacitor block are determined under various conditions. However, the present invention is not limited to the above embodiments. Further, in each of the above embodiments, the case where the power supply system is one system is shown, but the present invention can be applied to the case where there are two or more power supply systems.

[0066]

As described above, according to the present invention, a capacitor for a noise filter is provided on a power supply wiring by using an automatic placement design without causing a prolonged design period, a decrease in design accuracy, and an increase in chip area. It is possible to provide a semiconductor integrated circuit that can be inserted, an automatic layout design method and a manufacturing method thereof.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an example of a pattern layout on a chip of a gate array type or standard cell type LSI according to a first embodiment of the present invention.

FIG. 2 is a pattern diagram showing a capacitor block in which a power-supply power strap portion in FIG.

3 is a diagram showing an example of a planar pattern and a cross-sectional structure of a capacitor block according to a configuration example 1 of a capacitor for a noise filter in FIG. 2;

FIG. 4 is a diagram showing an example of a planar pattern and a cross-sectional structure of a capacitor block according to a configuration example 2 of the capacitor for a noise filter in FIG. 2;

FIG. 5 is a diagram showing an example of a planar pattern and a cross-sectional structure of a capacitor block according to a configuration example 3 of the capacitor for a noise filter in FIG. 2;

[Explanation of symbols]

 24: first power supply wiring, 25: first ground wiring, 31, 32: diffusion layer, 33: insulating layer, 34a, 34b: conductive layer, 35: gate insulating film, 36a, 36b, 37a, 37b: contact Department.

Claims (6)

[Claims] 1. A cell row in which cells are arranged in one row, and a cell row is provided in parallel to supply a power supply voltage and a ground potential to the cell row, and each is formed so as to pass above the cell row. A plurality of pairs of power supply wiring and ground wiring, and a semiconductor substrate or semiconductor of the cell row, which is provided at an intermittent position in the cell row to draw power from the pair of power supply wiring and ground wiring to the cell row. A power strap portion connected to a first diffusion layer formed in a surface layer portion of a well region in the substrate; and a noise filter provided in the power strap portion and connected to one of the power supply wiring and the ground wiring. A semiconductor integrated circuit comprising: a capacitor. 2. The semiconductor integrated circuit according to claim 1, wherein the capacitor for the noise filter includes: a second diffusion layer formed on a surface of a semiconductor substrate in the cell row or a well region in the semiconductor substrate; A conductor for a capacitor electrode formed on the semiconductor substrate via a gate insulating film so as to face at least a part of the second diffusion layer, and connected to one of the power supply wiring and the ground wiring. A semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the capacitor for the noise filter includes a well region formed in a surface layer of a semiconductor substrate in the cell row, and at least a part of a surface layer of the well region. Formed in
A second diffusion layer connected to one of the power supply wiring and the ground wiring. 4. The semiconductor integrated circuit according to claim 1, wherein the capacitor for the noise filter comprises a first polysilicon layer formed on a semiconductor substrate of the cell row via a first insulating film. And a power supply line and a ground line formed on the first conductor via a second insulating film for a capacitor insulating film so as to face at least a part of the first conductor. And a second capacitor electrode made of a second polysilicon layer connected to one of the first and second semiconductor integrated circuits. 5. A step of preparing in advance block pattern data including a noise filter capacitor in a power strap section for drawing in power to a cell row in which cells are arranged in a row on an integrated circuit chip; Arranging the block pattern at a predetermined frequency in a column. 6. A step of forming a cell row in which cells are arranged in a row on an integrated circuit chip, and a step of forming a capacitor for a noise filter in a region where a power strap section for power supply of the cell row is to be formed. And a step of forming a power supply wiring and a ground wiring so as to pass above the cell row, contact the power strap portion, and contact at least one of the capacitors. Manufacturing method.