JPH11204766A - Semiconductor integrated circuit and its design method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit which can surely restrain noise. SOLUTION: Layout of a basic cell, a power source line and a ground line is performed (S1). After size and arrangement interval of each bypass capacitor are temporarily set (S2), the bypass capacitors are arranged in vacant regions, in accordance with layout of the basic cell, the power source line, the ground line, etc., (S3). When desired arrangement of the bypass capacitors is obtained, that arrangement is made the final arrangement (S5). When desired arrangement is not obtained, size and arrangement interval of the bypass capacitors are set again (S7). Processes of rearrangement of the respective bypass capacitors are repeated until desired arrangement of the bypass capacitors is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for designing the same, and more particularly to an arrangement of a bypass capacitor in a chip used as a measure against noise.

[0002]

2. Description of the Related Art The operating speed of semiconductor integrated circuits has been improving year by year with the progress of semiconductor manufacturing process technology.
The operation speed of MOS type semiconductor integrated circuits has been remarkably improved. As the operating speed of such a semiconductor integrated circuit increases, the change in charging / discharging current to a load in the circuit becomes sharp, and the power supply voltage fluctuates in the conventional power supply wiring layout method. There was a problem that speed could not be obtained. In addition, the operation of the circuit itself has been unstable due to power supply noise caused by fluctuations in the power supply voltage. The problem of malfunction due to this type of noise has become a particularly serious problem in recent years, as LSI miniaturization and voltage reduction have further advanced.

Conventionally, as a countermeasure against noise as described above, L
When mounting an SI on a printed circuit board or the like, a method has been adopted in which a bypass capacitor is mounted between a power supply voltage terminal and a ground terminal of the LSI. A bypass capacitor prevents noise generated from a power supply or an external element of an LSI from entering a semiconductor integrated circuit through a power supply wiring, and at the same time, noise generated in the semiconductor integrated circuit through a power supply wiring. This is an element for preventing leakage to the outside. However, in this method, the bypass capacitor is set to L
Since mounting is performed using the lead terminals of the SI, it is affected by the parasitic resistance, the parasitic inductance, and the like of the lead terminals, and there is a certain limit to the reduction of noise.

Therefore, a method of forming a bypass capacitor inside an LSI has been proposed. For example, in Japanese Patent Application Laid-Open Nos. 1-239964 and 5-13672, a power supply line and a ground line are formed so as to be approximately the same width via an insulating layer, and the power supply line and the ground line are bypassed. Constructs a capacitor. Japanese Patent Application Laid-Open No. 5-48020 discloses an example in which a gate capacitance between a gate electrode and a substrate is used as a bypass capacitor.

[0005]

SUMMARY OF THE INVENTION However, LSI
In a conventional noise countermeasure in which a bypass capacitor is formed inside, a place where a bypass capacitor is formed in a semiconductor integrated circuit, the number of bypass capacitors, and the like are limited for reasons of layout design. As a result, a bypass capacitor cannot be formed at a necessary portion in a semiconductor integrated circuit, or a biased portion is formed in a portion where the bypass capacitor is formed. It was insufficient as a noise countermeasure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and in particular, is an LSI in which a number of basic cells are continuously arranged, such as a cell-based LSI and a gate array.
An object of the present invention is to provide a semiconductor integrated circuit capable of reliably suppressing noise generated in a chip and noise entering from the outside via a power supply line, and a method of designing the same.

[0007]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention comprises a plurality of basic cells,
A plurality of power supply lines and ground lines arranged over these basic cells and formed with an interlayer insulating film interposed therebetween, and electrodes and interlayer insulating films respectively drawn from these power supply lines and ground lines to empty areas of the basic cells. And a bypass capacitor. Further, it is preferable that the plurality of bypass capacitors be arranged in a distribution constant in the chip.

In the method of designing a semiconductor integrated circuit according to the present invention, a layout of a plurality of basic cells and a power supply line and a ground line is implemented, and the size of each bypass capacitor and the interval between the bypass capacitors are provisionally set. When the bypass capacitors whose sizes and arrangement intervals are provisionally set are arranged in the empty areas of the basic cells according to the layout of the basic cells, power supply lines and ground lines, respectively, and the desired arrangement of the bypass capacitors is obtained. Makes the arrangement the final arrangement, but if the desired arrangement of the bypass capacitors is not obtained, the size and arrangement interval of the bypass capacitors are set again, and then the respective bypass capacitors are arranged again. Characterized by repeating the procedure until the desired arrangement of bypass capacitors is obtained. A. In this case, it is preferable that the arrangement of the bypass capacitors be a distribution constant arrangement.

In other words, in laying out the bypass capacitor, the place where the bypass capacitor is arranged is determined on the power supply line, the ground line, or the free area of the basic cell in the conventional concept, and the size of the bypass capacitor is determined from the required capacitance value. The arrangement was performed after being fixed uniformly. On the other hand, in the design method of the present invention, after temporarily setting the size and arrangement interval of the bypass capacitors,
Arrange bypass capacitors based on the layout of basic cells, power supply lines, ground lines, etc., and even if the desired arrangement of bypass capacitors is not obtained, set the size and arrangement interval of bypass capacitors again and redo the arrangement This is the biggest feature.

As described above, by giving a certain degree of freedom to the size and arrangement interval of the bypass capacitors and repeating the operation of rearranging the bypass capacitors so as to conform to the chip layout, it is possible to arrange the bypass capacitors as desired. Obtainable. If, for example, the bypass capacitors are arranged in a distributed constant manner in the chip, it is possible to reliably suppress noise generated in the chip and noise entering from the outside via the power supply line over the entire circuit. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a flowchart showing the procedure of the method for designing a semiconductor integrated circuit according to the present embodiment. FIGS. 2A and 2B are views showing the arrangement of bypass capacitors.

First, as an LSI to which the design method of this embodiment is applied, an LSI in which basic cells of the same size are continuously arranged, such as a cell-based LSI and a gate array, is used.
Target. Then, in an LSI interlayer structure having a structure in which a power supply line layer and a ground line layer are wired via an interlayer insulating film, a power supply line pattern and a ground line pattern face each other via an interlayer insulating film. The bypass capacitor is configured by actively utilizing the parasitic capacitance generated at the location where the power supply is located. As a specific configuration, as shown in FIG. 2B, a power supply line 2 and a ground line 3 are arranged over a plurality of basic cells 1a and 1b.
And wirings 4 and 5 respectively drawn from the ground line 3
Are provided, and a bypass capacitor 8 is formed by the electrodes 6, 7 and an interlayer insulating film interposed between the electrodes 6, 7.

FIG. 2A is a diagram showing a state in which the bypass capacitors 8 are arranged in a distributed constant manner in the vacant areas of the basic cells 1a and 1b inside the LSI chip. The arranged empty area and the area 9b surrounded by the broken line are empty areas where the bypass capacitor 8 is not arranged.

Next, the procedure of the method for designing a semiconductor integrated circuit according to the present embodiment will be described with reference to FIG. This method is, of course, an automatic layout method using CAD. As shown in FIG. 1, first, as a first step, an extremely common chip layout is performed (step S1 in FIG. 1). That is, a large number of basic cells 1a, 1b,
The layout of the entire chip including the arrangement of the power supply line 2, the ground line 3, and the like is implemented. Especially in the configuration of the logic circuit,
In the case of a cell base, a gate array or the like, as shown in FIG. 2B, the power supply line 2 and the ground line 3 are generally arranged in a horizontal or vertical direction while keeping a slight distance.

On the other hand, the size of each bypass capacitor 8 and the arrangement interval between the bypass capacitors 8 are provisionally set (step S2 in FIG. 1). That is, the dimensions of the electrodes 6 and 7 constituting one bypass capacitor 8 and the pitch between adjacent bypass capacitors 8 are provisionally set to appropriate values in advance.

Next, as a second stage, the bypass capacitors 8 whose sizes and arrangement intervals are temporarily set in step S2 are arranged in the empty areas of the basic cells 1a and 1b (step S3 in FIG. 1). Here, a bypass capacitor 8 having a size set in advance in the space between the power supply line 2 and the ground line 3 based on the CAD data at the time of the first-stage layout along the power supply line 2 and the ground line 3 Are extracted, and the bypass capacitors 8 are arranged at all of the positions where they can be formed.

The bypass capacitor 8 is formed in an empty area between the basic cells 1a and 1b or an empty area for signal wiring (omitted in the present description). However, in the logic circuit layout method, the basic cells 1a and 1b are formed. Basic dimensions are determined at the beginning of design with respect to the wiring width, wiring pitch, and the like of signal wiring. Therefore, it is possible to determine the possibility of disposing the bypass capacitor 8 after the layout in the first stage by analyzing the information of the layout result.

Next, it is determined whether or not the desired arrangement of the bypass capacitors 8 has been obtained (step S in FIG. 1).
4). Here, the desired arrangement means that the designer of the semiconductor integrated circuit can judge that this is sufficient. For example, a distribution constant arrangement having a high suppression effect on noise may be considered. If the desired arrangement of the bypass capacitors 8 is obtained by one arrangement work (step S5 in FIG. 1), the design is finished with the arrangement as the final arrangement.

On the other hand, when the desired arrangement of the bypass capacitor 8 cannot be obtained (step S6 in FIG. 1).
In step (1), the size and arrangement interval of the bypass capacitors 8 are reset (step S7 in FIG. 1), and the respective bypass capacitors 8 are rearranged. Then, the procedure of step S3 is repeated until the desired arrangement of the bypass capacitors 8 is obtained.

In the design method of the present embodiment, after temporarily setting the size and arrangement interval of the bypass capacitor 8, the bypass capacitor 8 is set based on the CAD data of the basic cells 1a and 1b, the power supply line 2, the ground line 3, and the like. Even if the desired arrangement of the bypass capacitors 8 is not obtained at one time, the size and arrangement interval of the bypass capacitors 8 are reset and the arrangement of the bypass capacitors 8 is repeated. Therefore, by repeating the operation of rearranging the bypass capacitors 8 so as to match the chip layout of the semiconductor integrated circuit, the desired arrangement of the bypass capacitors 8 can be obtained, and the distribution of the bypass capacitors 8 in the chip can be distributed in a constant manner. Can be. As a result, not only switching noise generated from the logic circuit itself but also an effective means for reliably preventing malfunctions over the entire circuit with respect to noise entering from outside through a power supply line.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the specific size and arrangement interval of the bypass capacitors can be set as appropriate.

[0022]

As described above in detail, according to the present invention, it is possible to arrange bypass capacitors as desired by a designer in an LSI chip, and it is also possible to arrange bypass capacitors in a distributed constant manner. Will be possible. As a result, a high noise suppression effect can be expected over the entire semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of a method of designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2A is a diagram illustrating an arrangement of bypass capacitors in the entire chip, and FIG. 2B is an enlarged view of a portion where bypass capacitors are formed.

[Explanation of symbols]

 1a, 1b Basic cell 2 Power line 3 Ground line 4, 5 Wiring 6, 7 Electrode 8 Bypass capacitor

Claims (4)

[Claims] 1. A semiconductor integrated circuit design including a plurality of basic cells, a power supply line and a ground line arranged over the basic cells, and a plurality of bypass capacitors electrically connected to the power supply line and the ground line. Laying out the plurality of basic cells, the power supply line and the ground line, temporarily setting the size of each of the bypass capacitors and the arrangement interval between the bypass capacitors, and then temporarily setting the size and the arrangement interval. Each of the set bypass capacitors is arranged in an empty area of the basic cell according to the layout. When a desired bypass capacitor arrangement is obtained, the arrangement is set as a final arrangement, If the arrangement of the bypass capacitor cannot be obtained, Method for designing a semiconductor integrated circuit, characterized in that repeated until the arrangement of bypass capacitors as desired procedure repositioning each bypass capacitor again is obtained in terms of the re-set the arrangement interval between. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the arrangement of the desired bypass capacitors is a distribution constant arrangement. 3. A plurality of basic cells, a power supply line and a ground line arranged over the basic cells and formed with an interlayer insulating film interposed therebetween, and each of the power supply line and the ground line is placed in an empty area of the basic cell. A semiconductor integrated circuit comprising: a plurality of bypass capacitors each including an extracted electrode and the interlayer insulating film. 4. The semiconductor integrated circuit according to claim 3, wherein said plurality of bypass capacitors are arranged in a distributed constant manner within a chip.