JPS5877245A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To remove a limit on the connecting position of wirings, and moreover to reduce capacity of the wirings on an unused element of a semiconductor integrated circuit device by a method wherein unevenness of the surface of a first insulating film covering the main face of an Si substrate on the side provided with circuit elements of the plural number is compensated with a second insulating film provided thereon. CONSTITUTION:FET's 204, 205 are formed being separated by a field oxide film 206 on a substrate 200, and the places other than a source and a drain 203 and the connecting parts of a first layer metal wiring 207 are covered with PSG 208, and are covered with insulating polyimide films 209 in succession to flatten the upper part of an unused element 205. Therefore disconnection according to a step part is not generated, and a prohibition about the connecting position of the wirings 207, 211 is cancel on the unused element 205. When the connection prohibiting place is canceled by this way, the degree of integration can be enhanced, and moreover the distances between the metal wirings 207, 211 and the substrate 200 are enlarged by interposition of the insulating film 209 to reduce parasitic capacity. Accordingly the speed of a logic gate is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and in particular to a semi-custom LS that is suitable for LSI production of a wide variety of products in small quantities. In other words, it relates to the master slice LSI.

FIG. 1 shows the configuration of a conventional master slice LSI. L
The SI chip 1 has a bonding pad and an input/output circuit area 5 on its outer periphery, and inside it, basic cell rows 3 in which basic cells 2 consisting of elements such as transistors are arranged in the X-axis direction are repeated with a wiring area 4 in between. The configuration is as follows. In order to obtain a desired electrical circuit operation, one or several adjacent basic cells 2 are connected to form a NAND gate or flip-flop. One LSI is constructed by connecting various logic gates formed by a plurality of basic cells 2 according to a logic diagram.

However, in a master slice LSI in which only wiring-related masks are changed, the width of the wiring area 4 is fixed regardless of whether there are many or few wirings. Therefore, if there are few wires, a lot of space is freed up.

The implementation efficiency was poor. Therefore, the inventors first proposed a method of embedding elements such as transistors under the conventional wiring area 4 so that various circuits can be constructed without wasting the elements and wiring area.

However, if an element is buried under the wiring area 4, the following 3
There are two drawbacks.

(1) The level difference becomes severe at or around the boundary of the embedded element, making it more likely that the At wiring will be disconnected.
A7 of the first layer wiring. and At2 of the second layer wiring of A7
There are restrictions on the position of contacts between wiring lines. This becomes a limitation when automatic wiring is performed by a computer on an unused embedded element, and this results in a substantial reduction in the number of wiring channels, resulting in unwired wiring.

(11) The distance between the unused buried element and the substrate is shorter than that on the field oxide film in the conventional wiring region 4. Therefore, the parasitic capacitance of the wiring passing over the unused buried elements increases, and the speed of the logic gate decreases.

Old At wiring that passes through areas with severe differences cannot be made thinner from the reliability standpoint.

There is no choice but to make the wire thicker, but increasing the wire capacitance increases the speed of the logic gate.

An object of the present invention is to provide a semiconductor integrated circuit device that eliminates the above-mentioned drawbacks.

Specifically speaking, the purpose of the present invention is to provide A4. It is an object of the present invention to provide a master slice type semiconductor integrated circuit device which eliminates restrictions on the contact positions of and At2 and reduces wiring capacitance on unused elements.

A feature of the semiconductor integrated circuit device of the present invention that achieves the above object is that the unevenness occurring on the surface of the first insulating film covering the main surface of the semiconductor substrate on the side on which a large number of circuit elements are formed is removed. This is compensated for by the second insulating film made of an organic material formed in the above-mentioned manner.

An embodiment of the present invention will be described below with reference to FIG. Second
The figure shows a part of the cross section of the xx' plane of a new master slice LSI in which elements are embedded in the so-called wiring area 4 of FIG.

A gate oxide film 201 . Gate electrode 20
2. Embedded element 2 with source and drain regions 203
04,205 are configured. There is a field oxide film 206 between elements 204 and 205. Above the devices 204 and 205, the device source and drain regions 203 and 1
Areas other than the connection with the metal wiring 207 of the layer are covered with an adjacent glass insulating film 208. The structure up to this point is an LSI structure using general MOS transistors.

On the adjacent glass insulating film (hereinafter abbreviated as PSG film) 208,
Among the buried elements, an unused element 205 is covered with a polyimide-based organic insulating film 209 in order to flatten the upper part thereof. Since planarization on the unused element 205 has been achieved, there is no restriction on the contact position between the first layer metal wiring 207 and the second layer metal wiring 211 on the unused buried element 205. In FIG. 2, a hole is made in the insulating film 210 on the boundary between the source and drain region 203 of an unused buried element 205 and the field oxide film 206, and the first layer metal wiring 207 and the second layer metal wiring 211 are connected. Connected. Unused element 2
05 is achieved and the above-mentioned limitations are eliminated, the following effects are achieved.

(1) When using an unused element among embedded elements as a wiring area, there are no places where connection is prohibited between the first and second layer metal wiring, so there are no restrictions on automatic wiring using a computer. .

(1i) If there is a place where connection is prohibited, it is necessary to extend the metal wiring to a place where connection is possible, so the number of wiring channels has to be increased, and the degree of integration has decreased.

In the present invention, since there are no prohibited places for connection, the degree of integration can be improved.

01D Also, as you can see from Figure 2, is it on the element?
The distance between the substrate 200 and the metal wirings 207 and 211 passing over the field oxide film 206 and 204, 205 is increased because the negative side is covered with the organic insulating film 209. Therefore, the parasitic capacitance of the metal wiring to the substrate is reduced. This increases the speed of logic gates that propagate signals by charging and discharging capacitances.

Although the above description has been made regarding the structure on the unused element of the embedded element, the same thing can be said when there is an unused basic cell in the basic cell row 3 of FIG.

Next, one manufacturing method for obtaining the structure shown in FIG. 2 will be explained.

As shown in FIG. 3(a), the field oxide film 206. Gate oxide film 201. Gate electrode 202. The process up to forming the source and drain regions 203 and the PSG film 208 is the same as the conventional LSI manufacturing method.

Next, as shown in FIG. 3(b), a film 209 of a polyimide-based organic insulating material, such as polyimide isoindolo quinazolinedione (hereinafter referred to as PIQ), is applied using a spinner. Of course, other insulators can also be used to achieve planarization. Next, as shown in FIG. 3(C), after applying a photoresist film 300, photoresist processing is performed using a photomask 301 for processing the PIQ film, and the PIQ film 200 is
Drill a hole at 9. Here, holes are not made in the PIQ film 209 on the unused elements 205 among the embedded elements 204 and 205. Next, the photoresist film 300 is removed and now [1dP
IQ film 209'f: Instead of photoresist, a hole is made in the PSG film 208 as shown in FIG. 3(d).

Next, as shown in FIG. 3(e), a first layer of metal 207 is deposited, and then photoresist is processed into a wiring pattern.

Here, on the unused embedded element 205 is a PIQ film 209.
Flattening is achieved by Next, as shown in FIG. 3(f), an insulating film 3 insulating the first layer metal wiring 207 is
After applying 02 and photoresist film 303-i, photoresist processing is performed using a photomask 304'e for insulating film processing,
A hole is made in the insulating film 302. In the example shown in the figure, a hole 305 for connecting the first and second layer metals is formed on the boundary between the source and drain region 203 of the unused buried element 205 and the field oxide film 206. There are no restrictions on where to drill the hole. Except for this restriction on the position of the hole, the hole is opened in the usual way. After that, it is a general manufacturing process, and the photoresist film 303 is removed and the second
As shown in the figure, after a second layer of metal 211 is deposited, photoresist processing is performed to form a wiring pattern. After that, a protective film 212 is covered. In this manufacturing method, the PTQ film 209 on the PSG film 208 is used instead of photoresist when making holes in the PSG film 208, so the number of photomasks is the same as in the conventional manufacturing method. As the number of photomasks increases, the process becomes more complicated and the manufacturing cost and manufacturing period increase.

According to the present invention, since wiring can be performed on unused elements in the same image as the wiring area of a conventional master slice, a master slice LSi with high packaging density can be obtained. Also,
Since the parasitic capacitance of the metal wiring can be reduced, a high-speed operation master slice LSI' can be obtained. PSG film 20
The thickness of 8 is 0.5 μm.

If the thickness of the PIQ film 209 is 1.5 μm, the parasitic capacitance of the first layer metal wiring 207 on unused elements will be reduced to one-fourth, so a significant speed improvement can be expected.

[Brief explanation of the drawing]

FIG. 1 is a master chip plan view of a conventional master slice LSI, FIG. 2 is a sectional view of an LSI according to an embodiment of the present invention, and FIG.
The figure is a cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention. 203... Source, drain region, 2o7... First layer metal wiring, 208... Phosphorous glass insulating film, 2o9
...PIQ film, 202...gate electrode, 2o6...
・Field oxide film, 204.205...MOS) range 2θ0 2″5 ~ 200

Claims (1)

[Claims] 1. A semiconductor substrate with a large number of circuit elements arranged side by side on one main surface, and a first insulating film mainly composed of a semiconductor oxide that covers one main surface of the semiconductor substrate. and. A second insulating film formed on the first insulating film and made of an organic material and having a substantially flat surface; a first wiring layer formed on the second insulating film; A semiconductor comprising: a third insulating layer; and a second wiring layer formed on the third insulating layer and connecting circuit elements together with the first wiring layer to a desired circuit configuration. Integrated circuit device. 2. A semiconductor integrated circuit device according to claim 1, characterized in that a polyimide-based organic insulating film is used as the second insulating film.