JPS6035537A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity between each of signal wires by a method wherein conductive plates connected to a constant power source in low resistance are provided on the upper layer or the lower layer of a signal wire layer through an insulating layer. CONSTITUTION:A semiconductor integrated circuit is constituted of a first-layer metal wiring 2 wherein ground wires have been formed, an N type diffusion layer 3 wherein the sources and drains of transistors have been formed, a polycrystalline silicon layer 6 wherein gates have been formed, a silicon oxide film layer 7 which is used for intergate or interlayer insulation, a first passivation layer 8, a second passivation layer 9 and a silicon substrate 10. A polycrystalline silicon layer 11, whereon ground potential has been impressed, and a second-layer metal wiring layer 12, whereon ground potential has been impressed, are provided on the upper layer or the lower layer of a first-layer metal wiring layer 1 wherein signal wires have been formed. As a result, the rate of the electric lines of force, which head for the signal wires 1 and conductive plates 11 and 12, is increased, thereby enabling to reduce the capacity between each of the signal wires.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits.6 As the scale of semiconductor integrated circuits increases, patterns become finer, layers become more multilayered, and circuits become more dynamic. FIG. 1 (atΦ) shows a plan view of an MO8 type integrated circuit and its AA sectional view as an example.

Here, l is a metal wiring layer forming a signal line, 2 is a metal wiring layer forming a ground line, 3 is an N-type diffusion layer forming the source and drain of a transistor, and 4 is a metal wiring layer l and polycrystalline Contact with silicon layer 6, 5 is metal wiring 71
A contact between i and the diffusion layer 3, 6 a polycrystalline silicon layer forming the gate of the transistor, 7 a silicon oxide film forming the gate of the transistor and an interlayer insulating film, and 8 a protective film layer called basivation. Usually, silicon oxide film, nitride film, phosphorus glass, etc. are used. 9 is a silicon substrate.

Conventionally, the capacitance of the signal line, t, metal wiring layer and wafer substrate,
The capacitance between the diffusion layer and the polycrystalline silicon layer of the gate was king, but as patterns become finer, the capacitance between the metal wiring layers is increasing.

That is, as the pattern becomes finer, the spacing between metal wiring layers becomes smaller, but it does not change much in order to ensure the reliability of electromigration, etc. of metal wiring with a thickness of 1 in each layer. For example, in a 256K memory, the passivation is 1 to 2 μm, the width of the metal wiring layer is 3 to 4 μm, and the spacing is 2 μm.
m, thickness is 1 μm.

The distance between the metal wiring layer and the substrate is about lttm. Since a depletion layer with a thickness of 2 μm and 8 degrees is formed on the substrate, the distance from the actual metal wiring layer to the conductive substrate is about 3 μm.

Therefore, lines of electric force increase between adjacent signal lines through passivation above and below the signal lines and insulating bands of depletion layers, resulting in an increase in capacitance between adjacent signal lines. In this example, about 50% of the total capacitance of one signal line is the capacity M between adjacent signal lines. For this reason, when the potentials of other signal lines are abruptly changed, a dynamic circuit has a drawback in that a signal line at a floating potential generates large noise.

The present invention eliminates these drawbacks of the conventional circuit and provides a semiconductor integrated circuit in which the capacitance between signal lines is reduced.

According to the present invention, there is obtained a semiconductor integrated circuit characterized in that it has a conductive plate connected to a constant power source with low resistance through an insulating layer above or below a signal line layer.

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 2(a) and 2(b) show a plan view and a sectional view taken along line 70BB of an embodiment of the present invention. Here, 1 is the first line forming the signal line.
2 is the first metal wiring layer to which a ground voltage of about 11t is applied; 3 is an N-type diffusion layer forming the source and drain of the transistor; 4 is the first metal wiring layer 1 is a contact between the polycrystalline silicon layer 6 and the first metal wiring layer 2 and the polycrystalline silicon WIii; 5 is a contact between the first metal wiring layer l and the diffusion layer 3;
6t is polycrystalline silicon IN forming the gate of the transistor, 7td is a silicon oxide film layer used for the gate of the transistor or insulation between layers, 8 is the passivation 7M of the first passivation L'1tlil'E2, l
The ot, t silicon substrate II is a polycrystalline silicon layer to which a ground potential is applied, and the distance from the fifth metal wiring layer l is about 0.5 μm. Reference numeral 12 denotes a second metal wiring layer to which a ground potential is applied, and the distance from the first metal wiring layer 1 is approximately I Itm. 13 is a contact between the first and second metal wiring layers.

As shown in this example, if a conductive plate 11.12 with low resistance and a constant potential is provided on the upper or lower layer of the signal line l, the proportion of electric lines of force directed toward the signal line l and the conductive plate 11°12Vc increases. The amount of '8 between signal lines is reduced.

The present invention is not limited to MO8 type integrated circuits, but is also effective in other integrated circuits by forming a four-electric plate with low resistance and a constant potential applied on the upper or lower layer of the signal line.

According to the present invention, as described above, the capacitance between signal lines in a semiconductor integrated circuit can be reduced.

[Brief explanation of the drawing]

Fig. 1(a) (bl is a top view showing a conventional MO8 type integrated circuit and its A-A sectional view, and Fig. 2(a) (bl is a top view showing an embodiment of the present invention and its B-A sectional view). B sectional view -1
. . . 1st NjI metal wiring layer forming a signal line, 2 . . . 1st metal wiring layer forming a ground line, 3 . . . Diffusion layer, 4...1st
Contact between the N4 metal wiring layer and the polycrystalline silicon layer, 5...Contact between the first layer metal wiring layer and the diffusion layer, 6...Form the gate of the transistor. Polycrystalline silicon layer, 7... silicon oxide film layer, 8... first passivation layer, 9...
- Second passivation layer, 10... silicon substrate, 11... polycrystalline silicon layer to which ground potential is applied, 12... second passivation layer to which ground potential is applied Layer metal wiring layer, 13...Contact between the first and second metal wiring layers. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A semiconductor integrated circuit characterized by having a conductive plate connected to a constant power source with low resistance through an insulating layer above or below a signal line layer.