JPH02264432A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02264432A JPH02264432A JP1086004A JP8600489A JPH02264432A JP H02264432 A JPH02264432 A JP H02264432A JP 1086004 A JP1086004 A JP 1086004A JP 8600489 A JP8600489 A JP 8600489A JP H02264432 A JPH02264432 A JP H02264432A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- parasitic resistance
- metallic
- gnd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002356 single layer Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野Ｊ
この発明は、半導体装置における金属配線の構造に関す
るものである・
〔従来の技術〕
第３図は従来の半導体メモリ装置のチップの概略を示す
平面図である。図において、（１）はＩＣチップ、（２
）はメモ湾レイ、（３）は外部より電源Ｖｃｃが供給さ
れるＶｃｃパッドであり、ここよｐ Ｖｃｃ側周辺回路
（７）、ＧＮＤ側周辺回路（８）及びメモリセルアレイ
（２）に、金属配線を用いて電源Ｖｃｃが供給される。[Detailed Description of the Invention] [Industrial Application Field J] This invention relates to the structure of metal wiring in a semiconductor device. [Prior Art] Fig. 3 schematically shows a chip of a conventional semiconductor memory device. FIG. In the figure, (1) is an IC chip, (2
) is the memory cell array, and (3) is the Vcc pad to which the power supply Vcc is supplied from the outside. Power supply Vcc is supplied using wiring.
このとき、ＧＮＤ側周辺回路（８）への電源Ｖｃｃの供
給は、長いＶｃｃ配＃１（５）を介して行われる。At this time, the power supply Vcc is supplied to the GND side peripheral circuit (8) via the long Vcc wiring #1 (5).
（４）は外部より接地電位ＧＮＤが供給されるＧＮＤバ
ンドであり、ここよりＶｃｃ側周辺回路（７）、ＧＮＤ
側周辺回路（８）及びメモリセルアレイレ）に、金属配
線を用いて接地電位ＧＮＤが供給される。この時、Ｖｃ
ｃ側周辺回路（７）への接地電位ＧＮＤの供給は、長い
（ＩＩＤ配線（６）を介して行われる。(4) is the GND band to which the ground potential GND is supplied from the outside, and from here the Vcc side peripheral circuit (7), the GND band
The ground potential GND is supplied to the side peripheral circuit (8) and the memory cell array (memory cell array) using metal wiring. At this time, Vc
The ground potential GND is supplied to the c-side peripheral circuit (7) via a long IID wiring (6).
従来の半導体メモリ装置は以上のように構成されている
ので、近年、メモリ容量の増加に伴ない、チップサイズ
が増大してくるにつれて、Ｖｃｃ配線（５）及びＧＮＩ
）配線（６）における金属１！ｉａ線の寄生抵抗が無視
できなくなってき九。すなわちＶｃｃ（ＩｌｌＦ！４辺
回路（７）においてＧＮＤが浮き上がったり、逆にＧＮ
Ｄ側周辺回路（８）においてＶｃｃ Ｋ衰退が生じたり
して、強いては、これがノイズ不良の原因になるという
問題点が生じてきた。Conventional semiconductor memory devices are configured as described above, and in recent years, as memory capacity has increased and chip size has increased, Vcc wiring (5) and GNI
) Metal 1 in wiring (6)! The parasitic resistance of the IA line has become impossible to ignore. In other words, GND rises in the Vcc (IllF!4-side circuit (7)), or conversely, GN
A problem has arisen in that Vcc K decline occurs in the D-side peripheral circuit (8), and this eventually becomes a cause of noise defects.
第４図は上記のノイズ不良が発生するメカニズムを説明
する反転回路とＧＮＤＩＤ配線す回路図、第５図は第４
図の各部の波形を示すタイミングチヤードである。図に
おいて、（９）、（１０）はＶｃｃ４１Ｊ１１辺回路（
７）に金回路る反転回路である。第５図（ａ）に示した
ように反転回路（ｌＯ）に入力される信号ＡがＬ＃から
１Ｎ１１に変化すると、反転回路（１０）のＮｃｈトラ
ンジスタを通じて充放電電流１がＧＮＤに流れ込む。こ
のとき、ＧＮＤバンド（４）の電位ＧＮＤ１は′ｓ５図
（ｂ）に示すように安定しているが、マＣｃ側周辺回路
（７）の接地電位ＧＮＤ２は、ＧＮＤ配線（６）の寄生
抵抗Ｒのため充分速く電流を流し切れず、第５図（ｃ）
Ｋ示すように一時的に浮き上がってしまう。そのため
その他の反転回路（９）に入力される信号Ｂは１．相対
的にみれば、第５図（ｄ）に示すようにノイズが入った
ような状態となる。これが誤動作の原因となる。Figure 4 is a circuit diagram of the inverting circuit and GNDID wiring to explain the mechanism by which the above noise defect occurs, and Figure 5 is the circuit diagram of the inverting circuit and GNDID wiring.
This is a timing chart showing the waveforms of each part in the figure. In the figure, (9) and (10) are Vcc41J11 side circuit (
7) is an inverting circuit with a gold circuit. As shown in FIG. 5(a), when the signal A input to the inverting circuit (lO) changes from L# to 1N11, a charging/discharging current 1 flows into GND through the Nch transistor of the inverting circuit (10). At this time, the potential GND1 of the GND band (4) is stable as shown in Figure 's5 (b), but the ground potential GND2 of the peripheral circuit on the MacC side (7) is due to the parasitic resistance of the GND wiring (6). Because of R, the current cannot flow quickly enough, and as shown in Figure 5(c)
As shown in K, it appears temporarily. Therefore, the signal B input to the other inverting circuit (9) is 1. From a relative point of view, it appears as if noise has been introduced, as shown in FIG. 5(d). This causes malfunction.
この発明は上記のような問題点を解消するためになされ
たもので、電源配線部の面積を増大させることなく、そ
の寄生抵抗値を減少させることにより、チップサイズが
より小さく、ノイズによる誤動作の起ζりにくい半導体
装置を得ることを目的とする。This invention was made to solve the above-mentioned problems. By reducing the parasitic resistance value of the power supply wiring section without increasing its area, the chip size can be made smaller and malfunctions caused by noise can be reduced. The purpose of the present invention is to obtain a semiconductor device that is less likely to cause ζ.
〔課題を解決するための手段および作用〕この発明に係
る半導体装置は、電源配線部の金属配線の厚さを他の回
路部の金属配線の厚さより厚くすることにより、を源配
線部の面積を増大させることなく、その寄生抵抗値を減
少させたものである。[Means and effects for solving the problem] A semiconductor device according to the present invention reduces the area of the source wiring portion by making the thickness of the metal wiring in the power wiring portion thicker than the thickness of the metal wiring in other circuit portions. This reduces the parasitic resistance value without increasing the resistance.
［実施例］
第１図はこの発明の一実施例を示す半導体メモリ装置の
断面図である。第１図の断面図に相当する半導体装置の
平面図は第３図の従来例と同じであるので省略するが、
第１図は第３図に示すＸＸにおける断面を示す。図にお
いて（２）、（５）、（６）は第３図の従来例に示した
ものと同等であるので説明を省略する＊ Ｖｃｃ配線（
５）及びＧＮＤ配ｍ （６）の金属配線は、メモリセル
アレイ（２）部の金属配線よりも厚い。[Embodiment] FIG. 1 is a sectional view of a semiconductor memory device showing an embodiment of the present invention. The plan view of the semiconductor device corresponding to the cross-sectional view in FIG. 1 is the same as the conventional example in FIG. 3, so it will be omitted.
FIG. 1 shows a cross section taken along the line XX shown in FIG. In the figure, (2), (5), and (6) are the same as those shown in the conventional example in Figure 3, so explanations are omitted. *Vcc wiring (
5) and GND wiring The metal wiring in (6) is thicker than the metal wiring in the memory cell array (2) portion.
次に動作について説明する、金属配線の寄生抵抗値Ｒは
、その厚さに反比例するので、これにょシ、電源配線部
の面積を増大させることなく、その寄生抵抗値Ｒを減少
可能である。！、！ｌ！８ｊｕｌ！の寄生抵抗値Ｒが減
少すれば、第４図の例の場合でも、第５図（ｅ）に示す
ようにＶＣＣ側周辺回路（７）の接地電位ＧＮＤ２の一
時的な浮き上が９も低減でき、反転回路（９）に入力す
る信！−Ｂにも、８５図（ｆ’）に示すようにさほど大
きなノイズとなって現われないので、誤動作に至る可能
性は低くなる。The parasitic resistance value R of the metal wiring, whose operation will be described next, is inversely proportional to its thickness, so it is possible to reduce the parasitic resistance value R without increasing the area of the power supply wiring part. ! ,! l! 8jul! If the parasitic resistance value R decreases, even in the case of the example shown in Fig. 4, the temporary rise of the ground potential GND2 of the VCC side peripheral circuit (7) will be reduced by 9 as shown in Fig. 5 (e). The signal input to the inverting circuit (9)! -B as well, as shown in Figure 85 (f'), it does not appear as a very large noise, so the possibility of malfunction is reduced.
第２図（ａ）〜（ｄ）は上記実施例のような金属配線の
構造を容易に得るための製造方法の工程を示す半導体メ
モリ装置の断面図である。図において（１１）は基板、
（１２）は層間膜、（１３）は金属配線材料、（１４）
は１回目レジスト、（１５）は２ｒｆｆＪ目Ｖシストで
ある。まず最初に第２図ｂ）のように層間膜（１２）の
上の全面に厚く金属配線材料（１３）を塗布する。次に
、第２図（ｂ）のように電源配線部のみに１回目レジス
ト（１４）を被せ、全体を異方性エツチングする。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor memory device showing steps of a manufacturing method for easily obtaining a metal wiring structure as in the above embodiment. In the figure, (11) is the substrate,
(12) is an interlayer film, (13) is a metal wiring material, (14)
is the first resist, and (15) is the 2nd rffJth V cyst. First, as shown in FIG. 2b), a metal wiring material (13) is coated thickly over the entire surface of the interlayer film (12). Next, as shown in FIG. 2(b), only the power supply wiring portion is covered with a first resist (14), and the entire area is anisotropically etched.
次に、第２図（ａ）のように、金属配線のパターンすべ
てに２回目レジス） （１５）を被せ、再度異方性エツ
チングする。以上のような製造方法により、第２図（ｄ
）のように、１１図に示すような金属配線の構造を容易
に得ることができる。Next, as shown in FIG. 2(a), the entire metal wiring pattern is covered with a second resist (15) and anisotropically etched again. By the above manufacturing method, the product shown in Fig. 2 (d
), a metal wiring structure as shown in FIG. 11 can be easily obtained.
なお、上記実施例では、ＭＯ８半導体メモリ装置につい
て示したが、これに限らずすべての半導体装置で適用可
能であり、上記実施例と同様の効果を奏する。In the above embodiment, an MO8 semiconductor memory device is shown, but the present invention is not limited to this and can be applied to all semiconductor devices, and the same effects as in the above embodiment can be achieved.
また、上記実施例では、金属配線を厚くするべき電源配
線部としてＶｃｃ配線及びＧＮＤ配線をとり上げたが、
その他すべての電源配線部に適用可能であり、上記実施
例と同様な効果を奏する。In addition, in the above embodiment, the Vcc wiring and the GND wiring were taken up as the power supply wiring part where the metal wiring should be made thicker.
This embodiment can be applied to all other power supply wiring sections, and produces the same effects as the embodiments described above.
［発明の効果］
以上のように、この発明によれば、電源配線部の金属配
線の厚さを他の回路部の金属配線の厚さよりも厚くする
ことにより、電源配線部の寄生抵抗を低減したので、チ
ップサイズは小さく、ノイズによる誤動作の起こりにく
い半導体装置を得ることができる。[Effects of the Invention] As described above, according to the present invention, the parasitic resistance of the power supply wiring section is reduced by making the thickness of the metal wiring in the power supply wiring section thicker than the thickness of the metal wiring in other circuit sections. Therefore, it is possible to obtain a semiconductor device with a small chip size and less likely to malfunction due to noise.
第１図はこの発明の一実施例を示す半導体メモリ装置の
断面図、第２図（ａ）〜（ｄ）は、第１図に示す構造を
得るための製造工程を示す半導体メモリ装置の断面図、
第３図は従来の半導体メモリ装置のチップの概略を示す
平面図、第４図はノイズ不良の発生メカニズムを説明す
る反転回路とＧＮＤ配線を示す回路図、第５図は第４図
の各部の波形を示すタイミングチャートである。
図において（２）はメモリセルアレイ、（５）はＶＣＣ
配線、（６）はＧＮＤ配線、（１１）は基板、（１２）
は層間膜（１３）は金属配線材料、（１４）は１回目レ
ジスト、（１５）は２回目レジストである。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a cross-sectional view of a semiconductor memory device showing an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views of the semiconductor memory device showing manufacturing steps for obtaining the structure shown in FIG. figure,
FIG. 3 is a plan view schematically showing a chip of a conventional semiconductor memory device, FIG. 4 is a circuit diagram showing an inverting circuit and GND wiring to explain the mechanism of noise defect generation, and FIG. 5 shows each part of FIG. 4. 5 is a timing chart showing waveforms. In the figure, (2) is the memory cell array, and (5) is the VCC
Wiring, (6) is GND wiring, (11) is board, (12)
The interlayer film (13) is a metal wiring material, (14) is the first resist, and (15) is the second resist. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
部の金属配線の厚さを、その他の回路部の金属配線の厚
さよりも厚くしたことを特徴とする半導体装置。1. A semiconductor device comprising a single layer of metal wiring, characterized in that the thickness of the metal wiring in a power supply wiring part is thicker than the thickness of the metal wiring in other circuit parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086004A JPH02264432A (en) | 1989-04-04 | 1989-04-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086004A JPH02264432A (en) | 1989-04-04 | 1989-04-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02264432A true JPH02264432A (en) | 1990-10-29 |
Family
ID=13874536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1086004A Pending JPH02264432A (en) | 1989-04-04 | 1989-04-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02264432A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088246A (en) * | 1994-06-21 | 1996-01-12 | Nippon Motorola Ltd | Method for forming metal wiring of semiconductor device |
| US6822334B2 (en) | 2000-05-30 | 2004-11-23 | Renesas Technology Corp. | Semiconductor device having a layered wiring structure with hard mask covering |
| US9653406B2 (en) | 2015-04-16 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive traces in semiconductor devices and methods of forming same |
-
1989
- 1989-04-04 JP JP1086004A patent/JPH02264432A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088246A (en) * | 1994-06-21 | 1996-01-12 | Nippon Motorola Ltd | Method for forming metal wiring of semiconductor device |
| US6822334B2 (en) | 2000-05-30 | 2004-11-23 | Renesas Technology Corp. | Semiconductor device having a layered wiring structure with hard mask covering |
| US9653406B2 (en) | 2015-04-16 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive traces in semiconductor devices and methods of forming same |
| US10937734B2 (en) | 2015-04-16 | 2021-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive traces in semiconductor devices and methods of forming same |
| US11894299B2 (en) | 2015-04-16 | 2024-02-06 | Taiwan Semiconductor Ltd | Conductive traces in semiconductor devices and methods of forming same |
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