JPH03108338A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration and prevent the generation of crack, by forming an outer connection electrode on an element region by using a part of the uppermost layer of a plurality of conducting layers formed on a semiconductor substrate. CONSTITUTION:A semiconductor chip 1 is constituted of circuit elements, metal wiring layers 9, 10, 12, and interlayer insulating layers between them which are all formed on a semiconductor substrate. The layer 9 and circuit elements (gate polysilicon 7 and a diffusion layer 8) are connected by contact boles 11. The layers 9, 10 are connected by a viacontact 13, and the layers 10, 12 are connected by a viacontact 14. An outer connection electrode 6 is formed by using a part of the layer 12 as the uppermost layer. Under the electrode 6, the layer 10 is not positioned, and an insulating layer 15 is formed. Thereby the insulating layer under the electrode 6 is thickened, the generation of crack at the time of bonding can be prevented, the area for an electrode is omitted, the degree of integration is improved, and a chip can be flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and particularly to an improvement in the arrangement structure of external connection electrodes.

(Prior Art) Generally, a semiconductor integrated circuit is formed on a semiconductor chip called an IC chip or an LSI chip, and in order to use it as an electronic component, it is necessary to connect the integrated circuit on the semiconductor chip with the outside. It is necessary to input and output signals between them and to supply power to the integrated circuit. For this reason, the semiconductor chip is mounted within an envelope, and the chip and lead terminals of the envelope are connected with wires.

In this case, an external connection electrode called a bonding pad, which is connected to the wiring of the integrated circuit and is made of a metal wiring layer with a large area, is provided on the chip, and the connection is made by bonding the wire to this pad. I'm going.

FIG. 6 shows the arrangement of the element regions and bonding pads of the integrated circuit in such a semiconductor chip. This arrangement is well known and is the arrangement employed in the majority of semiconductor chips. That is, the semiconductor chip 1 includes a logic circuit block 3 and wiring (not shown) on a semiconductor substrate 2, and an I10 cell (input/output cell) 4 arranged so as to surround these.
The device has an element region 5 consisting of the following, and a bonding pad 6 is further arranged on the outer periphery of the element region 5.

Note that, in the layer below the bonding pad 6, no circuit elements or wiring as in the element region 5 are provided, and only the bonding pad 6 is formed.

FIG. 7 is a sectional view taken along the line xx' in FIG. 6 above. A circuit element composed of a gate polysilicon 7, a diffusion layer 8, etc. is formed on the semiconductor substrate 2, and a first metal wiring layer 9 and a second metal wiring layer 10 are laminated thereon. There is. The gate polysilicon 7 and the first metal wiring layer 9 are connected through a contact hole 11. Further, the first metal wiring layer 9 and the second metal wiring layer 10 are connected by via contacts 13. A bonding pad 6 is provided on the second metal wiring layer 10. As described above, the bonding pad 6 is formed on the outer periphery of the element region 5 (range indicated by arrow a).

No circuit elements or wiring are provided under this pad.

(Problem to be Solved by the Invention) In the conventional semiconductor chip having the above-mentioned configuration, even if the degree of integration of the integrated circuit formed on the chip is increased and the area of the element region is reduced, there are problems due to the reasons described below. Since the area of the outer periphery of the chip occupied only by the bonding pads, which cannot be reduced below a certain level, does not change, the area of the semiconductor chip as a whole does not become much smaller.

Furthermore, even when functions are added to the integrated circuit on a semiconductor chip, efforts are made to maintain the chip size by preventing the size of the semiconductor chip from increasing as much as possible and by increasing the degree of integration in the element area.

However, with the addition of such functions, the number of input/output signals will increase, and the number of bonding pads mentioned above will also inevitably increase, so the size of the semiconductor chip will increase due to the increase in the number of bonding pads. tends to be unavoidable.

Conventionally, therefore, the chip size was maintained by reducing the size of the bonding pad itself. However, the bonding pad cannot be made smaller than a certain level due to limitations caused by positional accuracy during bonding and the diameter of the wire used.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device in which the arrangement structure of external connection electrodes is improved so as to contribute to an improvement in the degree of integration without increasing the chip size.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention provides an integrated circuit element region formed on a semiconductor substrate, and an integrated circuit element region provided on the integrated circuit element region. A semiconductor integrated circuit device comprising a plurality of conductor layers and an external connection electrode formed in a portion of the uppermost layer of the conductor layer corresponding to the integrated circuit element region, having the configuration described below, namely A space between the lowermost layer of the conductor layer and the external connection electrode is filled with an insulating layer.

Further, the insulating layer filled between the bottom layer of the conductor layer and the external connection electrode has a thickness that is at least twice as thick as the thickness between the conductor layers.

Further, in the present invention, a conductive layer is provided at a position below the external connection electrode and in an intermediate layer between the lowermost layer and the uppermost layer of the conductive layer, independently of other conductive layers in the intermediate layer. It has body layers.

(Function) In order to solve the problems of the prior art with the present invention, an external connection electrode is formed on the element region using a part of the uppermost layer of the conductive layer formed on the semiconductor substrate. As a result, the outer periphery of the semiconductor integrated circuit device can be eliminated, so the area of the semiconductor integrated circuit device can be reduced, and furthermore, a semiconductor integrated circuit device with increased functionality can be provided with the same area as the conventional one.

In addition, the electrode for external connection is arranged at the same layer position as the conductive layer in the middle layer between the uppermost layer and the lowermost layer of the above conductive layer at the position below the electrode for external connection, and is arranged independently from other conductive layers. Forming a potential conductive layer. As a result, a structure can be created in which a short circuit between the external connection electrode and the conductive layer under the electrode due to a crack generated by an impact during bonding does not affect the circuit.

Furthermore, because of this, the surface of the external connection electrode becomes higher by the thickness of the conductor layer, so that T A B (Ta
A chip mounting method that can be connected to the outside without using wire bonding, such as an automated bonding method, can be easily adopted.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is for showing the configuration of a first embodiment of the present invention, and FIG. 1A is an enlarged view of the vicinity of a bonding pad formed on an element region 5, and (B
) is a sectional view taken along the line YY' in FIG.

As shown in the figure, a semiconductor chip 1 serving as a semiconductor integrated circuit device includes circuit elements formed on a semiconductor substrate 2, metal wiring layers 9, 10, and 12 laminated in three layers thereon, and interlayer insulation between them. A film is formed. This metal wiring layer consists of a first wiring layer 9, a second wiring layer 1o, and a third wiring layer 12, which is the uppermost layer and forms a bonding pad 6 that becomes an electrode for external connection. The second wiring layer 10 is formed so as not to be located under the bonding pad 6. Further, a contact hole 11 connects the first wiring layer 9 and the circuit elements (gate polysilicon 7, diffusion layer 8).

A via contact 13 is provided between the first and second wiring layers.
The second and third wiring layers are also connected by via contacts 14 .

This is because in the conventional semiconductor chip having the above-mentioned structure, if the insulating film underlying the bonding pad is thin, the insulating film may crack due to the impact when bonding the wire. In such a case, if a metal wiring layer or element is provided under the bonding pad, foreign matter may enter the crack, causing problems such as a short circuit between the pad and the wiring layer. There is a fear that it will be lost.

Therefore, the second pad is placed under the pounding pad 6.
When an insulating layer 15 is formed instead of the wiring layer 10, the thickness of the insulating layer 15 is added to the thickness of the interlayer insulating film. Therefore, this integrated circuit has a structure in which the insulating film under the pad 6 is not easily damaged even by the impact when the wire 16 is bonded to the bonding pad 6.

That is, in general, when bonding, the thicker the interlayer insulating film under the bonding pad is, the less it will be damaged. However, if the interlayer insulating film is formed thickly, the contact hole used to connect the metal wiring layers sandwiching this film becomes deep. Moreover, conventional thin film formation technology has a limit in completely filling contact holes with large aspect ratios, and the depth of contact holes must be adjusted to ensure coverage of the metal wiring layer formed on the insulating layer. subject to restrictions. Therefore, in this embodiment, three metal wiring layers are stacked and two thin interlayer insulating films are formed to ensure sufficient thickness and to prevent the contact hole from becoming deep.

FIG. 2 is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention. In the figure, the bonding pad 6 is located above and below the I10 cell 4 with an interlayer insulating layer (not shown) in between. When viewed from above, this positional relationship is
What was conventionally provided on the outer periphery is overlapped in this embodiment so that a portion thereof coincides. Therefore, the area of the semiconductor chip can be reduced by this overlap.

In this second embodiment, approximately half of the bonding pad 6 overlaps with the I10 cell 4, but the invention is not limited to this, and the entire portion may overlap. In other words, the bonding pad 6, which was conventionally placed on the outer periphery.
The entire structure may be formed on the I10 cell 4 with the insulating layer interposed therebetween.

For this reason, bonding pads are generally provided in the second metal wiring layer, but in this embodiment, a third metal wiring layer 12 is newly formed, and the bonding pads 6 are provided therein.

Therefore, the present invention is possible when a structure is formed by stacking three or more metal wiring layers on a semiconductor substrate, but cannot be implemented when a structure is formed by stacking two or less metal wiring layers.

Further, a third embodiment of the present invention is shown in FIG. Components in this figure that are arranged in the same way as in FIG. 2 are given the same reference numerals and their explanations will be omitted.

In this embodiment, the bonding pads 6 are further inside the semiconductor chip 1 from the arrangement shown in FIG. 2, and all pads are provided above the element region 5. Therefore, the outer periphery provided with the padding pad can be omitted.

Furthermore, especially when a mounting method such as the TAB method in which wires are not bonded is used, the I10 cell 4 can be provided at any position on the element region. For this reason, the above I
The above-mentioned bonding pad 6 connected to the 10 cells 4 is
It is not necessary to arrange it near the periphery on the semiconductor chip 1, and it can similarly be provided at any arbitrary position.

However, the insulating layer used under the bonding pad 6 in the above embodiment has a lower film forming rate (film forming m per unit time) than a metal film, and it takes time to form the insulating layer. Moreover, it is difficult to form a flat surface. Semiconductor chips whose surfaces are not completely flat may be difficult to bond wires to, even if the TAB
If you use a mounting method like this, there is a possibility that a mounting failure will occur.

FIG. 4 shows a fourth embodiment of the present invention in which wire bonding and the TAB method described above can be easily employed. Components in this figure that are arranged in the same way as in FIG. 1(B) are given the same reference numerals and their explanations will be omitted.

That is, in this embodiment, an insulating layer is formed at the second layer wiring layer 10 under the bonding pad 6 in the above-described example, but instead, the insulating layer is floating in potential or is formed on the second wiring layer 10 below the bonding pad 6. Metal layer 1 which is a conductor layer with the same potential
7 is formed.

When this metal layer 17 is formed, even if a crack occurs in the insulating film directly under the pad due to the impact during wire bonding and a short circuit occurs between the bonding pad 6 and the metal layer 17, the Since the layer has the same potential as the bonding pad 6, there is no problem. Moreover, when this metal layer 17 is formed, it takes a shorter time to form than when using the above-mentioned insulating layer, and it is easier to flatten the third wiring layer 12, which is the uppermost layer that forms the bonding pad 6. Even when the above TAB method is used, mounting defects are eliminated.

Further, by using the above-described structure, as a fifth embodiment of the present invention, as shown in FIG. I can do it. Components in this figure that are arranged in the same way as in FIG. 4 are given the same reference numerals and their explanations will be omitted.

In this structure, a diffusion layer 8 is provided in a semiconductor substrate 2, an insulating film 18 is formed on the diffusion layer 8, and a gate polysilicon layer 7 is provided.

In addition, a first
A metal wiring layer 9 is provided. A second metal wiring layer 10 is provided with an interlayer insulating film 19 therebetween, and the wiring layer 1o is formed so as to be connected to the bonding pad 6 to which the wire 16 is bonded via a via contact 14.

That is, there is a case where an insulating layer is provided between the bonding pad 6 and the first metal wiring layer 9, or a conductive layer having the same potential as the bonding pad 6 is formed with an insulating layer interposed therebetween. In this case, an element such as a transistor can be provided under the first wiring layer 9.

Although the present invention has been described in detail above, the present invention is not limited to these embodiments, and it goes without saying that various modifications and applications can be made without departing from the gist of the invention. It is.

[Effects of the Invention] As described above, according to the present invention, the bonding pad, which is an electrode for external connection, is provided on the element area or wiring that forms the integrated circuit of a semiconductor chip. The area of the outer periphery provided for this purpose can be eliminated.

As a result, even if the area of a semiconductor chip is reduced by increasing the degree of integration of the integrated circuit, the area occupied by the bonding pads provided on the outer periphery of the semiconductor chip does not change.
Although the area of the semiconductor chip has not been significantly reduced, the size of the semiconductor chip has been reduced to the area of only the element region.

This is because the area of the semiconductor chip itself has decreased, -
More semiconductor chips can be formed on each semiconductor substrate wafer than in the past, and the production amount of semiconductor chips can be increased even with the same number of wafers.

Further, if the area of the semiconductor chip itself is the same as that of the conventional semiconductor chip, it is possible to expand the element area to the outer periphery, and a semiconductor integrated circuit with further increased functionality can be formed on the chip.

In addition, since the insulating layer between the element region or the metal wiring layer that becomes the conductor layer and the bonding pad is more than twice as thick as the metal wiring layer, cracks may occur even if a shock is applied during bonding. This semiconductor integrated circuit device has a layout structure that prevents the occurrence of.

Furthermore, since a conductor layer is provided as an intermediate layer in the insulating layer under the bonding pad and has the same potential as the bonding pad and is independent of the wiring, the time for forming the insulating layer is shortened, and the entire semiconductor chip is It also becomes easier to flatten the surface.

Since the bonding pads provided on the top layer are formed at the same height, T
This is a semiconductor integrated circuit device with an arrangement structure that allows easy external connections such as AB method.

[Brief explanation of drawings]

FIG. 1(A) is an enlarged view of the vicinity of the bonding pad on the semiconductor chip as the first embodiment of the present invention, and FIG. 1(B)
is a cross-sectional view taken along the line Y-Y' in FIG. 4 and 5 are cross-sectional views of semiconductor chips as fourth and fifth embodiments of the present invention, respectively.
Fig. 6 is a plan view showing the arrangement of integrated circuits and bonding pads on a conventional semiconductor chip, and Fig. 7 is x-x in Fig. 6.
FIG. 1... Semiconductor integrated circuit device, 2... Semiconductor substrate, 4
...I10 cell, 5...Element region, 6...External connection electrode, 9, 10.12...Conductor layer, 15...
Insulating layer, 16... wire, 17... conductor layer. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (5)

[Claims] (1) an integrated circuit element region formed on a semiconductor substrate;
A semiconductor integrated circuit device comprising a plurality of conductor layers provided on the integrated circuit element region, and an external connection electrode formed in a portion of the uppermost layer of the conductor layer corresponding to the integrated circuit element region. . (2) Claim (1) characterized in that the space between the lowermost layer of the conductor layer and the external connection electrode is filled with an insulating layer.
The semiconductor integrated circuit device described above. (3) The insulating layer filled between the bottom layer of the conductor layer and the external connection electrode has a thickness that is at least twice the thickness of the layer between the conductor layers. Claims (
2) The semiconductor integrated circuit device described above. (4) A conductor layer disposed below the external connection electrode and in an intermediate layer between the bottom layer and the top layer of the conductor layer, independently of other conductors in the intermediate layer. The semiconductor integrated circuit device according to claim 1, further comprising: (5) The external connection material is arranged below the external connection electrode and in an intermediate layer between the bottom layer and the top layer of the conductive layer, independently of other conductors in the intermediate layer. The semiconductor integrated circuit device according to claim 1, further comprising a conductive layer having the same potential as the electrode.