JP2016219655A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reinforce a power supply in a semiconductor device.SOLUTION: A semiconductor device comprises: a pad P formed on one principal surface of a substrate 11, and electrically connected with a bump B; first metal wiring M1 electrically connected with the pad P; and second metal wiring M2 at least partially formed on the same metal layer as the bump B. The first metal wiring M1 has a first portion M1a and a second portion M1b. The first portion M1a and the second portion M1b of the first metal wiring M1 are electrically connected with the second metal wiring M2, respectively.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of substrates are three-dimensionally stacked.

  In recent years, a technique for three-dimensionally laminating a plurality of semiconductor chips has attracted attention as one of the techniques for realizing high performance of a semiconductor device. In particular, by connecting between multiple stacked semiconductor chips via through electrodes and bumps that penetrate the substrate of the semiconductor chip, it is possible to connect an extremely large number of signal lines with a short wiring length. A device is obtained. However, since there are various restrictions on the installation locations of the through electrodes and bumps, they are often arranged unevenly on the plane of the semiconductor chip. For example, in the case of a wide IO type DRAM (Dynamic Random Access Memory), a plurality of memory chips are stacked on a logic chip, but through electrodes and bumps are concentrated on the central portion of the memory chip. On the other hand, the chip size of a memory chip is increasing with an increase in capacity. As a result, the circuit block arranged near the end of the chip has a longer distance from the through electrode, and thus the power supply potential tends to fluctuate, resulting in a disadvantage in high speed operation.

JP 2005-167222 A

  Patent Document 1 discloses a technique for providing an additional wiring layer on a semiconductor chip when a power supply pad formed on the semiconductor chip and an external terminal on a package provided around the semiconductor chip are connected with a metal wire. It is disclosed. According to this, although the electric resistance of the power supply line between the semiconductor chip and the external terminal can be lowered, the electric resistance of the power supply line inside the chip cannot be lowered.

  A semiconductor device according to the present invention includes a first substrate, a second substrate stacked on the first substrate and electrically connected to the first substrate via a bump group, and a main surface of the first substrate. A pad formed and electrically connected to the first bump included in the bump group; and a first metal wiring electrically connected to the pad. The first metal wiring has a first portion and a second portion, and at least a part of the first metal wiring and the second portion of the first metal wiring are respectively the first bump. Are electrically connected to the second metal wiring formed in the same metal layer.

  According to the present invention, there is provided a semiconductor device in which a plurality of semiconductor chips are electrically connected to each other via connection terminals such as bumps and stacked, and the electric resistance of the power supply potential feed line in each semiconductor chip is reduced. can do.

1 is a schematic plan view showing a main part of a memory chip 10A according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view along the line aa shown in FIG. 1. It is a top view which shows the whole structure of 10 A of memory chips. It is sectional drawing which shows the semiconductor device 20 by which the memory chip 10A is laminated | stacked on another chip | tip. It is a schematic plan view showing a main part of a memory chip 10B according to a second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view along the line bb shown in FIG. 5. It is a schematic plan view showing a main part of a memory chip 10C according to a third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a main part of a memory chip 10D according to a fourth embodiment of the present invention. It is a schematic plan view showing a main part of a memory chip 10E according to a fifth embodiment of the present invention. FIG. 10 is a schematic cross-sectional view taken along line ee shown in FIG. 9. FIG. 10 is a schematic cross-sectional view showing a main part of a memory chip 10F according to a sixth embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a main part of a memory chip 10G according to a seventh embodiment of the present invention. It is sectional drawing which shows the semiconductor device 30 formed by laminating | stacking three chips | tips. It is a schematic plan view showing the configuration of the memory chip 10I in which the bump group BG is arranged along the side. It is a top view which shows the whole structure by the modification of 10 A of memory chips.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view showing the main part of the memory chip 10A according to the first embodiment of the present invention. 2 is a schematic cross-sectional view along the line aa shown in FIG.

  The plan view shown in FIG. 1 is an enlarged view of a part of the appearance of the memory chip 10A, and includes a bump group BG composed of a plurality of bumps B laid out in a matrix. Each bump B is an external terminal of the memory chip 10A and includes a power supply terminal and a signal terminal. Among these, the power supply terminals include at least a terminal to which the power supply potential VDD is supplied and a terminal to which the ground potential VSS is supplied.

  As shown in FIG. 2, the memory chip 10 </ b> A includes a substrate 11 made of a semiconductor material such as single crystal silicon (Si), an insulating layer 12 that covers one main surface of the substrate 11, and a passivation film that covers the upper surface of the insulating layer 12. 13 and a protective film 14 that further covers the passivation film 13.

  The insulating layer 12 is a multilayer film made of an insulating material such as silicon oxide or silicon nitride, and a multilayer wiring structure including a plurality of metal wiring layers and various circuit elements are embedded therein. In the example shown in FIG. 2, an example in which three metal wiring layers L1, L3, and L4 are embedded is shown, but the present invention is not limited to this. FIG. 2 shows a transistor T and a capacitor C as examples of circuit elements. The transistor T includes a source / drain region SD provided on the substrate 11 and a gate electrode G covering between the two source / drain regions SD. The source / drain region SD is connected to the metal wiring layer L1 through the contact conductor CE. In the example shown in FIG. 2, the metal wiring layer L1 connected to one of the source / drain regions SD is connected to the capacitor C, whereby a transistor T and a capacitor C constitute a DRAM memory cell.

  The passivation film 13 and the protective film 14 are provided to chemically and physically protect the multilayer wiring structure and circuit elements embedded in the insulating layer 12. Although not particularly limited, the passivation film 13 is made of silicon nitride, and the protective film 14 is made of polyimide.

  As shown in FIG. 2, a pad P is provided on the uppermost layer of the multilayer wiring structure, and the pad P is exposed from the opening OP of the passivation film 13. The lower part of the pad P is connected to the metal wiring layers L4 and L3 through the through-hole conductor TH. Corresponding bumps B are provided on the pads P, respectively. The bump B is an external terminal of the memory chip 10A, and is formed by plating, unlike each metal wiring layer constituting the multilayer wiring structure. For this reason, the height (thickness) of the bump B is significantly thicker than the thickness of the pad P, the wiring layer L4, and the like. In addition, aluminum (Al) is mainly used as the conductive material of each metal wiring layer constituting the multilayer wiring structure, whereas the conductive material of the bump B is a material having a lower specific resistance, for example, copper (Cu Etc.) are preferably used.

  Furthermore, in the memory chip 10A according to the present embodiment, a part of the pads P is stretched as it is to form the first metal wiring M1. That is, the pad P and the first metal wiring M1 are located in the same metal wiring layer (the uppermost metal wiring layer). The first metal wiring M1 (VDD) shown in FIG. 2 is obtained by extending the pad P to which the power supply potential VDD is supplied. As shown in FIG. 1, the pad P to which the ground potential VSS is supplied is also extended to form the first metal wiring M1 (VSS).

  A second metal wiring M2 is disposed above the first metal wiring M1 with a passivation film 13 interposed therebetween. The second metal wiring M2 is formed at the same time as the bump B, and is a rewiring located in the outermost layer. However, the solder layer provided on the upper surface of the bump B is omitted.

  The bottom surface of the second metal wiring M2 is in contact with the upper portion of the corresponding first metal wiring M1 through a plurality of openings OP provided in the passivation film 13. Thereby, since the second metal wiring M2 functions as a backing wiring for the first metal wiring M1, the electric resistance of the power supply wiring can be greatly reduced. In other words, the power supply at a position away from the bump B is strengthened, and this makes it possible to suppress fluctuations in the power supply potential. For example, in the first metal wiring M1, when the portion close to the bump B is the first portion M1a and the portion far from the bump B (that is, the portion close to the edge of the chip) is the second portion M1b, Without the metal wiring M2, the electrical resistance between the bump B and the second portion M1b becomes high. In the present embodiment, the electrical resistance between the two is as a result of being backed by the second metal wiring M2. Can be greatly reduced.

  FIG. 3 is a plan view showing the overall configuration of the memory chip 10A.

  As shown in FIG. 3, the memory chip 10A includes four channels CH0 to CH3, and a bump group BG corresponding to each channel is arranged between the channels CH0 and CH2 and between the channels CH1 and CH3. Has been. Although not shown, each channel CH0 to CH3 includes a large number of memory cells (memory cell matrix) arranged in a matrix. With such a layout, the distance from the bump B is longer at the chip edge, particularly near the upper and lower sides shown in FIG.

  However, in the present embodiment, since the first metal wiring M1 is backed by the second metal wiring M2 provided in the same metal layer as the bump B, the power supply on the four sides of the chip is strengthened.

  Also, as shown in FIG. 3, a test pad TP (probe measurement pad) is provided adjacent to the second metal wiring M2 in the vicinity of the four sides of the chip. The test pad TP is connected to the corresponding first metal wiring M1 and second metal wiring M2. As a result, even during a test operation in which the bump B is not used, the same power supply conditions as in the actual use in which the bump B is used can be reproduced.

  In the example shown in FIG. 3, the second metal wiring M2 is disposed so as to cross the channels CH0 to CH3. However, the layout of the second metal wiring M2 is not particularly limited, and for example, FIG. As shown in FIG. 2, the second metal wiring M2 may be extended along the two channels.

  FIG. 4 is a cross-sectional view showing a semiconductor device 20 in which the memory chip 10A is stacked on another chip.

  A semiconductor device 20 shown in FIG. 4 includes a package substrate 21 and has a structure in which a control chip SOC and a memory chip 10A are stacked on the upper surface thereof. The control chip SOC and the memory chip 10A are embedded in a sealing resin 22 that covers the upper surface of the package substrate 21. A large number of ball electrodes 23 that are external terminals are provided on the lower surface of the package substrate 21.

  As shown in FIG. 4, the chip size of the control chip SOC is smaller than the chip size of the memory chip 10A. However, since the bump group BG is disposed at the substantially central portion of the memory chip 10A, the memory chip 10A and the control chip SOC can be electrically connected via the plurality of bumps B. In this case, the vicinity of the end of the memory chip 10A is far from the bump B. However, as described above, since the second metal wiring M2 is provided in the memory chip 10A, the end of the memory chip 10A is provided. Power supply in the vicinity is strengthened.

  FIG. 5 is a schematic plan view showing the main part of the memory chip 10B according to the second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view along the line bb shown in FIG.

  As shown in FIGS. 5 and 6, the memory chip 10B according to the present embodiment is different from the memory chip 10A according to the first embodiment in that the second metal wiring M2 is divided at a plurality of locations in the extending direction. doing. Since other configurations are the same as those of the memory chip 10A according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  In the memory chip 10B according to the present embodiment, since the second metal wiring M2 is divided at a plurality of locations, the underfill flow is not hindered. Thus, after the memory chip 10B is stacked on the control chip SOC, it is possible to reliably fill the underfill in the gap between the memory chip 10B and the control chip SOC.

  FIG. 7 is a schematic plan view showing the main part of the memory chip 10C according to the third embodiment of the present invention.

  As shown in FIG. 7, in the memory chip 10C according to the present embodiment, the second metal wires M2 (VSS) and M2 (VDD) covering both the first metal wires M1 (VSS) and M1 (VDD) are alternately arranged. Is different from the memory chip 10A according to the first embodiment. Since other configurations are the same as those of the memory chip 10A according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  In the memory chip 10C according to the present embodiment, since the second metal wiring M2 covers both the first metal wiring M1 (VSS) and M1 (VDD), the wiring width of the second metal wiring M2 is increased. can do. Further, as in the second embodiment, since the second metal wiring M2 is divided at a plurality of locations, the flow of underfill is not hindered.

  FIG. 8 is a schematic cross-sectional view showing the main part of a memory chip 10D according to the fourth embodiment of the present invention.

  As shown in FIG. 8, the memory chip 10D according to the present embodiment is different from the memory chip 10A according to the first embodiment in that the second metal wiring M2 and the corresponding bump B are integrated. Yes. Since other configurations are the same as those of the memory chip 10A according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. Thus, it is not essential to provide the second metal wiring M2 separately from the bumps B, and both may be integrated.

  FIG. 9 is a schematic plan view showing the main part of the memory chip 10E according to the fifth embodiment of the present invention. FIG. 10 is a schematic cross-sectional view along the line ee shown in FIG.

  As shown in FIGS. 9 and 10, in the memory chip 10E according to the present embodiment, a plurality of elongated openings OP are provided in the passivation film 13 along the first metal wiring M1, and the second metal wiring is formed in the opening OP. The memory chip 10A according to the first embodiment is different in that M2 is embedded. Since other configurations are the same as those of the memory chip 10A according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. According to the memory chip 10E according to the present embodiment, the underfill can be more reliably filled in the gap between the memory chip 10E and the control chip SOC.

  FIG. 11 is a schematic cross-sectional view showing the main part of a memory chip 10F according to the sixth embodiment of the present invention.

  As shown in FIG. 11, the memory chip 10F according to the present embodiment has a memory electrode according to the first embodiment in that a through-hole electrode TSV that overlaps the bump B in plan view and penetrates the substrate 11 in the vertical direction is provided. This is different from the chip 10A. Since other configurations are the same as those of the memory chip 10A according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. Thus, the present invention can also be applied to a semiconductor device having the through silicon via TSV. The through electrode TSV is connected to the corresponding bump B via the wiring layers L2 to L4 and the pad P.

  FIG. 12 is a schematic cross-sectional view showing the main part of a memory chip 10G according to the seventh embodiment of the present invention.

  As shown in FIG. 12, the memory chip 10G according to the present embodiment is different from the memory chip 10F according to the sixth embodiment in that a third metal wiring M3 is provided on the other surface of the substrate 11. . Since other configurations are the same as those of the memory chip 10F according to the sixth embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted. In this way, the third metal wiring M3 electrically connected to the first metal wiring M1 can be provided on the other surface of the substrate 11. In this case, the second metal wiring M2 may be omitted.

  FIG. 13 is a cross-sectional view showing a semiconductor device 30 in which three chips are stacked. Elements that are the same as those of the semiconductor device 20 shown in FIG.

  A semiconductor device 30 shown in FIG. 13 has a configuration in which a memory chip 10G is stacked on a control chip SOC, and another memory chip 10H is stacked on the memory chip 10G. The configuration of the memory chip 10G is as shown in FIG. 12, but the second metal wiring M2 is omitted. The circuit configuration of the memory chip 10G and the memory chip 10H is basically the same.

  FIG. 13 also illustrates some of the through silicon vias TSV and the first metal wiring M1. As is apparent from FIG. 13, the power supply potential or the ground potential is supplied to the far end portions of the memory chips 10G and 10H via the through silicon via TSV and the third metal wiring M3. It is illustrated.

  FIG. 14 is a schematic plan view showing the configuration of the memory chip 10I in which the bump group BG is arranged along the side.

  When the bump group BG is arranged along the side of the chip as in the memory chip 10I shown in FIG. 14, the power supply terminal included in one bump group BG, the power supply terminal included in the other bump group BG, May be connected by the second metal wiring M2. According to this, it is possible to enhance the power supply at the center of the chip.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the case where the second metal wiring M2 is provided in the memory chip has been described as an example. However, the present invention is not limited to this, and the second type of semiconductor chip may be the second. The metal wiring M2 may be provided.

10A to 10I Memory chip 11 Substrate 12 Insulating layer 13 Passivation film 14 Protective film 20, 30 Semiconductor device 21 Package substrate 22 Sealing resin 23 Ball electrode B Bump BG Bump group C Capacitor CE Contact conductor CH0 to CH3 Channel G Gate electrode L1 L4 Metal wiring layer M1 First metal wiring M1a First part M1b Second part OP Opening P Pad SD Source / drain region SOC Control chip T Transistor TH Through-hole conductor TP Test pad TSV Through electrode

Claims (19)

A first substrate;
A second substrate stacked on the first substrate and electrically connected to the first substrate via a bump group;
A pad formed on one main surface of the first substrate and electrically connected to a first bump included in the bump group;
A first metal wiring electrically connected to the pad,
The first metal wiring has a first portion and a second portion,
Each of the first portion and the second portion of the first metal wiring is electrically connected to a second metal wiring at least partially formed on the same metal layer as the first bump. , Semiconductor devices.   The semiconductor device according to claim 1, wherein both the pad and the first metal wiring are formed in a first metal layer.   3. The semiconductor device according to claim 1, wherein a through electrode penetrating the first substrate is formed below the pad.   The semiconductor device according to claim 3, wherein the first bump is formed on the other main surface of the first substrate and is electrically connected to the through electrode.   4. The semiconductor device according to claim 1, wherein the first bump is formed above the pad. 5.   The semiconductor device according to claim 1, wherein the bump group is arranged in a matrix at a substantially central portion of the first substrate in a plan view.   The semiconductor device according to claim 1, wherein the bump group is arranged in a matrix in the vicinity of one of the four sides of the first substrate in a plan view.   The semiconductor device according to claim 1, wherein a thickness of the second metal wiring is thicker than a thickness of the first metal wiring.   The semiconductor device according to claim 1, wherein a specific resistance of a main conductive material of the second metal wiring is smaller than a specific resistance of a main conductive material of the first metal wiring.   The first portion of the first metal wiring is disposed in the vicinity of the pad, and the second portion of the first metal wiring is on the one main surface of the first substrate, and The semiconductor device according to claim 1, wherein the semiconductor device is disposed in the vicinity of any one of the four sides of the substrate.   11. The first portion and the second portion of the first metal wiring are arranged in a region sandwiched between two memory cell matrices arranged on the main surface of the first substrate. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein the first portion and the second portion are in contact with each other and are formed continuously. An insulating film having a groove formed on the first metal wiring and extending in the extending direction of the first metal wiring;
13. The semiconductor device according to claim 1, wherein the second metal wiring includes a metal material whose bottom is in contact with the upper surface of the first metal wiring and embedded in the groove.   The semiconductor device according to claim 1, wherein the second metal wiring is a power supply potential or ground potential dedicated wiring.   The semiconductor device according to claim 1, wherein a probe measurement pad electrically connected to the second metal wiring is provided in the vicinity of the second metal wiring. A third substrate laminated on the first substrate via a second bump group;
The semiconductor device according to claim 1, wherein the second substrate and the third substrate are electrically connected via the first substrate.   The semiconductor device according to claim 1, wherein the first substrate and the second substrate are semiconductor chips having the same circuit configuration. A first substrate;
A second substrate stacked on the first substrate and electrically connected to the first substrate via a bump group;
A pad formed on one main surface of the first substrate and electrically connected to a first bump included in the bump group;
A first metal wiring electrically connected to the pad,
The first metal wiring has a first portion and a second portion,
The semiconductor device, wherein the first portion and the second portion of the first metal wiring are electrically connected to a second metal wiring formed above an insulating layer covering the pad, respectively. The first substrate, the second substrate, and the third substrate have a laminated body laminated in this order,
The first substrate and the second substrate are connected via a first bump group,
The second substrate and the third substrate are connected via a second bump group,
The second substrate has a through electrode group arranged at a planar position of each bump of the second bump group,
The semiconductor device is
A pad formed on one main surface of the second substrate and electrically connected to a first bump included in the first bump group;
A first metal wiring electrically connected to the pad,
The first metal wiring has a first portion and a second portion,
The semiconductor device, wherein the first portion and the second portion of the first metal wiring are electrically connected to a second metal wiring formed above an insulating layer covering the pad, respectively.

Images