JP2778235B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2778235B2 JP2778235B2 JP2250565A JP25056590A JP2778235B2 JP 2778235 B2 JP2778235 B2 JP 2778235B2 JP 2250565 A JP2250565 A JP 2250565A JP 25056590 A JP25056590 A JP 25056590A JP 2778235 B2 JP2778235 B2 JP 2778235B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- floating
- power supply
- view
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の金属配線に関する。Description: TECHNICAL FIELD The present invention relates to a metal wiring of a semiconductor device.
近年半導体集積回路は、高集積度化が進み、金属配線
も２層,3層等の多層化が進んできている。一方、電気的
に基板に接続されていない配線（フローティング配線）
の扱いについては、単層配線の際には、なんら問題がな
かったことから、多層配線になっても制限がなかったの
が実状である。In recent years, the degree of integration of semiconductor integrated circuits has been increased, and the number of metal wirings has also been increased to two or three. On the other hand, wiring not electrically connected to the board (floating wiring)
In fact, there is no problem in the case of single-layer wiring, so there is no limit in the case of multi-layer wiring.
第３図に、従来のフローティング配線の構造例を示
す。FIG. 3 shows a structure example of a conventional floating wiring.
第３図（ａ）は平面図、第３図（ｂ）は断面図であ
る。半導体素子は図示省略してある。信号配線５はボン
ディングワイヤー（図示省略）を通じてパッケージピン
（図示省略）と接続されている。又信号配線５はスルー
ホール６を通して、下層の信号配線７につながってい
る。この下層配線７は、シリコン基板１と接続がされて
いない。即ちフローティング配線となっている。又、信
号配線７の上には、プラズマ窒化膜３があり、更にその
上に電源配線４が存在している。FIG. 3A is a plan view, and FIG. 3B is a sectional view. The semiconductor elements are not shown. The signal wiring 5 is connected to a package pin (not shown) through a bonding wire (not shown). The signal wiring 5 is connected to a lower signal wiring 7 through a through hole 6. The lower wiring 7 is not connected to the silicon substrate 1. That is, it is a floating wiring. Further, the plasma nitride film 3 is provided on the signal wiring 7, and the power supply wiring 4 is further provided thereon.
〔発明が解決しようとする課題〕 この従来のフローティング配線構造においては、静電
気が信号配線５に印加された時、フローティング状態と
なっている為逃げ場がなくなり、プラズマ窒化膜３のウ
ィークスポット８（下層に段差が存在する場所に存在す
る）を通じて電源配線４に放電し、結果的に信号配線５
と電源配線４がショートするという問題点があった。[Problem to be Solved by the Invention] In this conventional floating wiring structure, when static electricity is applied to the signal wiring 5, the floating state is in a floating state, so that there is no escape area and the weak spot 8 (lower layer) of the plasma nitride film 3 is formed. At the place where the step exists), and discharges to the power supply wiring 4, and consequently the signal wiring 5
And the power supply wiring 4 is short-circuited.
本発明の半導体装置は、フローティング配線が電気的
に半導体基板に接続されている配線と重ならないことを
特徴とする構造を有している。The semiconductor device of the present invention has a structure in which a floating wiring does not overlap a wiring electrically connected to a semiconductor substrate.
次に本発明について図面を参照して説明する。第１図
は本発明の一実施例であり、第１図（ａ）は平面図、第
１図（ｂ）は断面図である。この例ではフローティング
配線である信号配線５は、電源配線４と同層にしか存在
しておらず、従って静電気等でフローティング配線と電
源配線がショートすることは原理的にありえない。Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is a sectional view. In this example, the signal wiring 5 which is a floating wiring exists only in the same layer as the power wiring 4, and therefore, in principle, a short circuit between the floating wiring and the power wiring due to static electricity or the like cannot occur.
第２図は、フローティング配線である信号配線５が電
源配線４の下層に存在する場合の実施例である。本例の
場合、下層の信号配線７と上層の電源配線４を重ねない
構造としている為、プラズマ窒化膜３のウィークスポッ
ト８上に電源配線が存在せず、従ってフローティング配
線と電源配線が静電気等でショートすることがない。FIG. 2 shows an embodiment in which the signal wiring 5 which is a floating wiring is present below the power supply wiring 4. In the case of this example, since the signal wiring 7 in the lower layer and the power supply wiring 4 in the upper layer are not overlapped, the power supply wiring does not exist on the weak spot 8 of the plasma nitride film 3, and therefore, the floating wiring and the power supply wiring have static electricity or the like. There is no short circuit.
以上説明したように本発明はフローティング配線が電
気的に半導体基板に接続されている配線と垂直方向に交
わらない構造となっている為、静電気等により下地段差
によって生じる層間絶縁膜のウィークスポットを破壊
し、フローティング配線と電源配線がショートすること
がないという効果を有する。As described above, since the present invention has a structure in which the floating wiring does not intersect the wiring electrically connected to the semiconductor substrate in the vertical direction, the weak spot of the interlayer insulating film caused by the underlying step due to static electricity or the like is destroyed. However, there is an effect that the floating wiring and the power supply wiring do not short-circuit.
第４図には本発明の効果を確認する為、静電破壊耐圧
を測定したデータを示す。これより判る様に、従来構造
では、静電破壊耐圧のバラツキが大きいが、本発明の構
造ではバラツキが少なく、充分な静電破壊耐圧を有す
る。FIG. 4 shows data obtained by measuring the electrostatic breakdown voltage in order to confirm the effect of the present invention. As can be seen, the conventional structure has a large variation in the electrostatic breakdown voltage, but the structure of the present invention has a small variation and has a sufficient electrostatic breakdown voltage.
第１図（ａ），（ｂ）は本発明の一実施例の平面図及び
断面図、第２図（ａ），（ｂ）は他の実施例の平面図及
び断面図、第３図（ａ），（ｂ）は従来の構造における
平面図及び断面図である。第４図はフローティング配線
構造と静電破壊電圧の関係を示す図である。 尚図中の記号は以下の通りである。 １……シリコン基板、３……プラズマ窒化膜、４……電
源配線、５……信号配線、６……スルーホール、７……
信号配線、８……ウィークスポット。FIGS. 1A and 1B are a plan view and a sectional view of one embodiment of the present invention, FIGS. 2A and 2B are a plan view and a sectional view of another embodiment, and FIG. 3A and 3B are a plan view and a sectional view of a conventional structure. FIG. 4 is a diagram showing the relationship between the floating wiring structure and the electrostatic breakdown voltage. The symbols in the figure are as follows. 1 ... silicon substrate, 3 ... plasma nitride film, 4 ... power supply wiring, 5 ... signal wiring, 6 ... through-hole, 7 ...
Signal wiring, 8 ... weak spot.
Claims (1)
体素子を１つあるいは複数備え、電気的に半導体基板に
接続されていない金属配線と、電気的に半導体基板に接
続されている電源配線とが絶縁膜を間に挟んで上下に存
在する半導体装置において、前記金属配線が、電気的に
半導体基板と接続されている前記電源配線と重ならない
ことを特徴とする半導体装置。1. A semiconductor substrate comprising one or more semiconductor elements of one or more types, and a metal wiring not electrically connected to the semiconductor substrate, and a power supply wiring electrically connected to the semiconductor substrate. Wherein the metal wiring does not overlap with the power supply wiring electrically connected to the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2250565A JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2250565A JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04129227A JPH04129227A (en) | 1992-04-30 |
| JP2778235B2 true JP2778235B2 (en) | 1998-07-23 |
Family
ID=17209786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2250565A Expired - Lifetime JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2778235B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69729963T2 (en) * | 1997-08-29 | 2005-08-25 | Mitsubishi Denki K.K. | SEMICONDUCTOR COMPONENT WITH INSULATED GATE AND METHOD FOR THE PRODUCTION THEREOF |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281050A (en) * | 1985-10-04 | 1987-04-14 | Nec Corp | Static protective circuit |
| JPS62166557A (en) * | 1986-01-20 | 1987-07-23 | Nec Corp | Protective device against electrostatic breakdown of semiconductor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58177944U (en) * | 1982-05-21 | 1983-11-28 | 日本電気株式会社 | semiconductor equipment |
-
1990
- 1990-09-20 JP JP2250565A patent/JP2778235B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281050A (en) * | 1985-10-04 | 1987-04-14 | Nec Corp | Static protective circuit |
| JPS62166557A (en) * | 1986-01-20 | 1987-07-23 | Nec Corp | Protective device against electrostatic breakdown of semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04129227A (en) | 1992-04-30 |
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