JPH04129227A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04129227A JPH04129227A JP25056590A JP25056590A JPH04129227A JP H04129227 A JPH04129227 A JP H04129227A JP 25056590 A JP25056590 A JP 25056590A JP 25056590 A JP25056590 A JP 25056590A JP H04129227 A JPH04129227 A JP H04129227A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- floating
- lines
- static electricity
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 abstract description 7
- 230000003068 static effect Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の金属配線に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to metal wiring for semiconductor devices.
近年半導体集積回路は、高集積度化が進み、金属配線も
2層、3層等の多層化が進んできている。一方、電気的
に基板に接続されていない配線(フローティング配線)
の扱いについては、単層配線の際には、なんら問題がな
かったことから、多層配線になっても制限がなかったの
が実状である。In recent years, semiconductor integrated circuits have become highly integrated, and metal wiring has also become multilayered, such as two or three layers. On the other hand, wiring that is not electrically connected to the board (floating wiring)
Since there were no problems with single-layer wiring, there were no restrictions on the handling of multi-layer wiring.
第3図に、従来のフローティング配線の構造例を示す。FIG. 3 shows an example of the structure of a conventional floating wiring.
第3図(a)は平面図、第3図(b)は断面図である。FIG. 3(a) is a plan view, and FIG. 3(b) is a sectional view.
半導体素子は図示省略しである。信号配線5はボンディ
ングワイヤー(図示省略)を通してパッケージビン(図
示省略)と接続されている。又信号配線5はスルーホー
ル6を通して、下層の信号配線7につながっている。こ
の下層配線7は、シリコン基板1と接続がされていない
。即ちフローティング配線となっている。又、信号配線
7の上には、プラズマ窒化膜3があり、更にその上に電
源配線4が存在している。Semiconductor elements are not shown. The signal wiring 5 is connected to a package bin (not shown) through a bonding wire (not shown). Further, the signal wiring 5 is connected to a lower layer signal wiring 7 through a through hole 6. This lower layer wiring 7 is not connected to the silicon substrate 1. In other words, it is a floating wiring. Furthermore, a plasma nitride film 3 is provided on the signal wiring 7, and a power supply wiring 4 is further provided on top of the plasma nitride film 3.
この従来のフローティング配線構造においては、静電気
が信号配線5に印加された時、フローティング状態とな
っている為逃げ場がなくなり、プラズマ窒化膜3のウィ
ークスポット8(下層に段差が存在する場所に存在する
)を通じて電源配線4に放電し、結果的に信号配線5と
電源配線4がショートするという問題点があった。In this conventional floating wiring structure, when static electricity is applied to the signal wiring 5, it is in a floating state, so there is no place for it to escape, and weak spots 8 of the plasma nitride film 3 (exist where there is a step in the lower layer) ) and discharged to the power supply wiring 4, resulting in a short circuit between the signal wiring 5 and the power supply wiring 4.
本発明の半導体装置は、フローティング配線が電気的に
半導体基板に接続されている配線と重ならないことを特
徴とする構造を有している。The semiconductor device of the present invention has a structure characterized in that the floating wiring does not overlap the wiring electrically connected to the semiconductor substrate.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例であり、第1図(a)は平面
図、第1図(b)は断面図である。この例ではフローテ
ィング配線である信号配線5は、電源配線4と同層にし
か存在しておらず、従って静電気等でフローティング配
線と電源配線がショートすることは原理的にありえない
。FIG. 1 shows an embodiment of the present invention, with FIG. 1(a) being a plan view and FIG. 1(b) being a sectional view. In this example, the signal wiring 5, which is a floating wiring, exists only in the same layer as the power supply wiring 4, and therefore, it is theoretically impossible for the floating wiring and the power supply wiring to be short-circuited due to static electricity or the like.
第2図は、フローティング配線である信号配線5が電源
配線4の下層に存在する場合の実施例である。本例の場
合、下層の信号配線7と上層の電源配線4を重ねない構
造としている為、プラズマ窒化膜3のウィークスポット
8上に電源配線が存在せず、従ってフローティング配線
と電源配線が静電気等でショートすることがない。FIG. 2 shows an embodiment in which the signal wiring 5, which is a floating wiring, is present in the lower layer of the power supply wiring 4. In FIG. In this example, since the structure is such that the lower layer signal wiring 7 and the upper layer power supply wiring 4 do not overlap, there is no power supply wiring above the weak spot 8 of the plasma nitride film 3, and therefore the floating wiring and the power supply wiring are exposed to static electricity. There will be no short circuit.
以上説明したように本発明はフローティング配線が電気
的に半導体基板に接続されている配線と垂直方向に交わ
らない構造となっている為、静電気等により下地段差に
よって生じる眉間絶縁膜のウィークスポットを破壊し、
フローティング配線と電源配線がショートすることがな
いという効果を有する。As explained above, since the present invention has a structure in which the floating wiring does not intersect with the wiring electrically connected to the semiconductor substrate in the vertical direction, the weak spots of the insulating film between the eyebrows caused by the step difference in the base due to static electricity etc. are destroyed. death,
This has the effect of preventing short-circuits between the floating wiring and the power supply wiring.
第4図には本発明の効果を確認する為、静電破壊耐圧を
測定したデータを示す。これより判る様に、従来構造で
は、静電破壊耐圧のバラツキが大きいが、本発明の構造
ではバラツキが少なく、充分な静電破壊耐圧を有する。FIG. 4 shows data obtained by measuring electrostatic breakdown voltage in order to confirm the effects of the present invention. As can be seen from this, the conventional structure has large variations in electrostatic breakdown voltage, but the structure of the present invention has little variation and has sufficient electrostatic breakdown voltage.
第1図(a)、(b)は本発明の一実施例の平面図及び
断面図、第2図(a)、(b)は他の実施例の平面図及
び断面図、第3図(a)、(b)は従来の構造における
平面図及び断面図である。
第4図はフローティング配線構造と静電破壊電圧の関係
を示す図である。
尚図中の記号は以下の通りである。
1・・・シリコン基板、3・・・プラズマ窒化膜、4・
・・電源配線、5・・・信号配線、6・・・スルーホー
ル、7・・・信号配線、8・・・ウィークスポット。FIGS. 1(a) and (b) are a plan view and a sectional view of one embodiment of the present invention, FIGS. 2(a) and (b) are a plan view and a sectional view of another embodiment, and FIG. a) and (b) are a plan view and a sectional view of a conventional structure. FIG. 4 is a diagram showing the relationship between the floating wiring structure and electrostatic breakdown voltage. The symbols in the figure are as follows. 1... Silicon substrate, 3... Plasma nitride film, 4.
...Power wiring, 5...Signal wiring, 6...Through hole, 7...Signal wiring, 8...Weak spot.
Claims (1)
つあるいは複数備え、電気的に半導体基板に接続されて
いない金属配線が存在する半導体装置において、前記金
属配線が電気的に半導体基板と接続されている配線と重
ならないことを特徴とする半導体装置。One type or multiple types of semiconductor elements are placed on a semiconductor substrate.
1. A semiconductor device including one or more metal wirings that are not electrically connected to a semiconductor substrate, wherein the metal wirings do not overlap with wirings that are electrically connected to the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2250565A JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2250565A JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04129227A true JPH04129227A (en) | 1992-04-30 |
JP2778235B2 JP2778235B2 (en) | 1998-07-23 |
Family
ID=17209786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2250565A Expired - Lifetime JP2778235B2 (en) | 1990-09-20 | 1990-09-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2778235B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999012214A1 (en) * | 1997-08-29 | 1999-03-11 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method for manufacturing the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58177944U (en) * | 1982-05-21 | 1983-11-28 | 日本電気株式会社 | semiconductor equipment |
JPS6281050A (en) * | 1985-10-04 | 1987-04-14 | Nec Corp | Static protective circuit |
JPS62166557A (en) * | 1986-01-20 | 1987-07-23 | Nec Corp | Protective device against electrostatic breakdown of semiconductor |
-
1990
- 1990-09-20 JP JP2250565A patent/JP2778235B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58177944U (en) * | 1982-05-21 | 1983-11-28 | 日本電気株式会社 | semiconductor equipment |
JPS6281050A (en) * | 1985-10-04 | 1987-04-14 | Nec Corp | Static protective circuit |
JPS62166557A (en) * | 1986-01-20 | 1987-07-23 | Nec Corp | Protective device against electrostatic breakdown of semiconductor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999012214A1 (en) * | 1997-08-29 | 1999-03-11 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method for manufacturing the same |
US6285058B1 (en) | 1997-08-29 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2778235B2 (en) | 1998-07-23 |
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