JP3038904B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3038904B2 JP3038904B2 JP32805290A JP32805290A JP3038904B2 JP 3038904 B2 JP3038904 B2 JP 3038904B2 JP 32805290 A JP32805290 A JP 32805290A JP 32805290 A JP32805290 A JP 32805290A JP 3038904 B2 JP3038904 B2 JP 3038904B2
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- wiring layer
- integrated circuit
- opening
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体集積回路における、スクライブ領域上
のTEG（Test Element Group:特性評価素子）パターン
に関する。The present invention relates to a test element group (TEG) pattern on a scribe area in a semiconductor integrated circuit.
［従来の技術］ 従来の半導体集積回路においては、TEGのパッド部の
複数の金属配線層間を接続するために設けられた層間絶
縁層の開口部は、ほぼパッド開口部と同じ大きさであ
り、そのため金属配線層のスリット開口部と重ってい
た。[Prior Art] In a conventional semiconductor integrated circuit, an opening of an interlayer insulating layer provided for connecting a plurality of metal wiring layers of a pad section of a TEG is almost the same size as a pad opening, Therefore, it overlapped the slit opening of the metal wiring layer.
第１図及び第２図は従来例である。第１図は平面図で
あり、第２図は第１図のAA線において切断した場合の断
面図である。101は第一層目の金属配線層であり、102は
第二層目の金属配線層である。103は最終保護膜の開口
部エッジであり、104は第一層目の金属配線層（101）と
第二層目の金属配線層（102）の層間絶縁層である。105
は金属配線層に設けられたスリット開口部である。層間
絶縁層の開口部（104）が、最終保護膜の開口部（103）
とほぼ同じ大きさで開いており、その結果、金属配線層
のスリット部は層間絶縁層の開口部と重なっている。1 and 2 show a conventional example. FIG. 1 is a plan view, and FIG. 2 is a sectional view taken along line AA in FIG. Reference numeral 101 denotes a first metal wiring layer, and reference numeral 102 denotes a second metal wiring layer. Reference numeral 103 denotes an opening edge of the final protective film, and reference numeral 104 denotes an interlayer insulating layer between the first metal wiring layer (101) and the second metal wiring layer (102). 105
Denotes a slit opening provided in the metal wiring layer. The opening (104) of the interlayer insulating layer is the opening (103) of the final protective film.
As a result, the slit portion of the metal wiring layer overlaps with the opening of the interlayer insulating layer.
［発明が解決しようとする課題］ 前述の従来技術では、金属配線層間の層間絶縁層の開
口部がパッド開口部とほぼ同じ大きさで開いているた
め、複数の金属配線層のスリット開口部が重なった場
合、基板表面近くまで達する深い穴となり、パッド穴開
口時の基板とのショートあるいは、バンプ形成時の残留
空気の膨張によるレジスト破壊に起因するバンプ部の異
状形成等の問題点を有する。そこで本発明はこのような
問題点を解決するもので、その目的とするところは、チ
ップサイズ及びデータ作成工数に影響を及ぼさず、スク
ライブ上に配置されるTEGの安定した形成を可能にする
パターン形状を提供するところにある。[Problems to be Solved by the Invention] In the above-mentioned conventional technology, since the openings of the interlayer insulating layer between the metal wiring layers are almost the same size as the pad openings, the slit openings of a plurality of metal wiring layers are formed. When they are overlapped, the hole becomes a deep hole reaching up to near the substrate surface, and there are problems such as a short circuit with the substrate at the time of opening the pad hole or abnormal formation of a bump portion due to resist destruction due to expansion of residual air at the time of bump formation. Therefore, the present invention solves such a problem, and an object of the present invention is to provide a pattern capable of stably forming a TEG arranged on a scribe without affecting the chip size and the number of data creation steps. To provide shape.
［課題を解決するための手段］ 本発明の集積回路は、スクライブ領域上に配置された
TEGのパッド部の金属配線層のスリット開口部と前記金
属配線層の上または下に位置する他の金属配線層を接続
するために設けられた層間絶縁層の開口部が重なってい
ないことを特徴とする。[Means for Solving the Problems] The integrated circuit of the present invention is arranged on a scribe area.
The slit opening of the metal wiring layer of the pad portion of the TEG and the opening of the interlayer insulating layer provided for connecting another metal wiring layer located above or below the metal wiring layer do not overlap. And
［作用］ 本発明の上記の構成によれば、パッド部の複数の金属
配線層のスリット開口部が重なった場合でも、層間絶縁
層の開口部が上記金属配線層のスリットと重ならないた
め、上層部から基板表面近くまで達する深い穴は生じ
ず、パッド穴開口時の基板とのショートあるいは、バン
プ形成時の残留空気の膨張によるレジスト破壊に起因す
るバンプ部の異状形成等の発生を抑える事が可能とな
る。[Operation] According to the above configuration of the present invention, even when the slit openings of the plurality of metal wiring layers of the pad portion overlap, the openings of the interlayer insulating layer do not overlap with the slits of the metal wiring layer. There is no deep hole reaching from the part to the vicinity of the substrate surface, and it is possible to suppress the occurrence of short-circuit with the substrate when opening the pad hole or the abnormal formation of the bump part due to the resist breakdown due to the expansion of the residual air when forming the bump. It becomes possible.
［実施例］ 以下、本発明について、実施例に基づいて説明する。[Examples] Hereinafter, the present invention will be described based on examples.
第３図及び第４図は本発明の実施例である。第３図は
平面図であり、第４図は第３図のAA線において切断した
場合の断面図である。101は第一層目の金属配線層であ
り、102は第二層目の金属配線層である。103は最終保護
膜の開口部エッジであり、104は第一層目の金属配線層
（101）と第二層目の金属配線層（102）の層間絶縁層で
ある。105は金属配線層に設けられたスリット開口部で
ある。層間絶縁層の開口部（104）は、金属配線層のス
リット開口部（105）とは完全にずれている。3 and 4 show an embodiment of the present invention. FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line AA in FIG. Reference numeral 101 denotes a first metal wiring layer, and reference numeral 102 denotes a second metal wiring layer. Reference numeral 103 denotes an opening edge of the final protective film, and reference numeral 104 denotes an interlayer insulating layer between the first metal wiring layer (101) and the second metal wiring layer (102). 105 is a slit opening provided in the metal wiring layer. The opening (104) of the interlayer insulating layer is completely displaced from the slit opening (105) of the metal wiring layer.
［発明の効果］ 以上述べたように発明によれば、パッド部に設けられ
た複数の金属配線層のスリット開口部と上記金属配線層
間の層間絶縁層の開口部が重ならないため、上層部から
基板表面近くまで達する深い穴は生じず、パッド穴開口
時の基板とのショートあるいは、バンプ形成時の残留空
気の膨張によるレジスト破壊に起因するバンプ部の異状
形成等の発生を抑える事が可能となる。[Effects of the Invention] As described above, according to the invention, since the slit openings of the plurality of metal wiring layers provided in the pad portion do not overlap with the openings of the interlayer insulating layer between the metal wiring layers, the upper layer portion There is no deep hole reaching near the substrate surface, and it is possible to suppress the occurrence of short-circuit with the substrate at the time of opening the pad hole or the formation of abnormal bumps due to resist breakdown due to expansion of residual air at the time of bump formation. Become.
第１図及び第２図は従来の半導体集積回路のパッド部の
形状例を示す図。 第３図及び第４図は、本発明による半導体集積回路のパ
ッド部の形状例を示す図。 101……第一層目の金属配線層 102……第二層目の金属配線層 103……最終保護膜の開口部 104……第一層目の金属配線層（101）と第二層目の金属
配線層（102）の層間絶縁層 105……金属配線層に設けられたスリット開口部1 and 2 are views showing examples of the shape of a pad portion of a conventional semiconductor integrated circuit. FIG. 3 and FIG. 4 are diagrams showing examples of the shape of a pad portion of a semiconductor integrated circuit according to the present invention. 101 first metal wiring layer 102 second metal wiring layer 103 opening of final protective film 104 first metal wiring layer (101) and second metal wiring layer Interlayer insulating layer 105 of the metal wiring layer (102) ... Slit opening provided in the metal wiring layer
Claims (1)
ために設けられたスクライブ領域を有し、前記スクライ
ブ領域上に配置されているTEGが、外部と信号を授受す
るためのパッド部の金属配線層にスリット開口部を有
し、かつ、前記パッド部の金属配線層が複数の層で構成
されている半導体集積回路において、前記スクライブ領
域上に配置されたTEGのパッド部の金属配線層のスリッ
ト開口部と前記金属配線層の上または下に位置する他の
金属配線層を接続するために設けられた層間絶縁層の開
口部が重なっていないことを特徴とする半導体集積回
路。1. A scribe area provided for separating a semiconductor integrated circuit into respective chips, wherein a TEG disposed on the scribe area is a metal of a pad part for transmitting and receiving signals to and from the outside. In a semiconductor integrated circuit having a slit opening in a wiring layer, and the metal wiring layer of the pad portion is composed of a plurality of layers, the metal wiring layer of the pad portion of the TEG disposed on the scribe region is A semiconductor integrated circuit, wherein an opening of an interlayer insulating layer provided for connecting a slit opening to another metal wiring layer located above or below the metal wiring layer does not overlap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32805290A JP3038904B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32805290A JP3038904B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04196461A JPH04196461A (en) | 1992-07-16 |
| JP3038904B2 true JP3038904B2 (en) | 2000-05-08 |
Family
ID=18205977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32805290A Expired - Fee Related JP3038904B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3038904B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI247903B (en) * | 2004-10-22 | 2006-01-21 | Advanced Semiconductor Eng | Electrical test device having isolation slot |
| JP4653799B2 (en) * | 2007-12-03 | 2011-03-16 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
-
1990
- 1990-11-28 JP JP32805290A patent/JP3038904B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04196461A (en) | 1992-07-16 |
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