JPH04196461A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress the abnormal formation of a bump by preventing a plurality of the slit openings of wiring layers provided on a pad from being overlapped with the opening of a layer-to-layer insulating layer between the metal wiring layers. CONSTITUTION:The opening 104 of a layer-to-layer insulating layer 103 is completely deviated from the slit opening 105 of a metal wiring layer. Therefore, even when a plurality of the slit openings 105 of metal wiring layers 101 and 102 of a pad are overlapped, since the opening 104 of the layer-to-layer insulating layer 103 does not overlap with the slits of the metal wiring layers 101 and 102, a deep hole which almost reaches the substrate surface from a top layer is not generated. Thus, the abnormal formation of a bump caused by the short-circuit with the substrate when opening a pad hole or by resist breakage caused by the expansion of the remaining air when the bump is formed is suppressed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a TEG (Test Element Group) on a scribe area in a semiconductor integrated circuit.
(characteristic evaluation element) pattern.

[Prior Art] In a conventional semiconductor integrated circuit, an opening in an interlayer insulating layer provided for connecting a plurality of metal wiring layers in a pad portion of a TEG is the same size as a pad opening. , and therefore overlapped with the slit opening of the metal wiring layer.

1 and 2 are conventional examples. FIG. 1 is a plan view, and FIG. 2 is a sectional view taken along line AA in FIG. 1. 101 is the first metal wiring layer;
02 is a second metal wiring layer. 103 is the opening edge of the final protective film, and 104 is an interlayer insulating layer between the first metal wiring layer (101) and the second metal wiring layer (102). 105 is a slit opening provided in the metal wiring layer. The opening (104) in the interlayer insulating layer is approximately the same size as the opening (103) in the final protective film, and as a result, the slit in the metal wiring layer overlaps the opening in the interlayer insulating layer. .

[YA1fll to be Solved by the Invention In the above-mentioned prior art, the opening in the interlayer insulating layer between the metal wiring layers is approximately the same size as the pad opening, so the slit openings in the multiple metal wiring layers overlap. In this case, the hole becomes deep reaching close to the substrate surface, resulting in problems such as a short circuit with the substrate when the pad hole is opened, or abnormal formation of the bump portion due to resist destruction due to expansion of residual air during bump formation. Therefore, the present invention is intended to solve these problems, and its purpose is to create a pattern that does not affect the chip size or data creation man-hours and enables stable formation of TEG placed on the scribe. It is in providing the shape.

[Means for Solving the Problems] The integrated circuit of the present invention has T
The slit opening in the metal wiring layer of the pad portion of the EG does not overlap with the opening in the interlayer insulating layer provided for connecting another metal wiring layer located above or below the metal wiring layer. shall be.

[Function] According to the above structure of the present invention, even if the slit openings of the plurality of metal wiring layers of the pad portion overlap, the openings of the interlayer insulating layer do not overlap with the slits of the metal wiring layer, so that the upper layer There are no deep holes that reach close to the board surface.
It is possible to suppress the formation of irregularities in the bump portion due to short circuits with the substrate when opening pad holes or resist destruction due to expansion of residual air during bump formation.

[Example] Hereinafter, the present invention will be explained based on examples.

3 and 4 are examples of the present invention. FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line AA in FIG. 3. 101 is a first metal wiring layer, and 102 is a second metal wiring layer. 103 is the opening edge of the final protective film, and 104 is the first metal wiring layer (101) and the second metal wiring layer (102).
) is an interlayer insulating layer. 105 is a slit opening provided in the metal wiring layer. Opening of interlayer insulating layer (104
) is completely shifted from the slit opening (105) in the metal wiring layer.

[Effects of the Invention] As described above, according to the invention, since the slit openings of the plurality of metal wiring layers provided in the pad portion and the openings of the interlayer insulating layer between the metal wiring layers do not overlap, Deep holes that reach close to the substrate surface do not occur, making it possible to suppress the formation of irregularities in the bump area due to short circuits with the substrate when opening pad holes, or resist destruction due to expansion of residual air during bump formation. Become.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams showing examples of the shape of a pad portion of a conventional semiconductor integrated circuit. 3 and 4 are diagrams showing examples of the shape of a pad portion of a semiconductor integrated circuit according to the present invention. 101...First layer metal wiring layer 102...
...Second metal wiring layer 103...Opening part 104 of final protective film...First metal wiring layer (101) and second metal wiring layer Interlayer insulating layer 105 of layer (102)... slit opening provided in the metal wiring layer Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (and 1 other person) Figure 1 105 1o4 Figure 3

Claims (1)

[Claims] It has a scribe area provided to separate the semiconductor integrated circuit into each chip, and the TEG placed on the scribe area has a slit opening in the metal wiring layer of the pad part for transmitting and receiving signals with the outside. has a section, and
In a semiconductor integrated circuit in which the metal wiring layer of the pad portion is composed of a plurality of layers, the slit opening of the metal wiring layer of the pad portion of the TEG disposed on the scribe region and above or below the metal wiring layer. A semiconductor integrated circuit characterized in that openings in an interlayer insulating layer provided for connecting other metal wiring layers located in the semiconductor integrated circuit do not overlap.