JPH05183007A - Pad structure for semiconductor substrate - Google Patents
Pad structure for semiconductor substrateInfo
- Publication number
- JPH05183007A JPH05183007A JP7827992A JP7827992A JPH05183007A JP H05183007 A JPH05183007 A JP H05183007A JP 7827992 A JP7827992 A JP 7827992A JP 7827992 A JP7827992 A JP 7827992A JP H05183007 A JPH05183007 A JP H05183007A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- insulating film
- wiring metal
- layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体基板等のパッド構
造に関し、特に、絶縁膜上に配線層を多層化してなる半
導体基板，プリント基板等のパッド構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad structure for a semiconductor substrate or the like, and more particularly to a pad structure for a semiconductor substrate, a printed circuit board or the like having a wiring layer formed on an insulating film.
【０００２】[0002]
【従来の技術】従来、半導体基板においては、図３に示
されているように、無機絶縁膜１１上に形成された有機
絶縁膜１０をエッチングし、そのエッチング箇所にメッ
キ処理等によりパッド１２を形成している。このよう
に、比較的機械強度の高い無機絶縁膜１１上にパッド１
２を直接形成することにより、パッド１２自体の機械的
強度が向上し、当該パッド１２のボンディング時の圧力
による剥れ、及びリード接続後の剥がれを防止できる。
パッド１２上には、外部リード（図示せず）が加圧方式
又は半田付けによってボンディングされる。半田付けに
よる場合には、パッド１２上に低融点半田を配置し、マ
イクロピンを立ててリードを形成する（特開昭６３−２
７９７８９号参照）。この場合には、ボンディング時の
圧力がなくなるので、ボンディング時のパッド１２の剥
がれを確実に防ぐことができる。2. Description of the Related Art Conventionally, in a semiconductor substrate, as shown in FIG. 3, an organic insulating film 10 formed on an inorganic insulating film 11 is etched, and a pad 12 is formed on the etched portion by plating or the like. Is forming. Thus, the pad 1 is formed on the inorganic insulating film 11 having a relatively high mechanical strength.
By forming 2 directly, the mechanical strength of the pad 12 itself is improved, and it is possible to prevent the pad 12 from peeling due to pressure during bonding and peeling after lead connection.
External leads (not shown) are bonded to the pads 12 by a pressure method or soldering. In the case of soldering, a low-melting point solder is arranged on the pad 12 and the micropins are erected to form leads (JP-A-63-2).
79789). In this case, since the pressure at the time of bonding is eliminated, the peeling of the pad 12 at the time of bonding can be reliably prevented.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ような従来の半導体装置においては、有機絶縁膜１０を
多数積層する場合には、パッド１２へのリードの接続を
良好に行うために、パッド１２を有機絶縁膜よりも厚く
しなければならないが、パッド１２がメッキ処理等によ
って形成されるため、厚みの大きなパッドを形成するこ
とが非常に困難になり、その結果、パッドが有機絶縁膜
より薄くなるとパッドへのリードの接続が困難になる。However, in the conventional semiconductor device as described above, when a large number of organic insulating films 10 are stacked, in order to connect the leads to the pads 12 well, the pads 12 are well formed. However, since the pad 12 is formed by plating or the like, it is very difficult to form a pad having a large thickness, and as a result, the pad is thinner than the organic insulating film. Then, it becomes difficult to connect the lead to the pad.
【０００４】[0004]
【発明の目的】本発明の目的は、パッドへのリードの接
続を容易にするために機械的強度の弱い有機絶縁膜上に
パッドを形成したとしても、パッドの機械的強度を向上
させることができる半導体基板等のパッド構造を提供す
ることにある。An object of the present invention is to improve the mechanical strength of a pad even if the pad is formed on an organic insulating film having a weak mechanical strength in order to facilitate the connection of the lead to the pad. It is to provide a pad structure such as a semiconductor substrate that can be manufactured.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するために、無機絶縁膜上の配線金属層と、無機絶縁膜
上に形成された多層有機絶縁膜上のリード接続用のパッ
ドとを電気的に接続する半導体基板等のパッド構造にお
いて、多層有機絶縁膜の各層上にパッド及び無機絶縁膜
上の配線金属に位置的に対応するように設けられた各層
配線金属を有し、パッド，各層配線金属及び無機絶縁膜
上の配線金属とを各層有機絶縁膜に形成されたスルーホ
ールを介して電気的に接続している。In order to achieve the above object, the present invention provides a wiring metal layer on an inorganic insulating film and a pad for lead connection on a multi-layer organic insulating film formed on the inorganic insulating film. In a pad structure such as a semiconductor substrate for electrically connecting to each other, a pad is provided on each layer of the multilayer organic insulating film and each layer wiring metal is provided so as to correspond in position to the wiring metal on the inorganic insulating film. The wiring metal of each layer and the wiring metal on the inorganic insulating film are electrically connected to each other through a through hole formed in the organic insulating film of each layer.
【０００６】[0006]
【作用】半導体基板上に窒化膜等の無機絶縁膜が形成さ
れ、順次その上に拡散等によってソース，ドレイン，ゲ
ート等の素子領域が層状に形成される。各素子領域は必
要に応じて各層の配線金属によって接続され、各層の配
線金属は各層の有機絶縁膜によって絶縁される。同時
に、各層のそれぞれの配線金属は、有機絶縁膜上の複数
のパッドの対応する１つのパッドに電気的に接続され
る。このとき、無機絶縁膜上にパッド座としての配線金
属を設けるとともに、各有機絶縁膜上に配線金属を設
け、これらの配線金属と有機絶縁膜上のパッドをスルー
ホールで接続する。ボンディング作業等において、パッ
ドに圧力がかかっても、その圧力は機械的強度の大きい
無機絶縁膜上の最下のパッド座によって受けられるの
で、機械的強度の弱い有機絶縁膜には負担がかからな
い。An inorganic insulating film such as a nitride film is formed on a semiconductor substrate, and element regions such as a source, a drain and a gate are sequentially formed thereon in layers by diffusion or the like. Each element region is connected by the wiring metal of each layer as needed, and the wiring metal of each layer is insulated by the organic insulating film of each layer. At the same time, each wiring metal of each layer is electrically connected to one corresponding pad of the plurality of pads on the organic insulating film. At this time, a wiring metal as a pad seat is provided on the inorganic insulating film, a wiring metal is provided on each organic insulating film, and these wiring metals and pads on the organic insulating film are connected by through holes. Even if pressure is applied to the pad in the bonding work or the like, the pressure is received by the lowermost pad seat on the inorganic insulating film having high mechanical strength, so that the organic insulating film having low mechanical strength is not burdened.
【０００７】[0007]
【実施例】以下、本発明の一実施例を添付図面を参照し
つつ詳細に説明する。図１には、本発明の第１の実施例
に係る半導体基板の構造が示されている。この半導体基
板は、無機絶縁膜としての窒化膜２０と、窒化膜２０の
上に積層されたパッド座２２，２４ａ〜２４ｄ及びパッ
ド２６と、各層の配線金属を絶縁する有機絶縁膜として
のシリコン含有ポリイミド（ＰＳＩ）層２８とを含んで
いる。ＰＳＩ層２８は厚さ１μｍに成形され、パッド形
成部分に幅１μｍのスルーホール３０ａ，３０ｂ，３０
ｃが形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows the structure of a semiconductor substrate according to the first embodiment of the present invention. This semiconductor substrate includes a nitride film 20 as an inorganic insulating film, pad seats 22, 24a to 24d and a pad 26 stacked on the nitride film 20, and a silicon-containing film as an organic insulating film for insulating the wiring metal of each layer. And a polyimide (PSI) layer 28. The PSI layer 28 is formed to have a thickness of 1 μm, and the through holes 30a, 30b, 30 having a width of 1 μm are formed in the pad formation portion.
c is formed.
【０００８】パッド座２２，２４ａ〜２４ｄとパッド２
６とは同一サイズであり、パッド座２２，２４ａ〜２４
ｄは厚さ０．５μｍに形成されている。そして、最下部
のパッド座２２は平坦に、その他のパッド座２４ａ〜２
４ｄはスルーホール３０ａ〜３０ｃを充填するように突
起部分が形成されている。このようなパッド座２２，２
４ａ〜２４ｄとパッド２６は金メッキで形成され、金メ
ッキの下面にはＰＳＩ層２８との密着性を向上させるた
めにチタン・タングステン（ＴｉＷ）３２が厚さ５００
Åで形成されている。また、パッド座２４ｂは内部機能
回路（図示せず）と引出し配線３４によって接続されて
いる。以上のような構造により、パッド２６がスルーホ
ール３０ａ〜３０ｃ及び各配線層の配線金属及び窒化膜
２０上の金属配線（図示せず）と電気的に接続される。Pad seats 22, 24a to 24d and pad 2
6 has the same size and has pad seats 22, 24a to 24
d has a thickness of 0.5 μm. The lowermost pad seat 22 is flat, and the other pad seats 24a to 24a-2
4d is formed with a protrusion so as to fill the through holes 30a to 30c. Such pad seats 22, 2
4a to 24d and the pad 26 are formed by gold plating, and titanium / tungsten (TiW) 32 having a thickness of 500 is formed on the lower surface of the gold plating to improve adhesion with the PSI layer 28.
It is formed by Å. Moreover, the pad seat 24b is connected to an internal functional circuit (not shown) by a lead wiring 34. With the structure described above, the pad 26 is electrically connected to the through holes 30a to 30c, the wiring metal of each wiring layer, and the metal wiring (not shown) on the nitride film 20.
【０００９】図２には、本発明の第２の実施例に係る半
導体基板のパッド構造が示されている。なお、以下の説
明において上記第１の実施例と共通する部分についての
詳細は省略する。この半導体基板は、窒化膜２０と、窒
化膜２０の上に積層されたパッド座４０，４２ａ〜４２
ｄ及びパッド４６と、各パッド座４０，４２ａ〜４２
ｄ，４６間に配置されたシリコン含有ポリイミド（ＰＳ
Ｉ）層２８とを含んでいる。FIG. 2 shows a pad structure of a semiconductor substrate according to the second embodiment of the present invention. In the following description, the details of the parts common to the first embodiment will be omitted. This semiconductor substrate includes a nitride film 20 and pad seats 40, 42 a to 42 stacked on the nitride film 20.
d and the pad 46, and the pad seats 40, 42a to 42
Silicon-containing polyimide (PS) placed between d and 46
I) layer 28.
【００１０】パッド４４の四隅及び中央部分に対応する
箇所にはスルーホール４６ａ〜４６ｅが形成され、各ス
ルーホールに対応する位置にパッド座４０，４２ａ〜４
２ｄが分割して配置されている。５か所の各パッド座間
には、配線５０ａ，５０ｂが通過し、半導体装置の配線
領域が有効に活用される。Through holes 46a to 46e are formed at positions corresponding to the four corners and the central portion of the pad 44, and the pad seats 40, 42a to 4a are formed at the positions corresponding to the through holes.
2d is divided and arranged. Wirings 50a and 50b pass between the respective five pad seats, and the wiring region of the semiconductor device is effectively utilized.
【００１１】なお、上記実施例においては、半導体装置
に使用される半導体基板について説明したが、本発明は
プリント配線板等にも適用可能である。Although the semiconductor substrate used in the semiconductor device has been described in the above embodiments, the present invention is also applicable to a printed wiring board and the like.
【００１２】[0012]
【発明の効果】以上説明したように本発明に係る積層基
板は、無機絶縁膜上の配線金属層と、無機絶縁膜上に形
成された多層有機絶縁膜上のリード接続用のパッドとを
電気的に接続する半導体基板等のパッド構造において、
多層有機絶縁膜の各層上にパッド及び無機絶縁膜上の配
線金属に位置的に対応するように設けられた各層配線金
属を有し、パッド，各層配線金属及び無機絶縁膜上の配
線金属を各層有機絶縁膜に形成されたスルーホールを介
して電気的に接続しているため、パッドへのリードの接
続を容易にするために機械的強度の弱い有機絶縁膜上に
パッドを形成したとしても、パッドの機械的強度を向上
させることができるという効果がある。As described above, in the laminated substrate according to the present invention, the wiring metal layer on the inorganic insulating film and the pad for lead connection on the multilayer organic insulating film formed on the inorganic insulating film are electrically connected. In a pad structure such as a semiconductor substrate that is electrically connected,
Each layer has a wiring metal provided on each layer of the multi-layered organic insulating film so as to correspond to the wiring metal on the pad and the inorganic insulating film, and each pad has a wiring metal on each layer and the wiring metal on the inorganic insulating film. Since they are electrically connected through the through holes formed in the organic insulating film, even if the pad is formed on the organic insulating film having weak mechanical strength to facilitate the connection of the lead to the pad, There is an effect that the mechanical strength of the pad can be improved.
【図１】本発明の第１の実施例に係る半導体基板の構造
を示し、（ａ）が平面図、（ｂ）が（ａ）のＡ−Ａ方向
の断面図である。1A and 1B show a structure of a semiconductor substrate according to a first embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line AA of FIG.
【図２】本発明の第２の実施例に係る半導体基板の構造
を示し、（ａ）が平面図、（ｂ）が（ａ）のＡ−Ａ方向
の断面図である。2A and 2B show a structure of a semiconductor substrate according to a second embodiment of the present invention, FIG. 2A is a plan view, and FIG. 2B is a sectional view taken along line AA of FIG.
【図３】従来の半導体基板の構造を示す断面図である。FIG. 3 is a cross-sectional view showing a structure of a conventional semiconductor substrate.
２０ 窒化膜 ２２，２４ａ〜２４ｄ，４０，４２ａ〜４２ｄ パ
ッド座 ２６，４４ パッド ２８ シリコン含有ポリイミド（ＰＳＩ）層 ３０ａ〜３０ｃ，４６ａ〜４６ｅ スルーホール ３２ チタン・タングステン（ＴｉＷ） ３４ 引出し配線 ５０ａ，５０ｂ 配線20 Nitride film 22, 24a to 24d, 40, 42a to 42d Pad seat 26, 44 Pad 28 Silicon-containing polyimide (PSI) layer 30a to 30c, 46a to 46e Through hole 32 Titanium / tungsten (TiW) 34 Lead wiring 50a, 50b wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/34 Ｂ 9154−4Ｅ 3/46 Ｎ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/34 B 9154-4E 3/46 N 6921-4E
Claims (4)
絶縁膜上に形成された多層有機絶縁膜上のリード接続用
のパッドとを電気的に接続する半導体基板等のパッド構
造において、 前記多層有機絶縁膜の各層上に前記パッド及び前記配線
金属に位置的に対応するように設けられた各層配線金属
を有し、 前記パッド，前記各層配線金属及び前記無機絶縁膜上の
前記配線金属とは、前記各層有機絶縁膜に形成されたス
ルーホールを介して電気的に接続された構成を有するこ
とを特徴とする半導体基板等のパッド構造。1. A pad structure such as a semiconductor substrate for electrically connecting a wiring metal layer on an inorganic insulating film and a pad for lead connection on a multilayer organic insulating film formed on the inorganic insulating film, Each layer wiring metal provided so as to correspond to the pad and the wiring metal on each layer of the multilayer organic insulating film, the pad, the layer wiring metal, and the wiring metal on the inorganic insulating film The pad structure of a semiconductor substrate or the like is characterized in that it is electrically connected through through holes formed in each of the organic insulating films.
無機絶縁膜上の前記配線金属は、共に同一面積の正方形
状のパターンを有し、 前記スルーホールは、前記パターンに対応する位置に形
成された複数の矩形の長尺状のパターンを有する請求項
１記載の半導体基板等のパッド構造。2. The pad, the wiring metal of each layer, and the wiring metal on the inorganic insulating film have a square pattern of the same area, and the through hole is formed at a position corresponding to the pattern. The pad structure for a semiconductor substrate or the like according to claim 1, wherein the pad structure has a plurality of rectangular elongated patterns.
の前記配線金属は、前記パッドに対応する領域の内部に
おいて分割された複数の正方形状のアイランドのパター
ンを有する請求項１記載の半導体基板等のパッド構造。3. The semiconductor substrate according to claim 1, wherein the wiring metal in each layer and the wiring metal on the inorganic insulating film have a pattern of a plurality of square islands divided inside a region corresponding to the pad. Pad structure such as.
の前記配線金属は、金メッキによって構成され、その裏
面上にチタンタングステンが形成されている請求項１記
載の半導体基板等のパッド構造。4. The pad structure of a semiconductor substrate or the like according to claim 1, wherein the wiring metal of each layer and the wiring metal on the inorganic insulating film are formed by gold plating, and titanium tungsten is formed on the back surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7827992A JPH05183007A (en) | 1991-10-29 | 1992-02-28 | Pad structure for semiconductor substrate |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30998991 | 1991-10-29 | ||
| JP3-309989 | 1991-10-29 | ||
| JP7827992A JPH05183007A (en) | 1991-10-29 | 1992-02-28 | Pad structure for semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05183007A true JPH05183007A (en) | 1993-07-23 |
Family
ID=26419354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7827992A Pending JPH05183007A (en) | 1991-10-29 | 1992-02-28 | Pad structure for semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05183007A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001026154A1 (en) * | 1999-10-04 | 2001-04-12 | Philips Semiconductors Inc. | Die pad crack absorption integrated circuit chip and fabrication process |
| US6346471B1 (en) | 1998-05-26 | 2002-02-12 | Nec Corporation | Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor |
| US6653729B2 (en) | 2000-09-29 | 2003-11-25 | Nec Electronics Corporation | Semiconductor device and test method for manufacturing same |
| JP2012169663A (en) * | 1998-07-14 | 2012-09-06 | Texas Instruments Inc | System and method for bonding over active integrated circuits |
-
1992
- 1992-02-28 JP JP7827992A patent/JPH05183007A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346471B1 (en) | 1998-05-26 | 2002-02-12 | Nec Corporation | Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor |
| JP2012169663A (en) * | 1998-07-14 | 2012-09-06 | Texas Instruments Inc | System and method for bonding over active integrated circuits |
| WO2001026154A1 (en) * | 1999-10-04 | 2001-04-12 | Philips Semiconductors Inc. | Die pad crack absorption integrated circuit chip and fabrication process |
| US6503820B1 (en) | 1999-10-04 | 2003-01-07 | Koninklijke Philips Electronics N.V. | Die pad crack absorption system and method for integrated circuit chip fabrication |
| US6653729B2 (en) | 2000-09-29 | 2003-11-25 | Nec Electronics Corporation | Semiconductor device and test method for manufacturing same |
| US6815325B2 (en) | 2000-09-29 | 2004-11-09 | Nec Electronics Corporation | Semiconductor device and test method for manufacturing same |
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