JPH06216526A - Thin-film multi layer printed circuit board - Google Patents
Thin-film multi layer printed circuit boardInfo
- Publication number
- JPH06216526A JPH06216526A JP394593A JP394593A JPH06216526A JP H06216526 A JPH06216526 A JP H06216526A JP 394593 A JP394593 A JP 394593A JP 394593 A JP394593 A JP 394593A JP H06216526 A JPH06216526 A JP H06216526A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin
- bonding pad
- wiring
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は薄膜多層配線基板に係
り、さらに詳しくは、マルチチップモジュールやハイブ
リッドICの構成に適する薄膜多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multi-layer wiring board, and more particularly to a thin film multi-layer wiring board suitable for the construction of multichip modules and hybrid ICs.
【０００２】[0002]
【従来の技術】近年、電子部品もしくは電子回路の小形
化，高密度化（大容量化）などが図られており、たとえ
ばパッケージ化した半導体装置を、いわゆるプリント基
板に搭載・実装することが広く知られている。しかし、
前記従来の実装手段では、その高密度化（大容量化）な
どに限界があるため、薄膜技術によって製造し得る薄膜
多層配線基板を実装用の配線基板とし、たとえば TAB(T
ape Automated Bonding)チップを搭載・実装したマルチ
チップモジュールなどの開発が進められている。図３は
このような薄膜多層配線基板の構成例の要部を断面的に
示したもので、絶縁性支持基板１の所定領域面上に、い
わゆる薄膜多層配線部２を一体的に形成・配置し、その
薄膜多層配線部２の最上面には搭載・実装するチップ素
子３の電極端子3aにボンディングワイヤ４により電気的
に接続するためのボンディングパッド2fを列状に形成し
た構成を成している。すなわち、絶縁性支持基板１面上
に、電源（導体）層2a，厚さ 100〜 150nm程度の無機質
系の絶縁層、たとえば SiO2 層2b，グランド（導体）層
2cを、さらに、 SiO2 層2b1 ，2b2 ，2b3 、導体（信
号）配線層2d1 ，2d2 ，2d3 を交互に積層・一体化し、
最上面にはチップ素子３をマウントするダイパッド2e、
およびチップ素子３の電極端子3aとの間を電気的に接続
するボンディングパッド2fが、前記チップ素子３の電極
端子3aに対応して列状に一体的に配置された構成を成し
ている。 ところで、この種薄膜多層配線板の薄膜多層
配線部２においては、一般的にボンディングパッド2fに
対して、信号配線層2d1 ，2d2 ，2d3 の配線幅が小さく
（細く）設定されている。図４および図５は、異なる信
号配線層2d2 ，2d3 について、最上面のボンディングパ
ッド2fに対するパターニングを模式的に示したもので、
いずれの場合も配線幅がほぼ一定に設定されている。2. Description of the Related Art In recent years, electronic parts or electronic circuits have been miniaturized and increased in density (increased capacity). For example, packaged semiconductor devices are widely mounted and mounted on so-called printed circuit boards. Are known. But,
Since the conventional mounting means has a limitation in increasing the density (capacity), a thin-film multilayer wiring board that can be manufactured by a thin-film technology is used as a wiring board for mounting, for example, TAB (T
Development of a multi-chip module equipped with and mounting ape Automated Bonding) chips is underway. FIG. 3 is a cross-sectional view showing a main part of a configuration example of such a thin film multilayer wiring board, in which a so-called thin film multilayer wiring section 2 is integrally formed and arranged on a predetermined area surface of an insulating support substrate 1. On the uppermost surface of the thin-film multi-layer wiring section 2, bonding pads 2f for electrically connecting to the electrode terminals 3a of the chip element 3 to be mounted and mounted by the bonding wires 4 are formed in rows. There is. That is, a power source (conductor) layer 2a, an inorganic insulating layer having a thickness of about 100 to 150 nm, such as a SiO 2 layer 2b, a ground (conductor) layer, is formed on the surface of the insulating support substrate 1.
2c, and SiO 2 layers 2b 1 , 2b 2 , 2b 3 and conductor (signal) wiring layers 2d 1 , 2d 2 , 2d 3 are alternately laminated and integrated,
A die pad 2e for mounting the chip element 3 on the uppermost surface,
The bonding pads 2f for electrically connecting the electrode terminals 3a of the chip element 3 and the electrode terminals 3a of the chip element 3 are integrally arranged in a row corresponding to the electrode terminals 3a of the chip element 3. By the way, in the thin-film multilayer wiring part 2 of this kind of thin-film multilayer wiring board, the wiring width of the signal wiring layers 2d 1 , 2d 2 , 2d 3 is generally set to be small (thin) with respect to the bonding pad 2f. . FIGS. 4 and 5 schematically show patterning of the uppermost bonding pad 2f for different signal wiring layers 2d 2 and 2d 3 .
In either case, the wiring width is set to be almost constant.
【０００３】なお、上記構成においては、薄膜多層配線
部２の信号配線層2d1 ，2d2 ，2d3およびボンディング
パッド2f間が、たとえばビア接続2gによって電気的に接
続され、所要の配線回路を形成している。In the above structure, the signal wiring layers 2d 1 , 2d 2 , 2d 3 of the thin film multilayer wiring portion 2 and the bonding pads 2f are electrically connected by, for example, a via connection 2g, and a required wiring circuit is formed. Is forming.
【０００４】[0004]
【発明が解決しようとする課題】しかし、前記構成の薄
膜多層配線基板の場合は、次のような不都合な問題が認
められる。たとえば、多層配線部２の上面に所要のチッ
プ素子３をマウントし、そのチップ素子３の電極端子3a
と対応するボンディングパッド2fに、ワイヤボンディン
グする場合など、ボンディング性が劣るという問題があ
る。つまり、薄膜多層配線部２においては、一般的に信
号配線層2d1 ，2d2 ，2d3 の配線幅が小さく、ボンディ
ングパッド2fの幅よりも狭いため、この信号配線層2
d1 ，2d2 ，2d3 の配線領域上にボンディングパッド2f
が配置されると必然的に段差が生じることになる。この
ボンディングパッド2f面の段差発生は、ボンディングパ
ッド2f面の凹凸化を意味し、ボンディングワイヤの位置
決めの困難さ、もしくは位置ズレの起こり易さとなる一
方、また半田リフローなどによる場合は不均一な半田付
けを伴うことになり、結果的に信頼性の高い実装を達成
し得ないことになる。この点さらに詳述すると、この種
の薄膜多層配線板においては、薄膜多層配線部２の層間
絶縁層2b1 ，2b2 ，2b3 が 2〜15μm 程度と薄いため、
信号配線層2d1 ，2d2 ，2d3 の存否なども薄膜多層配線
部２表面の平坦性に影響を及ぼし易く、前記のようにボ
ンディングパッド2fに対して幅の狭い信号配線層2d1 ，
2d2 ，2d3 が直下領域に内層・配置されていても、段差
の発生が容易に認められる。そして、このような現象は
個々のボンディングパッド2fだけでなく、列状に配置さ
れているボンディングパッド2f間、換言すると直下領域
に信号配線層2d1 ，2d2 ，2d3が内層・配置されている
ボンディングパッド2fと信号配線層2d1 ，2d2 ，2d3 が
内層・配置されていないボンディングパッド2fとの間で
も段差が生じ、ボンディングパッド2f列としての平坦性
が損なわれることになる。したがって、前記ワイヤボン
ディングなどにおいて、たとえばボンディングツールの
均一的なボンディング作用の達成が困難となり、ボンデ
ィングの信頼性が損なわれ易いという問題がある。However, in the case of the thin-film multilayer wiring board having the above-mentioned structure, the following inconvenient problems are recognized. For example, a required chip element 3 is mounted on the upper surface of the multilayer wiring part 2 and the electrode terminal 3a of the chip element 3 is mounted.
There is a problem in that the bondability is inferior, for example, when wire bonding is performed on the bonding pad 2f corresponding to. That is, in the thin-film multilayer wiring section 2, the wiring width of the signal wiring layers 2d 1 , 2d 2 and 2d 3 is generally small and narrower than the width of the bonding pad 2f.
Bonding pad 2f on the wiring area of d 1 , 2d 2 , 2d 3
When is placed, a step will inevitably occur. The occurrence of a step on the bonding pad 2f surface means unevenness of the bonding pad 2f surface, which makes it difficult to position the bonding wire or easily causes a positional deviation, and when solder reflow or the like causes uneven soldering. As a result, a reliable implementation cannot be achieved as a result. More specifically, in this type of thin-film multilayer wiring board, the interlayer insulating layers 2b 1 , 2b 2 and 2b 3 of the thin-film multilayer wiring portion 2 are as thin as about 2 to 15 μm.
The presence / absence of the signal wiring layers 2d 1 , 2d 2 , 2d 3 easily influences the flatness of the surface of the thin-film multilayer wiring portion 2, and as described above, the signal wiring layer 2d 1 , which is narrower than the bonding pad 2f,
Even if 2d 2 and 2d 3 are inner layers / arranged in the region directly below, a step can be easily observed. Such a phenomenon is caused not only by the individual bonding pads 2f but also between the bonding pads 2f arranged in a row, in other words, the signal wiring layers 2d 1 , 2d 2 , 2d 3 are directly arranged in the inner layer / arrangement. A step also occurs between the existing bonding pad 2f and the bonding pad 2f in which the signal wiring layers 2d 1 , 2d 2 and 2d 3 are not arranged / arranged, and the flatness of the bonding pad 2f row is impaired. Therefore, in the wire bonding or the like, for example, it becomes difficult to achieve a uniform bonding action of the bonding tool, and there is a problem that the reliability of bonding is easily impaired.
【０００５】本発明は上記事情に対処してなされたもの
で、上面に列状に配置されているボンディングパッド面
の段差を解消し、良好なボンディング性を持たせること
により、信頼性の高いマルチチップモジュールなど容易
に構成し得る薄膜多層配線基板の提供を目的とする。The present invention has been made in consideration of the above circumstances, and eliminates the step difference of the bonding pad surface arranged in a row on the upper surface and provides good bonding performance, thereby providing a highly reliable multi-bonding device. An object of the present invention is to provide a thin-film multilayer wiring board that can be easily configured such as a chip module.
【０００６】[0006]
【課題を解決するための手段】本発明に係る薄膜多層配
線基板は、支持基板主面上に一体的に形成・配置された
導体配線層および電気絶縁層を交互に積層し、かつ上面
の所定箇所にボンディングパッドが列状に形設・配置さ
れた薄膜多層配線部を具備して成る薄膜多層配線基板に
おいて、前記薄膜多層配線部のボンディングパッド直下
領域に内層されている導体配線幅をボンディングパッド
の幅と同一以上に選択・設定するとともに、導体配線が
内層されていない他のボンディングパッド直下領域にダ
ミー層を配設定して、前記列状のボンディングパッド面
を平坦化させたことを特徴とする。A thin-film multilayer wiring board according to the present invention has conductor wiring layers and electric insulation layers which are integrally formed and arranged integrally on a main surface of a supporting substrate and which are alternately laminated and have a predetermined upper surface. In a thin film multilayer wiring board comprising a thin film multilayer wiring part in which bonding pads are formed and arranged in a row at a location, the width of the conductor wiring inside the bonding pad of the thin film multilayer wiring part is set to the bonding pad. The width is equal to or larger than the width of the bonding pad, and a dummy layer is arranged in a region directly under another bonding pad in which the conductor wiring is not inner layered to flatten the row of bonding pad surfaces. To do.
【０００７】[0007]
【作用】本発明によれば、多層配線部の信号配線のう
ち、上面に列状に配設されているボンディングパッドの
直下に位置する領域において、その信号配線幅を平面的
に膨大化して、前記上層に位置するボンディングパッド
が平面を保持し得る構成を採る一方、信号配線が直下に
存在しない他のボンディングパッドの直下領域にはダミ
ー層を内層・配置して、ボンディングパッド列が全体的
に平坦性を採るよう形成されている。つまり、信号配線
の内層に起因する列状のボンディングパッド面の段差付
けが容易、かつ確実に回避（解消）されて、全体的に良
好な平面（平坦）性を呈しているため、ボンディング性
が大幅に向上・改善され、信頼性の高いボンディングが
可能となり、品質のすぐれたマルチチップモジュールな
どの構成に大きく寄与する。According to the present invention, in the signal wiring of the multi-layer wiring portion, in the region located directly below the bonding pads arranged in rows on the upper surface, the signal wiring width is enlarged in plan view, While the bonding pad located on the upper layer has a structure capable of holding a flat surface, a dummy layer is arranged in the area immediately below the other bonding pad where the signal wiring does not exist immediately below, so that the bonding pad row is entirely formed. It is formed to have flatness. In other words, the stepping of the row-shaped bonding pad surface due to the inner layer of the signal wiring is easily and surely avoided (eliminated), and the overall good flatness (flatness) is exhibited. Significantly improved and improved, highly reliable bonding is possible, which greatly contributes to the construction of high-quality multi-chip modules.
【０００８】[0008]
【実施例】以下、図１〜図３を参照して本発明の一実施
例を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
【０００９】本発明に係る薄膜多層配線基板は、その基
本的な構成においては従来の場合と同様といえる。すな
わち、その構成は、前記図３に要部構成例を断面的に示
したごとく、支持基板１の所定領域面上に、いわゆる薄
膜多層配線部２を一体的に形成・配置し、その薄膜多層
配線部２の最上面には搭載・実装するたとえばチップ素
子３の電極端子3aを電気的に接続するためのボンディン
グパッド2fを形成した構成を成している。さらに詳述す
ると、支持基板１面上に、電源（導体）層2a，厚さ 100
〜 150nm程度の無機質系の絶縁層、たとえば SiO2 層2
b，グランド（導体）層2cを、さらに、 SiO2 層2b1 ，2
b2 ，2b3 、導体（信号）配線層2d1 ，2d2 ，2d3 を交
互に積層・一体化し、最上面にはチップ素子３をマウン
トするダイパッド2e、およびチップ素子３の電極端子3a
をワイヤボンディング４により電気的に接続するボンデ
ィングパッド2fが列状に一体的に配置された構成を成し
ている。The thin-film multilayer wiring board according to the present invention can be said to have the same basic structure as the conventional case. That is, as shown in the cross-sectional view of the main part configuration example in FIG. 3, the structure is such that the so-called thin film multilayer wiring part 2 is integrally formed and arranged on the surface of a predetermined region of the supporting substrate 1, and the thin film multilayer wiring part is formed. A bonding pad 2f for electrically connecting the electrode terminal 3a of the chip element 3 to be mounted / mounted, for example, is formed on the uppermost surface of the wiring portion 2. More specifically, the power supply (conductor) layer 2a and the thickness 100 are formed on the surface of the supporting substrate 1.
~ 150 nm inorganic insulating layer, for example SiO 2 layer 2
b, the ground (conductor) layer 2c, and the SiO 2 layers 2b 1 and 2
b 2 , 2b 3 , conductor (signal) wiring layers 2d 1 , 2d 2 , 2d 3 are alternately laminated and integrated, and the die pad 2e for mounting the chip element 3 on the uppermost surface and the electrode terminal 3a of the chip element 3
Bonding pads 2f for electrically connecting to each other by wire bonding 4 are integrally arranged in a row.
【００１０】ところで、本発明に係る薄膜多層配線板に
おいては、前記薄膜多層配線部２の構成の一部を、次の
ように変更・設定した点で特徴付けられる。すなわち、
前記列状に設けられているボンディングパッド2fに対し
て、その直下領域に位置する信号配線層2d1 ，2d2 ，2d
3 の配線幅を、特に、選択的に膨大化した形状に設定す
るとともに、信号配線が直下に存在しない領域にはボン
ディングパッド2f面と同一面積もしくはやや大きめのダ
ミー片（層）2hを内層・配置している。図１および図２
は、互いに異なる信号配線層、たとえば信号配線層2
d2 ，2d3 について、最上面のボンディングパッド2fに
対するパターニングを模式的に示したもので、いずれの
場合も、ボンディングパッド2fの直下の領域に位置する
信号配線幅を、前記ボンディングパッド2f幅と同一幅な
いしやや大きめに選択的に膨大に設定する一方、信号配
線が存在しない領域にはボンディングパッド2f面と同一
面積ないしやや大きめのダミー片（層）2hが内層・配置
されている。なお、上記構成においては、薄膜多層配線
部２の信号配線層2d1 ，2d2 ，2d3 およびボンディング
パッド2f間が、たとえばビア接続2gによって電気的に接
続され、所要の配線回路を形成している。By the way, the thin film multilayer wiring board according to the present invention is characterized in that a part of the structure of the thin film multilayer wiring section 2 is changed and set as follows. That is,
The signal wiring layers 2d 1 , 2d 2 , 2d located immediately below the bonding pads 2f arranged in a row are located.
In particular, the wiring width of 3 is set to a selectively enlarged shape, and a dummy piece (layer) 2h having the same area as or slightly larger than the bonding pad 2f surface is formed in the inner layer in the area where the signal wiring does not exist directly below. It is arranged. 1 and 2
Are different signal wiring layers, for example, signal wiring layer 2
With respect to d 2 and 2d 3 , patterning of the uppermost bonding pad 2f is schematically shown. In each case, the signal wiring width located immediately below the bonding pad 2f is referred to as the bonding pad 2f width. On the other hand, the dummy pieces (layers) 2h having the same area as or slightly larger than the bonding pad 2f surface are arranged in the inner layer in a region where the signal wiring does not exist, while the width is set to be the same width or slightly larger. In the above structure, the signal wiring layers 2d 1 , 2d 2 , 2d 3 of the thin film multilayer wiring section 2 and the bonding pads 2f are electrically connected by, for example, the via connection 2g to form a required wiring circuit. There is.
【００１１】上記本発明に係る薄膜多層配線板は、この
種薄膜多層配線板の製造において通常採られている製造
手段に基づいて容易に製造し得る。すなわち、この種の
薄膜多層配線板の常套的な製造手段で、前記絶縁層2
b1 ，2b2 ，2b3 および信号配線層2d1 ，2d2 ，2d3 の
交互・積層化工程の一部を変更し、信号配線層2d1 ，2d
2，2d3 のパターニング工程において、設計上予定して
いるボンディングパッド2f列の直下に配設される信号配
線の一部を選択的に膨大に設定する一方、同じく設計上
予定している他のボンディングパッド2fの直下領域に
は、前記信号配線と同程度厚の絶縁された金属片や樹脂
層などダミー層2hを所定位置（領域）に、適宜介挿・配
設する操作を加えるだけで容易に製造し得る。The thin-film multilayer wiring board according to the present invention can be easily manufactured based on the manufacturing means usually adopted in manufacturing such a thin-film multilayer wiring board. That is, the insulating layer 2 is manufactured by a conventional manufacturing method for this kind of thin-film multilayer wiring board.
b 1, 2b 2, 2b 3 and the signal wiring layer 2d 1, 2d 2, change some 2d 3 alternating-laminating step, the signal wiring layer 2d 1, 2d
In the patterning process of 2 and 2d 3 , a part of the signal wiring arranged directly below the row of bonding pads 2f, which is planned for design, is selectively set to an enormous amount, while other parts of the same design are planned. It is easy to just insert the dummy layer 2h such as an insulated metal piece or resin layer, which is about the same thickness as the signal wiring, in a predetermined position (area) directly below the bonding pad 2f. Can be manufactured.
【００１２】本発明は上記例示に限定されるものでな
く、発明の主旨を逸脱しない範囲で種々の変形を採り得
る。すなわち、支持基板としては、酸化膜付きのシリコ
ン基板に限られず、たとえばAl2 O 3 基板やポリイミド
樹脂系基板、低抵抗化したSi基板などでもよいし、多層
配線部の絶縁層も SiO2 層の代わりに、たとえばガラス
層、ポリイミド樹脂層やベンゾシクロブテン樹脂層など
でもよい。また、電源層，グランド層，信号配線層など
の材質も適宜選択される。The present invention is not limited to the above examples, and various modifications can be made without departing from the gist of the invention. That is, the support substrate is not limited to a silicon substrate with an oxide film, and may be, for example, an Al 2 O 3 substrate, a polyimide resin substrate, a low-resistance Si substrate, or the insulating layer of the multi-layer wiring part is a SiO 2 layer. Instead of, for example, a glass layer, a polyimide resin layer, a benzocyclobutene resin layer, or the like may be used. Further, the materials for the power supply layer, the ground layer, the signal wiring layer, etc. are also selected appropriately.
【００１３】[0013]
【発明の効果】以上説明したように、本発明に係る薄膜
多層配線基板においては、多層配線部の信号配線のう
ち、上面に配設されている列状のボンディングパッドの
直下領域では、その信号配線幅を平面的に膨大化して、
前記上層に位置するボンディングパッドが平面を保持し
得る構成を採る一方、他のボンディングパッドの直下に
信号配線が存在しない領域にはダミー層を内層・配置し
て、列状を成すボンディングパッド面が一様の平坦性を
採るように形成されている。つまり、信号配線に起因す
るボンディングパッド面の段差付けが全体的に容易、か
つ確実に回避（解消）されて、良好な平面（平坦）性を
呈しているため、ボンディング性が大幅に向上・改善さ
れ、信頼性の高いボンディングが可能となり、品質のす
ぐれたマルチチップモジュールなどの構成に大きく寄与
する。As described above, in the thin-film multi-layer wiring board according to the present invention, in the signal wiring of the multi-layer wiring portion, in the area directly below the row-shaped bonding pads arranged on the upper surface, the signal Enlarging the wiring width in a plane,
While the bonding pad located on the upper layer has a structure capable of holding a flat surface, a dummy layer is arranged in an inner layer in a region where no signal wiring exists immediately below another bonding pad to form a row of bonding pad surfaces. It is formed so as to have uniform flatness. In other words, the stepping of the bonding pad surface due to the signal wiring is easily and reliably avoided (eliminated) on the whole, and good flatness (flatness) is exhibited, so that the bondability is greatly improved and improved. Therefore, highly reliable bonding becomes possible, which greatly contributes to the construction of a multi-chip module having excellent quality.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明に係る薄膜多層配線基板の一信号配線層
のパターニング例の要部を示す平面図。FIG. 1 is a plan view showing a main part of a patterning example of one signal wiring layer of a thin-film multilayer wiring board according to the present invention.
【図２】本発明に係る薄膜多層配線基板の他の信号配線
層のパターニング例の要部を示す平面図。FIG. 2 is a plan view showing a main part of a patterning example of another signal wiring layer of the thin-film multilayer wiring board according to the present invention.
【図３】薄膜多層配線基板の要部構成を示す断面図。FIG. 3 is a cross-sectional view showing the main configuration of a thin-film multilayer wiring board.
【図４】従来の薄膜多層配線基板の一信号配線層のパタ
ーニング例の要部を示す平面図。FIG. 4 is a plan view showing a main part of a patterning example of one signal wiring layer of a conventional thin film multilayer wiring board.
【図５】従来の薄膜多層配線基板の他の信号配線層のパ
ターニング例の要部を示す平面図。FIG. 5 is a plan view showing a main part of another patterning example of a signal wiring layer of a conventional thin film multilayer wiring board.
１…支持基板 ２…薄膜多層配線部 2a…電源層
2b…絶縁層 2c，5c…グランド層 2b1 ，2b2 ，
2b3 …層間絶縁層 2d1 ，2d2 ，2d3 …信号配線層
2e…ダイパッド 2f…ボンディングパッド 2g…
ビア接続 2h…ダミー層（片） ３…チップ素子
3a…チップ素子の電極端子 ４…ボンディングワイヤ1 ... Supporting substrate 2 ... Thin film multilayer wiring part 2a ... Power supply layer
2b ... Insulating layer 2c, 5c ... Ground layer 2b 1 , 2b 2 ,
2b 3 … Interlayer insulation layer 2d 1 , 2d 2 , 2d 3 … Signal wiring layer
2e ... Die pad 2f ... Bonding pad 2g ...
Via connection 2h… Dummy layer (single) 3… Chip element
3a ... Chip element electrode terminal 4 ... Bonding wire
Claims (1)
れた導体配線層および電気絶縁層を交互に積層し、かつ
上面の所定箇所にボンディングパッドが列状に形設・配
置された薄膜多層配線部を具備して成る薄膜多層配線基
板において、 前記薄膜多層配線部のボンディングパッド直下領域に内
層されている導体配線幅をボンディングパッドの幅と同
一以上の幅に選択・設定するとともに、導体配線が内層
されていない他のボンディングパッド直下領域にダミー
層を配設定して、前記列状のボンディングパッド面を平
坦化させたことを特徴とする薄膜多層配線基板。1. A conductor wiring layer and an electric insulating layer integrally formed and arranged on a main surface of a supporting substrate are alternately laminated, and bonding pads are formed and arranged in rows at predetermined positions on the upper surface. In a thin film multi-layer wiring board comprising a thin film multi-layer wiring section, while selecting and setting the width of the conductor wiring inside the region immediately below the bonding pad of the thin-film multi-layer wiring section to a width equal to or greater than the width of the bonding pad, A thin film multi-layer wiring board characterized in that a dummy layer is arranged in a region immediately below another bonding pad in which no conductor wiring is provided as an inner layer to flatten the bonding pad surface in rows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP394593A JPH06216526A (en) | 1993-01-13 | 1993-01-13 | Thin-film multi layer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP394593A JPH06216526A (en) | 1993-01-13 | 1993-01-13 | Thin-film multi layer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216526A true JPH06216526A (en) | 1994-08-05 |
Family
ID=11571264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP394593A Withdrawn JPH06216526A (en) | 1993-01-13 | 1993-01-13 | Thin-film multi layer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216526A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100264162B1 (en) * | 1997-08-28 | 2000-08-16 | 구본준 | Structure of a pad formed on a substrate of a lcd and methode of manufactuaring the same |
| US7342177B2 (en) | 2003-02-04 | 2008-03-11 | Seiko Epson | Wiring board, electro-optical device and electronic instrument |
| JP2013128118A (en) * | 2011-12-19 | 2013-06-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
| JP2013229079A (en) * | 2012-04-26 | 2013-11-07 | Dainippon Printing Co Ltd | Substrate for suspension, suspension, suspension with element, and hard disk drive |
| JP2015156252A (en) * | 2015-05-21 | 2015-08-27 | 大日本印刷株式会社 | Flexure substrate for suspension, suspension, suspension with head, and hard disk drive |
-
1993
- 1993-01-13 JP JP394593A patent/JPH06216526A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100264162B1 (en) * | 1997-08-28 | 2000-08-16 | 구본준 | Structure of a pad formed on a substrate of a lcd and methode of manufactuaring the same |
| US7342177B2 (en) | 2003-02-04 | 2008-03-11 | Seiko Epson | Wiring board, electro-optical device and electronic instrument |
| JP2013128118A (en) * | 2011-12-19 | 2013-06-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
| JP2013229079A (en) * | 2012-04-26 | 2013-11-07 | Dainippon Printing Co Ltd | Substrate for suspension, suspension, suspension with element, and hard disk drive |
| JP2015156252A (en) * | 2015-05-21 | 2015-08-27 | 大日本印刷株式会社 | Flexure substrate for suspension, suspension, suspension with head, and hard disk drive |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000404 |