JP5191688B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a system in package (SiP) in which a system is configured by mounting one or a plurality of semiconductor chips on a wiring board.

  As a technology to meet the demand for multi-functionality of semiconductor devices for processing and storing large volumes of information at high speed, a system in which multiple semiconductor chips such as microprocessors and memories are configured as one system in the same package. -Package (SiP) technology is drawing attention. A plurality of semiconductor chips configured in a package are mounted side by side or stacked on a wiring board, and desired connection is made on the wiring board.

In recent years, with the increase in the number of functions of semiconductor chips, the wiring connecting the respective semiconductor chips has become more complex, and multilayer wiring boards and miniaturization of wiring design rules have been promoted. Further, for example, Japanese Patent Application Laid-Open No. 2004-153295 (Patent Document 1) discloses a technique that enables connection to a desired location on a wiring board by using a relay chip and reduces routing by the wiring board. Has been.
JP 2004-153295 A

  However, the present inventors have found the following problems in the substrate wiring technology in the system-in-package.

  As described above, along with the increase in functionality of individual semiconductor chips constituting the system-in-package, the routing of wiring on the wiring board has become complicated. In other words, when connecting from a terminal on a semiconductor chip to a desired pad on a wiring board by wire bonding or the like, the system-in-package having a plurality of semiconductor chips has a low degree of freedom, so that a pad with sufficient space can be obtained. Once connected, the wiring board is routed to a desired pad. And with the increase in functionality and the number of pins of individual semiconductor chips, the wiring routing has become complicated. As a result, multilayer technology for wiring boards and miniaturization of design rules are trends in current technology.

  Originally, it is a system-in-package that aims to reduce the size of a multifunctional system by configuring a plurality of semiconductor chips in one package.・ It will hinder downsizing of the package. Furthermore, the requirement for miniaturization of the design rules for the substrate wiring means that a more advanced manufacturing technique is required, which causes an increase in package cost.

  Further, in a system-in-package equipped with a circuit that handles a plurality of synchronization signals, etc., equal-length wiring is required between each semiconductor chip that constitutes. From this point of view, if the wiring of the substrate wiring becomes complicated, it is difficult to make the isometric wiring due to space limitations.

  In addition, in a system-in-package that requires high-capacity information processing at high speed, it is better to qualitatively shorten the wiring length, but in the method of routing complicated wiring with a multilayer board as described above, The wiring length becomes longer.

  As the above countermeasures, the present inventors have examined the technique disclosed in Patent Document 1. Here, as one of the semiconductor chips that make up the system-in-package, a chip (relay chip) that relays the connection by bonding wires is introduced to enable direct bonding to a desired location on the wiring board. By doing so, the routing wiring is reduced. However, the introduction of such a relay chip causes a further increase in the size of a system-in-package that is already composed of a plurality of semiconductor chips. Therefore, even if the number of wiring board layers can be reduced by this technique, the above-described problem that prevents the downsizing of the system-in-package cannot be essentially solved.

  As described above, the present inventors have found that in downsizing of a higher performance system-in-package, problems are concentrated on complicated routing wiring on a wiring board.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for realizing miniaturization in a high-performance system-in-package that requires complicated wiring.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

In other words, a method for manufacturing a semiconductor device including a plurality of semiconductor chips includes the following steps:
(A) a first surface, a first element formed on the first surface, a first insulating film formed on the first surface, and a first wiring formed on the first insulating film; , A first passivation film formed on the first wiring, a first conductor portion exposed from the first passivation film and formed on the first wiring, and a first conductor opposite to the first surface. Preparing a first semiconductor chip having one back surface;
(B) after the step (a), the bottom of the cavity of the first core member having a first main surface cavity is formed and a second main surface opposite to the first main surface, Fixing the first semiconductor chip such that the first back surface of the first semiconductor chip faces the bottom of the cavity ;
(C) After the step (b), a step of sealing the first semiconductor chip with a resin material;
(D) After the step (c), forming a second wiring on the first surface of the first semiconductor chip and electrically connecting the first wiring;
(E) a step of covering the second wiring with a solder resist after the step (d);
(F) After the step (e), the second surface, the second element formed on the second surface, the bonding pad conducting to the second element, and the second surface opposite to the second surface Fixing a second semiconductor chip having two back surfaces on the solder resist;
(G) After the step (f), electrically connecting the bonding pad of the second semiconductor chip and the first conductor part via a conductive part;
(H) After the step (g), a step of sealing the second semiconductor chip with a resin;
(I) A step of forming a bump electrode on a BGA land formed on the second main surface of the first core material after the step (h).

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, downsizing can be realized in a high-performance system-in-package that requires complicated wiring.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The semiconductor device according to the embodiment of the present invention is a so-called system in package (SiP) that constitutes a function-complete system or subsystem by using a plurality of semiconductor chips as the same package. In this semiconductor device, a technique for reducing the routing on the wiring board by forming the wiring on the semiconductor chip will be exemplified.

  The structure of the semiconductor device of this embodiment will be described with reference to FIGS.

  FIG. 1 is a plan view of a semiconductor device exemplified in the present embodiment, particularly a system-in-package SiP, and FIG. 2 is a cross-sectional view taken along line xx of FIG.

  A wiring substrate 1 constituting this semiconductor device is made of a flat rectangular thin plate, and has a main surface (first main surface) S1 and a back surface (second main surface) S2 located on opposite sides along the thickness direction. have.

  Two kinds of semiconductor chips 2 a and 2 b are stacked as the first semiconductor chip 2 on the main surface S <b> 1 of the wiring substrate 1. In the present embodiment, the first semiconductor chip 2 is composed of two types of semiconductor chips 2a and 2b. In order to construct a desired system required for the system-in-package SiP, the first semiconductor chip 2 is used. The chip 2 may be a single chip or three or more chips. The back surface of the lower semiconductor chip 2b is bonded to the main surface S1 of the wiring substrate 1 through the paste agent 3, and the back surface of the upper semiconductor chip 2a is bonded to the main surface of the lower semiconductor chip 2b through the paste agent 3. ing. In each of the semiconductor chips 2a and 2b, a plurality of integrated circuit elements for forming a desired integrated circuit such as a microprocessor or a memory are formed, and these two types of semiconductor chips 2a and 2b are provided. The formed integrated circuits are electrically connected to each other through wiring or the like on the wiring board 1 so that a desired system is configured as a whole. Bonding pads BP are formed on the individual semiconductor chips 2a and 2b in order to electrically connect the integrated circuit from the outside. Here, a connection such as a bonding wire BW can be made. At this time, the upper semiconductor chip 2a needs to be stacked in a state of being displaced in a plane with respect to the semiconductor chip 2b so as not to cover the bonding pads BP of the lower semiconductor chip 2b. The first semiconductor chip 2 mounted on the main surface S1 of the wiring board 1 is sealed with, for example, a resin material R1. The resin material R1 is formed of a resin such as an epoxy resin. Although there are a plurality of conductive wirings using the bonding pads BP and the bonding wires BW, only one wiring representing them is shown in FIG. 1 for convenience. Further, in FIG. 1, the bonding pads BP or the bonding wires BW are not on the xx line cross section, but these are projected and shown in FIG.

  On the back surface S <b> 2 of the wiring substrate 1, a plurality of bump electrodes (a plurality of electrodes) 4 are exposed and arranged regularly at predetermined intervals. That is, the semiconductor device of the present embodiment has a BGA (Ball Grid Array) package configuration. The system-in-package SiP can be mounted on the desired motherboard, for example, together with the semiconductor device constituting another system via the plurality of bump electrodes 4.

  The wiring board 1 has, as a basic part, core materials 1a and 1b formed of a resin such as a glass epoxy resin. The basic portion of the wiring board 1 is formed by stacking the core material 1a formed in a planar frame shape along the outer periphery of the main surface on the main surface of the planar quadrangular core material 1b. A plurality of electrodes 5 are formed on each of the main surface S1 and the back surface S2 of the wiring substrate 1 along each side of the wiring substrate 1 (FIG. 1 shows only one electrode 5 for simplicity). ) A prepreg 1c, which is an insulating film, is formed between the main surface S1 and the back surface S2 of the basic portion of the wiring substrate 1 adjacent to each other, and insulation between the electrodes 5 is ensured.

  The electrodes 5 on the main surface S1 and the back surface S2 of the basic part of the wiring board 1 are electrically connected by a through-hole wiring (first conductive portion) E1 that penetrates between the main surface S1 and the back surface S2. In addition, an electrode (hereinafter referred to as a BGA land) 6 electrically connected to the electrode 5 is formed on the back surface S2 of the wiring board 1, and the bump electrode 4 is electrically connected to the electrode 5 through the BGA land 6. It is connected to the.

  Further, on the main surface S1 of the wiring substrate 1, a first wiring W1 made of, for example, a metal material mainly composed of copper (Cu) is formed to realize wiring between chips or electrical connection with the electrode 5. doing. That is, with the above configuration, the bump electrode 4 formed on the back surface S2 of the wiring board 1 is connected to the electrode 5 formed on the main surface S1 of the wiring board 1 or the first wiring W1 via the through-hole wiring E1. Are electrically connected.

  Both the first wiring W1 formed on the main surface S1 of the wiring board 1 and the BGA land 6 formed on the back surface S2 are covered with the solder resist 1d. Here, on the main surface S1 of the wiring substrate 1, the solder resist 1d above the electrode 5 is opened at a location where direct electrical connection to the electrode 5 is required without passing through the first wiring W1. Yes. At this time, the electrode 5 is covered with a conductor film 5a in order to prevent exposure.

  Usually, the first semiconductor chip 2 constituting the system in the system-in-package SiP has the bonding wire BW drawn from the bonding pad BP formed on the semiconductor chips 2a and 2b and exposed to the main surface S1 of the wiring board 1. By connecting to the electrode 5, the bump electrode 4 on the opposite side is electrically connected through the through-hole wiring E1.

  At this time, as exemplified in the present embodiment, when the first semiconductor chip 2 is configured by stacking a plurality of semiconductor chips 2a and 2b, the underlying semiconductor chip 2b can be exposed. The position of the pad BP is limited. When it is necessary to electrically connect to the bump electrode 4 at a location away from the position of the exposed bonding pad BP, the technique studied by the present inventors can use the circuit board 1 up to the desired bump electrode 4. The first wiring W1 is routed above, or the bonding wire BW is routed using a relay chip or the like. At this time, if the first semiconductor chip 2 is multi-functionalized and multi-pinned, there is no space for connection, and the routing wiring becomes more complicated. As a result, strict design rules are required to accommodate the first wiring W1 on the wiring board 1. In some cases, it is necessary to cross the first wiring W1. For this reason, a technique for multilayering the wiring board 1 or adding a new relay chip that does not constitute the original system has been developed and put into practical use for the purpose of relaxing design rules and wiring intersections. Yes. However, these are all factors that hinder downsizing of the system-in-package SiP, and as a result, the proportion of the wiring board 1 in the manufacturing cost of the system-in-package SiP is increased.

  On the other hand, in this Embodiment, said subject is avoided with the following structures.

  First, a so-called cavity 7 that is recessed in the thickness direction of the wiring board 1 is formed in the center of the main surface S <b> 1 of the wiring board 1. The side surface of the cavity 7 is formed by the wall surface in the frame of the core material 1a, and the bottom surface of the cavity 7 is formed by the upper surface of the core material 1b.

  The second semiconductor chip 8 is accommodated in such a cavity 7. That is, the second semiconductor chip 8 is built in a region between the main surface S1 and the back surface S2 of the wiring board 1. The second semiconductor chip 8 uses, for example, single crystal silicon (Si) as a base material. In the present embodiment, the above-described configuration can be obtained by placing the second semiconductor chip 8 in the cavity 7 formed in the wiring board 1 and fixing it with the paste 3 or the like, for example.

  On the main surface of the second semiconductor chip 8, a second wiring W2 is formed. The second wiring W2 is used as the above-described routing wiring. That is, a plurality of electrodes 9 for electrical connection from outside are formed on the second wiring W2 formed on the second semiconductor chip 8, one on the first semiconductor chip 2 and one on the bump. By connecting to the first wiring W1 that is electrically connected to the electrode 4, for example, the bump electrode 4 at a location away from the bonding pad BP of the lower semiconductor chip 2b in the first semiconductor chip 2 can also be electrically connected. Connection becomes possible. Then, as described above, the second semiconductor chip 8 having the second wiring W2 for the routing wiring is built in the wiring board 1, and even when such a new chip is introduced, the system This does not prevent downsizing of the in-package SiP.

  Further, although the process of forming the second wiring W2 will be described in detail later, in this embodiment, a so-called semiconductor wafer process, that is, an insulating film formation by a CVD method or a thermal oxidation method, a wiring pattern by a photolithography method, etc. It is formed by a series of procedures such as metal film formation by transfer, sputtering method, vapor deposition method or plating method, and wiring pattern formation by etching or the like.

  In general, the technique for forming the first wiring W1 on the wiring substrate 1 is the current control on the order of μm, whereas the technique for forming the second wiring W2 on the second semiconductor chip 8 by the semiconductor wafer process described above. Can be controlled in nm order. Therefore, according to the technique exemplified in the present embodiment, the routing wiring, which has a structure that cannot be realized without being multilayered without being accommodated by the single-layer wiring board 1, can be realized by a single layer by using the semiconductor wafer process. It is possible. Furthermore, in the semiconductor wafer process, for example, a large number of transistors can be multilayered. Even in this case, since the control is performed in the nm order as described above, the package thickness does not increase.

  Here, the details of the configuration of the second semiconductor chip 8 having the second wiring W2 exemplified in the present embodiment will be described.

  The second wiring W2 included in the second semiconductor chip 8 is made of a metal material mainly composed of, for example, Cu or aluminum (Al). Such a second wiring W2 is insulated on the second semiconductor chip 8 by an insulating film 10 made of, for example, a silicon oxide film. If the second wiring W2 constituting the desired system is formed and if there is a space on the main surface of the second semiconductor chip 8, a plurality of passive elements and active elements are included in the insulating film 10 layer. Alternatively, a system having a specific function may be formed. As a result, the second semiconductor chip 8 can also have functionality. The second wiring W2 forms a desired wiring pattern in the insulating film 11. In addition, the main surface of the second semiconductor chip 8 on which the second wiring W2 is formed is surface-protected by the passivation films 12, 13 and the like.

  In the cavity 7 of the wiring substrate 1, the second semiconductor chip 8 is sealed with, for example, a resin material R2. Thereby, the mechanical strength, heat resistance, or strength against deterioration with time of the present structure in which the second semiconductor chip 8 is built in the cavity 7 can be improved. The resin material R2 is formed of a resin such as an epoxy resin, for example.

  The second wiring W2 is electrically connected to the first wiring W1 formed on the wiring board 1 by the second conductive portion E2. In the present embodiment, the second conductive portion E2 connecting the second wiring W2 and the first wiring W1 is the electrode 9 as described above. The second wiring W2 is electrically connected to a plurality of elements formed on the first semiconductor chip 2 by the third conductive portion E3. In the present embodiment, the third conductive portion E3 connecting the second wiring W2 and the first semiconductor chip 2 is composed of the electrode 9, the conductor film 5a covering the electrode 9, the bonding wire BW, and the bonding pad BP. ing.

  In the present embodiment, the electrode 9 for electrical connection with the second wiring W2 formed on the second semiconductor chip 8 is configured as follows. That is, in order from the portion directly connected to the second wiring W2, for example, a conductor portion 9a made of a metal mainly made of Al, a seed layer 9b made of Cu, for example, a conductor portion 9c made of a metal mainly made of Cu. , And a conductor portion 9d formed of a metal material.

  Here, the second conductive portion E2 and the third conductive portion E3 are for electrically connecting the second wiring W2 formed in the second semiconductor chip 8 to the first wiring W1 and the first semiconductor chip 2, respectively. It is not limited to the components or shapes shown above. For example, if the first semiconductor chip 2 is mounted on the wiring substrate 1 by a so-called flip chip method, the third conductive portion E3 does not need to be connected to the electrode 9 by the bonding wire BW. That is, in this case, the bump electrode 4 electrically connected to the plurality of elements of the first semiconductor chip 2 is brought into direct contact with the electrode 9 and is electrically connected to the second wiring W2 formed on the second semiconductor chip 8. Will do.

  Further, as will be described in detail below, the seed layer 9b is necessary when the conductor portion 9c to be a Cu electrode is formed by a plating method. This is not necessary if it is a technique or configuration for forming a pad without using a plating method.

  With the above configuration, the plurality of elements included in the first semiconductor chip 2 are the main parts of the second wiring W2, the second conductive part E2, and the wiring substrate 1 formed in the third conductive part E3 and the second semiconductor chip 8. The first wiring W1 formed on the surface S1 and the through-hole wiring E1 are sequentially connected to the bump electrode 4 formed on the back surface S2 of the wiring board 1. In this way, even when connecting to the bump electrode 4 at a location away from the plurality of elements provided in the first semiconductor chip 2, the second wiring W <b> 2 formed in the second semiconductor chip 8 with most of the wiring routed. As a result, the first wiring W1 to be formed on the wiring substrate 1 can be made as a small area of the extent of drawing. Further, as described above, the second semiconductor chip 8 having the second wiring W2 for routing is incorporated in the cavity 7 of the wiring board 1 so that the package size is not hindered. That is, by incorporating the second semiconductor chip 8 containing the desired routing wiring in the wiring substrate 1, the routing wiring can be simplified without greatly changing the shape of the wiring substrate 1.

  Further, by applying the rewiring technique after forming the second wiring W2 for routing on the second semiconductor chip 8, the adaptability of the wiring pattern of the second wiring W2 to various circuits is also improved. As a result, the system configuration required for the system-in-package SiP changes, for example, it is possible to cope with the case where the arrangement of the first semiconductor chip 2 has to be changed, and it is necessary to redesign the routing wiring of the wiring board 1 from the beginning. Is reduced. As a result, the development period and manufacturing cost of the system-in-package SiP can be reduced.

  In addition, the second wiring W2 on the second semiconductor chip 8 formed by the semiconductor wafer process has finer wiring dimensions such as line width and interval than the first wiring W1 formed on the wiring substrate 1. From this point of view, if the second wiring W2 has sufficient space, it is easy to realize equal-length wiring for stabilizing the element characteristics and reduction of wiring length that enables high-speed processing. In other words, the electric characteristics of the system-in-package SiP can be stabilized or improved in performance by the technique exemplified in the present embodiment.

  Next, a manufacturing method of the system-in-package SiP having the configuration exemplified in this embodiment will be described.

  First, a process of forming the second wiring W2 and the electrode 9 on the second semiconductor chip 8 by a normal semiconductor wafer process will be described with reference to FIGS.

  In general, the process of forming wirings or elements on a semiconductor is handled in the form of a substantially planar semiconductor thin plate called a semiconductor wafer, and after the desired elements / wirings are collectively formed, the semiconductor wafer is equivalent The semiconductor chip having the same structure is obtained. The process of forming the second wiring W2 and the electrode 9 on the second semiconductor chip 8 exemplified below is the same, and the figure is representatively illustrated as one of the processes that are collectively processed in the state of the semiconductor wafer. It is.

  First, as shown in FIG. 3, an insulating film 10 is formed on the second semiconductor chip 8 using, for example, single crystal silicon as a base material. In this embodiment, the insulating film 10 is assumed to be a silicon oxide film, for example, and is formed by, for example, a chemical vapor deposition (CVD) method or a thermal oxidation method. The insulating film 10 is intended to insulate the second wiring W2. Further, when an element having functionality is formed on the second semiconductor chip 8, the element may be formed in the insulating film 10.

  Thereafter, a second wiring W2 constituting a desired wiring pattern is formed. The wiring pattern is formed by combining a normal photolithography process, that is, a series of processes such as thin film formation, photoresist formation, exposure, development, and etching. For the second wiring W2, for example, a material made of a metal mainly composed of Al or Cu is used. Subsequently, the insulating film 11 is formed to protect the second wiring W2. As such an insulating film 11, for example, a silicon oxide film formed by a CVD method or a glass film formed by a precipitation method is used. If the second wiring W2 needs to be multilayered according to the required wiring pattern, an upper wiring layer can be formed by repeating the same process as described above.

  Subsequently, a conductor portion 9a for establishing electrical continuity from the outside is formed in the second wiring W2 by the same method. The conductor portion 9a is made of the same material as that of the second wiring W2. Subsequently, the surface is protected by the passivation film 12, and the upper portion of the conductor portion 9a is opened. The passivation film 12 is assumed to be the same material as the insulating film 11.

  Next, as shown in FIG. 4, the surface is protected by a passivation film 13 such as polyimide, and the upper portion of the conductor portion 9a is opened. Thereafter, a seed layer 9b is formed on the entire surface as a base for later forming a metal film by plating. Here, as the seed layer 9b, for example, a metal film mainly composed of Cu is deposited by sputtering or vapor deposition. Subsequently, a photoresist film 14 is formed so as to cover the seed layer 9b. Thereafter, the photoresist film 14 is patterned by photolithography so as to open the upper portion of the conductor portion 9a. In this state, by plating with the same metal material (for example, Cu) as the seed layer 9b, the conductor portion 9c is formed in the opening of the photoresist film 14 where the seed layer 9b is exposed.

  Thereafter, the photoresist film 14 and the seed layer 9b thereunder are selectively removed as shown in FIG. Thereafter, the back surface of the second semiconductor chip 8 is mechanically polished using a surface polishing apparatus called a back grinder to obtain a desired thickness. In the above process, a plurality of second semiconductor chips 8 are collectively processed in the state of a semiconductor wafer. Here, each of them is cut (so-called dicing) to form the shape of the second semiconductor chip 8. Divide into pieces.

  Through the above steps, the second wiring W2 is formed in the second semiconductor chip 8, and a part of the second conductive portion E2 and the third conductive portion E3 that can be electrically connected from the outside is formed by the semiconductor wafer process. Can do.

  Next, a process of forming a configuration in which the second semiconductor chip 8 having the second wiring W2 formed in the above process is built in the wiring board 1 will be described with reference to FIGS.

  First, as shown in FIG. 6, the second semiconductor chip 8 is placed inside the cavity 7 in the wiring substrate 1 having the core materials 1 a and 1 b. Here, the surface of the second semiconductor chip 8 on which the second wiring W <b> 2 is not formed is fixed to the core material 1 b that is the bottom of the cavity 7 with, for example, the paste 3. Thereafter, the resin material R <b> 2 is filled into the cavity 7, and the second semiconductor chip 8 is sealed inside the cavity 7. At this time, the conductor portion 9c made of Cu formed so that the second wiring W2 can communicate with the outside is exposed. Subsequently, the main surface S1 and the back surface S2 of the wiring board 1 are covered with the prepreg 1c. Thereafter, a conductor portion 9d made of a metal material is formed so as to be electrically connected to each conductor portion 9c formed by the semiconductor wafer process described above.

  Subsequently, on the main surface S1 of the wiring substrate 1, a first wiring W1 made of a metal mainly composed of Cu or the like is formed. In particular, in the present embodiment, the first wiring W1 is formed so that the conductor portion 9d conducting to the second wiring W2 and at least one through-hole wiring E1 are conducted. Thereafter, the first main surface S1 and the second main surface S2 of the wiring board 1 are covered with the solder resist 1d. At this time, electrodes that need to be electrically connected to the first semiconductor chip 2 to be mounted on the first main surface S1 of the wiring board 1 later (in this embodiment, in particular, part or all of the electrodes 5 and the conductor film 5a) are provided. In order to expose and prevent deterioration, the surface is plated with, for example, gold (Au). A BGA land 6 is formed on the second main surface S2 of the wiring board.

  Next, as shown in FIG. 7, the first semiconductor chip 2 having a plurality of elements for constituting a desired system in the system-in-package SiP is pasted on the first main surface S1 of the wiring substrate 1. Fix with Agent 3 or the like. In the present embodiment, the first semiconductor chip 2 is composed of two types of semiconductor chips 2a and 2b. However, this is not limited to three or more types in order to constitute a desired system. Also good. Thereafter, a plurality of bonding pads BP (FIG. 1 shows only one bonding pad BP for simplification) and a wiring board 1 are connected to a plurality of elements formed on the first semiconductor chip 2. A plurality of conductor films 5a exposed on the main surface S1 (FIG. 1 shows only one conductor film 5a for simplification) and a plurality of bonding wires BW (FIG. 1 shows simplification). Therefore, the first semiconductor chip 2 is mounted on the wiring board 1 by connecting with each other by only one bonding wire BW. Thereafter, the mounted first semiconductor chip 2 is sealed on the first main surface S1 of the wiring board 1 by, for example, a resin material R1. Finally, bump electrodes 4 are formed so as to be electrically connected to the BGA lands 6 formed on the back surface S2 of the wiring board 1, and individual cutouts are performed to complete a system-in-package SiP.

  The system-in-package SiP exemplified in the present embodiment in which the second semiconductor chip 8 having the second wiring W2 formed by using the semiconductor wafer process is built in the wiring substrate 1 through the above-described steps. Can be formed. That is, in the semiconductor wafer process, a dense pattern can be formed with higher accuracy than the substrate wiring technique, and the second semiconductor chip 8 having the second wiring W2 for routing formed by applying this pattern is used. . This avoids multilayering of the substrate and introduction of relay chips when the routing wiring is formed on the wiring substrate 1, and the second semiconductor chip 8 for routing wiring is built in the wiring substrate 1. -Increase in size of in-package SiP can be prevented. As a result, downsizing can be realized in a high-performance system-in-package SiP that requires complicated interchip wiring.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the cavity 7 is provided in the wiring board 1 and the second semiconductor chip 8 having the second wiring W2 is placed therein, so that the second semiconductor chip 8 is built in the wiring board 1. I am letting. The purpose is to prevent an increase in the size of the package due to the addition of the second semiconductor chip 8 for wiring. From this point of view, for example, two types of substrates are bonded together to form a wiring substrate. By embedding the second semiconductor chip 8 for wiring between the substrates, the second semiconductor chip 8 is consequently formed. It is good also as a structure incorporated in a wiring board.

  In the above embodiment, the second wiring W2 is formed on the second semiconductor chip 8 by a so-called semiconductor wafer process. However, the same effect can be obtained even if this is formed by a so-called rewiring process.

  In the above-described embodiment, the configuration in which the second wiring W2 formed in the second semiconductor chip 8 is made conductive by forming the conductor portions as the conductive portions E2 and E3 has been described. A similar effect can be obtained by adopting a configuration in which the chip 8 is a so-called flip chip system and is electrically connected to the first semiconductor chip 2 and the like mounted on the wiring substrate 1.

  In addition, the first semiconductor chip 2 constituting the desired system is a stack of a plurality of semiconductor chips 2a and 2b having a specific function, and these are mounted on the wiring board 1 in a flat manner. It may be.

  Further, the cavity 7 for incorporating the second semiconductor chip 8 having the second wiring W2 for routing in the wiring substrate 1 may not be the center of the wiring substrate 1.

  In the above embodiment, the wiring substrate 1 has a two-layer structure including the first wiring W1 formed on the main surface (first main surface) S1 and the wiring formed on the back surface (second main surface) S2. Although described, the present invention is not limited to this. A wiring board having a multilayer wiring structure in which wiring layers and prepregs are alternately laminated on the main surface side of the core material 1a and the back electrode side of the core material 1b may be used.

  The present invention can be applied to the semiconductor industry required for information processing in multifunction products such as mobile devices, car navigation systems, and microcomputers.

It is a top view of the semiconductor device which is one embodiment of the present invention. It is sectional drawing of the xx line of the semiconductor device of FIG. FIG. 2 is an essential part cross sectional view of the semiconductor device of FIG. 1 during a manufacturing step. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;

Explanation of symbols

1 Wiring board 1a, 1b Core material 1c Prepreg (insulating film)
1d Solder resist 2 First semiconductor chip 2a, 2b Semiconductor chip 3 Paste agent 4 Bump electrode (multiple electrodes)
5 Electrode 5a Conductor film 6 BGA land 7 Cavity 8 Second semiconductor chip 9 Electrode 9a, 9c, 9d Conductor part 9b Seed layer 10, 11 Insulating film 12, 13 Passivation film 14 Photoresist film BP Bonding pad BW Bonding wire E1 Through hole Wiring (first conductive part)
E2 Second conductive portion E3 Third conductive portion R1, R2 Resin material S1 Main surface (first main surface)
S2 Back side (second main surface)
SiP system-in-package W1 1st wiring W2 2nd wiring

Claims (3)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a first surface, a first element formed on the first surface, a first insulating film formed on the first surface, and a first wiring formed on the first insulating film; , A first passivation film formed on the first wiring, a first conductor portion exposed from the first passivation film and formed on the first wiring, and a first conductor opposite to the first surface. Preparing a first semiconductor chip having one back surface;
(B) after the step (a), the bottom of the cavity of the first core member having a first main surface cavity is formed and a second main surface opposite to the first main surface, Fixing the first semiconductor chip such that the first back surface of the first semiconductor chip faces the bottom of the cavity ;
(C) After the step (b), a step of sealing the first semiconductor chip with a resin material;
(D) After the step (c), forming a second wiring on the first surface of the first semiconductor chip and electrically connecting the first wiring;
(E) a step of covering the second wiring with a solder resist after the step (d);
(F) After the step (e), the second surface, the second element formed on the second surface, the bonding pad conducting to the second element, and the second surface opposite to the second surface Fixing a second semiconductor chip having two back surfaces on the solder resist;
(G) After the step (f), electrically connecting the bonding pad of the second semiconductor chip and the first conductor part via a conductive part;
(H) After the step (g), a step of sealing the second semiconductor chip with a resin;
(I) A step of forming a bump electrode on a BGA land formed on the second main surface of the first core material after the step (h). In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the second wiring is electrically connected to the bump electrode through a through-hole wiring formed in the first core material. The method of manufacturing a semiconductor device according to claim 2.
The method for manufacturing a semiconductor device, wherein the conductive portion is a bonding wire.

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