JPH05267392A - Multilayer interconnection board - Google Patents

Multilayer interconnection board

Info

Publication number
JPH05267392A
JPH05267392A JP4062288A JP6228892A JPH05267392A JP H05267392 A JPH05267392 A JP H05267392A JP 4062288 A JP4062288 A JP 4062288A JP 6228892 A JP6228892 A JP 6228892A JP H05267392 A JPH05267392 A JP H05267392A
Authority
JP
Japan
Prior art keywords
electrodes
electrode
multilayer wiring
solder ball
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4062288A
Other languages
Japanese (ja)
Other versions
JP3169254B2 (en
Inventor
Michiyoshi Kawahito
道善 川人
Akinari Kawai
亮成 河合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP06228892A priority Critical patent/JP3169254B2/en
Publication of JPH05267392A publication Critical patent/JPH05267392A/en
Application granted granted Critical
Publication of JP3169254B2 publication Critical patent/JP3169254B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To extend the break life of an electrode by preventing the occurance of a thermal stress and a thermal strain at the time of the solder flow, in a thin-film multilayer interconnection board wherein a semiconductor chip is connected through solder balls. CONSTITUTION:Electrodes for mounting a semiconductor ball are located symmetrically about the center of a thin-film multilayer interconnection board 3 or about the center line. These electrodes include effective electrodes (white circle 4) which are electrically connected to a semiconductor chip (requiring connection) and uneffective (dummy) electrodes (black circle 7). The effective electrodes include isolated electrodes 6 (having no effective electrode at adjacent lattice points). All these electrodes are symmetrized (about a point or about a line) and are electrically connected to a wiring on the rear face of the substrate via a through hole and therefore electrical isolation of the electrodes can be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップを半田ボ
−ルを介して接続する薄膜多層配線基板等の多層配線基
板に係り、特に、半田ボ−ルおよび半田ボ−ル搭載用電
極を長寿命化する多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board such as a thin film multilayer wiring board for connecting semiconductor chips via solder balls, and more particularly to a solder ball and electrodes for mounting solder balls. The present invention relates to a multilayer wiring board having a long life.

【0002】[0002]

【従来の技術】図4は、従来技術により形成した半導体
チップ1を半田ボ−ル2を介して接続した薄膜多層配線
基板3を示す。電気的に接続が必要な電極4及び電気的
な機能は必要としない電極5がある。電極5は半導体チ
ップの半田ボ−ル搭載用電極配置の標準化のために発生
する。従来は薄膜多層配線基板には、半導体チップの電
極5に対応する位置に半田ボ−ル搭載用電極を形成せ
ず、半導体チップの電極4に対応する位置にのみ半田ボ
−ル搭載用電極を形成している。なお、半田搭載用電極
の膜構成については特開平3−120853号公報に記
載されているが、電極配置について考慮されたものは知
られていない。
2. Description of the Related Art FIG. 4 shows a thin film multilayer wiring board 3 in which a semiconductor chip 1 formed by a conventional technology is connected via a solder ball 2. There are electrodes 4 that require electrical connection and electrodes 5 that do not require electrical function. The electrode 5 is generated for standardization of the solder ball mounting electrode arrangement of the semiconductor chip. Conventionally, a solder ball mounting electrode is not formed at a position corresponding to the electrode 5 of the semiconductor chip on the thin film multilayer wiring substrate, but a solder ball mounting electrode is provided only at a position corresponding to the electrode 4 of the semiconductor chip. Is forming. The film structure of the solder mounting electrode is described in Japanese Patent Laid-Open No. 3-120853, but no consideration is given to the electrode arrangement.

【0003】[0003]

【発明が解決しようとする課題】図4において、半導体
チップ1と薄膜多層配線基板3とは基板材料が相違する
ため熱膨張係数も異なる。このため、半田ボ−ル搭載の
ためのリフロ−時の加熱やその後の様々な加熱時に半田
ボ−ル及び半田ボ−ル搭載用電極に熱応力や熱歪が発生
する。しかし、上記従来技術で形成した薄膜多層配線基
板は、基板内の半田ボ−ル搭載用電極の配置に対称性を
持たせることについて何も考慮されていない。以上の状
況のため、従来技術では、薄膜多層配線基板の半田ボ−
ル搭載用電極の内、特定の電極にのみ大きな熱歪が発生
し、実使用における寿命を短くしている。
In FIG. 4, since the semiconductor chip 1 and the thin film multilayer wiring board 3 are made of different substrate materials, they have different thermal expansion coefficients. For this reason, thermal stress and thermal strain are generated in the solder ball and the solder ball mounting electrode during heating during reflow for mounting the solder ball and various heating thereafter. However, in the thin film multilayer wiring board formed by the above-mentioned conventional technique, no consideration is given to symmetry in the arrangement of the solder ball mounting electrodes in the board. Due to the above situation, in the conventional technology, the solder ball of the thin-film multilayer wiring board is
Among the mounting electrodes, a large thermal strain occurs only in a specific electrode, shortening the life in actual use.

【0004】このような問題が生じるのは、1つには、
薄膜多層配線基板の半田ボ−ル搭載用電極の配置に規則
性がなく、そのため周囲に電極の配置されてないいわゆ
る孤立電極や、チップ内でチップの中心点に対し非対称
に配置された電極が発生することにより、特定の電極に
大きな熱歪が発生することが原因になっていると考えら
れる。
One of the causes of such a problem is that
There is no regularity in the arrangement of electrodes for mounting solder balls on a thin-film multilayer wiring board, so-called isolated electrodes in which electrodes are not arranged around them, and electrodes asymmetrically arranged in the chip with respect to the center point of the chip It is considered that the cause is that a large thermal strain is generated in the specific electrode due to the generation.

【0005】従って、本発明の第1の目的は、上記従来
技術の問題点を克服し、これらの孤立電極や非対称の電
極配置のない電極配列によって、熱応力や熱歪の発生を
防止し電極の疲労破断を防いで長寿命の多層配線基板を
提供することにある。
Therefore, the first object of the present invention is to overcome the above-mentioned problems of the prior art, and prevent the generation of thermal stress and thermal strain by the electrode arrangement without these isolated electrodes or asymmetric electrode arrangement. Another object of the present invention is to provide a long-life multilayer wiring board by preventing fatigue fracture.

【0006】また、上記問題が生じるのは、2つには、
電気的に孤立する(浮いてしまう)電極が一因となって
いると考えられる。すなわち上記の電極配列を実現する
際、薄膜多層配線基板の半田ボ−ル搭載用電極の中には
電気的な機能を持つ必要がないいわゆるダミ−電極が発
生する。このダミ−電極を形成する際、薄膜多層配線基
板の最上層にのみ半田ボ−ル搭載用電極を形成し電気的
には孤立状態にすると、薄膜形成工程、例えばめっき成
膜やスパッタリング成膜時に上記の電気的には孤立状態
のダミ−電極と電気的には薄膜多層配線基板に接続して
いる正規の電極で、電位の相違が発生し、このため両電
極膜の成膜状態例えば膜厚や膜応力等が異なり、膜剥が
れや膜の接着強度が低い原因になっていると考えられ
る。
The above-mentioned problems occur in two ways:
It is considered that this is partly due to the electrically isolated (floating) electrodes. That is, when the above-mentioned electrode arrangement is realized, a so-called dummy electrode that does not need to have an electrical function is generated in the solder ball mounting electrode of the thin film multilayer wiring board. When forming the dummy electrode, if the solder ball mounting electrode is formed only on the uppermost layer of the thin film multilayer wiring board and is in an electrically isolated state, a thin film forming process, for example, plating film formation or sputtering film formation A potential difference occurs between the electrically isolated dummy electrode and the regular electrode electrically connected to the thin-film multilayer wiring board. It is considered that the cause of the peeling of the film and the low adhesive strength of the film due to the difference in the film stress and the film stress.

【0007】従って、本発明の第2の目的は、上記のよ
うな電気的に孤立する(浮く)電極が発生することのな
い多層配線基板を提供することにある。
Therefore, a second object of the present invention is to provide a multilayer wiring board in which the electrically isolated (floating) electrodes as described above are not generated.

【0008】[0008]

【課題を解決するための手段】上記第1の目的を達成す
るため、本発明は、半導体ボールを介して半導体チップ
を接続する多層配線基板において、半田ボール搭載用電
極を基板の中心に対して点対称、線対称、もしくは、点
対称かつ線対称に配置する。
In order to achieve the above first object, the present invention provides a multilayer wiring board for connecting a semiconductor chip via a semiconductor ball, wherein a solder ball mounting electrode is provided with respect to the center of the board. Arrange in point symmetry, line symmetry, or point symmetry and line symmetry.

【0009】また、これら電極のうち、半導体チップに
電気的な機能の供給もしくは取り出しを必要とする電極
に隣接する格子点に少なくとも1個以上の電極を配置す
る。上記第2の目的を達成するため、前記電極のうち、
半導体チップに電気的な機能の供給もしくは取り出しを
必要としない電極(ダミー電極)をスルーホールまたは
導体配線(薄膜多層配線)を介して基板裏側に電気的に
接続する。
Further, among these electrodes, at least one or more electrodes are arranged at a lattice point adjacent to the electrode which needs to be supplied or taken out of an electric function from the semiconductor chip. In order to achieve the second object, among the electrodes,
Electrodes (dummy electrodes) that do not require supply or extraction of electrical functions to the semiconductor chip are electrically connected to the back side of the substrate through through holes or conductor wiring (thin film multilayer wiring).

【0010】[0010]

【作用】上記構成に基づく作用を説明する。The operation based on the above configuration will be described.

【0011】本発明によれば、半田ボール搭載用電極を
対称配置すると共に隣接格子点に対し孤立する電極がな
いようにしたので、特定の電極に大きな熱歪が発生する
ことなく、半田ボールおよび半田ボール搭載用電極の破
断寿命を大幅に延長できる。また、ダミー電極をスルー
ホールまたは導体配線を介して基板裏側に接続したの
で、薄膜多層配線基板の半田ボ−ル搭載用電極を半導体
チップに電気的な機能の供給もしくは取り出しを必要と
しない電極(ダミー電極)も、それを必要とする電極
も、均一にすなわち膜特性のばらつきなく形成(成膜)
できる結果、高信頼性の電極膜を形成できる。
According to the present invention, the electrodes for mounting the solder balls are arranged symmetrically and there is no electrode isolated from the adjacent grid point, so that a large thermal strain does not occur in the specific electrode and the solder balls and The breaking life of the solder ball mounting electrode can be greatly extended. Further, since the dummy electrode is connected to the back side of the substrate through the through hole or the conductor wiring, the solder ball mounting electrode of the thin film multilayer wiring substrate is an electrode which does not require supply or extraction of an electrical function to the semiconductor chip ( Dummy electrodes) and electrodes that require them are formed uniformly (film formation) without variations in film characteristics
As a result, a highly reliable electrode film can be formed.

【0012】[0012]

【実施例】以下に、本発明の実施例を図面によって説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0013】図1は、本発明の一実施例による半田ボ−
ル搭載用電極を有する薄膜多層配線基板の平面配置図、
図2は図1の断面図である。図1及び図2において、半
田ボ−ル搭載用電極6のうち黒で塗りつぶした丸で示し
たのが半導体チップに電気的な機能の供給もしくは取り
出しを必要としない電極7(ダミー電極)であり、単な
る白丸は、半導体チップに電気的な機能の供給もしくは
取り出しが必要な電極4である。また、図1で格子点に
白丸4,6と黒丸7のいずれの電極もない、歯抜け状に
なっている部分は、半導体チップ側にも対応する電極が
存在しない部分である。(これに対し、ダミー電極7の
部分は、半導体チップ側にも対応するダミー電極が存在
する部分である)。
FIG. 1 shows a solder ball according to an embodiment of the present invention.
Layout plan of thin film multilayer wiring board having electrodes for mounting
FIG. 2 is a sectional view of FIG. In FIGS. 1 and 2, among the solder ball mounting electrodes 6, the circles filled with black are the electrodes 7 (dummy electrodes) that do not require the supply or extraction of electrical functions to the semiconductor chip. The simple white circles are the electrodes 4 for which the semiconductor chip needs to be supplied or taken out with an electrical function. Further, in FIG. 1, the part with no teeth, which does not have any of the white circles 4, 6 and the black circle 7 at the lattice points, is the part where no corresponding electrode exists on the semiconductor chip side. (On the other hand, the portion of the dummy electrode 7 is a portion where the corresponding dummy electrode exists also on the semiconductor chip side).

【0014】電極4のみを見れば、その中にいくつかの
孤立する電極6(周囲に1つも隣接する電極がないも
の)がある。この電極6の隣接する格子点に電極7を配
置し見かけ上孤立化を避けるようにした。また、薄膜多
層配線基板3内の全体的な配置は基板3の中心点Pに対
し点対称になるように配置した。
Looking only at the electrode 4, there are several isolated electrodes 6 (without any adjacent electrodes around). The electrode 7 is arranged at the adjacent lattice point of the electrode 6 so as to apparently avoid isolation. Further, the entire arrangement in the thin-film multilayer wiring board 3 is arranged so as to be point-symmetric with respect to the center point P of the board 3.

【0015】また断面図で示すごとく、電極4、電極6
は当然であるが、電極7も含む全ての電極は、薄膜多層
配線内のスル−ホ−ルや配線膜により基板の裏面に電気
的な導通をとった。
Further, as shown in the sectional view, the electrodes 4 and 6 are provided.
As a matter of course, all the electrodes including the electrode 7 were electrically connected to the back surface of the substrate by the through holes and the wiring film in the thin film multilayer wiring.

【0016】半田ボ−ル搭載用電極4,6,7等の膜構
成は図3のごとく構成される。図3は、図1〜2の薄膜
多層基板3の作製法を説明するため図2の一部を拡大し
た詳細断面図である。図2では単純化されているが、図
3のものが多層化されて図2のものができており、図2
の電極4,7ないしスルーホールの上部が図3に10〜
13として示されている。図3で、薄膜内装配線8のア
ルミや銅膜上のポリイミド系の有機層間絶縁膜もしくは
酸化珪素等の無機層間絶縁膜9に形成したスル−ホ−ル
に、接着層10として絶縁膜と接着性の良好なクロム膜
等およびその上層に半田拡散防止層11として銅や銅と
ニッケルの合金がスッパッタリング等により成膜され、
その後通常のフォトエッチングでパタ−ニングされる。
この上に半田との濡れ層13として金等がめっき法で形
成される。この時銅や銅とニッケルの合金と金等の間に
もう一層半田拡散防止層12としてニッケル等をめっき
で形成する場合がある。このメッキの際に、電気的に孤
立した電極があると、上記のような電位の相違が発生
し、膜剥がれが起るものである。
The film structure of the electrodes 4, 6, 7 etc. for mounting the solder balls is constructed as shown in FIG. FIG. 3 is a detailed cross-sectional view in which a part of FIG. 2 is enlarged for explaining the method of manufacturing the thin film multilayer substrate 3 of FIGS. Although it is simplified in FIG. 2, the one in FIG. 3 is multi-layered to form the one in FIG.
The upper part of the electrodes 4 and 7 of FIG.
It is shown as 13. In FIG. 3, a through hole formed on the polyimide-based organic interlayer insulating film on the aluminum or copper film of the thin film internal wiring 8 or the inorganic interlayer insulating film 9 such as silicon oxide is bonded to the insulating film as the adhesive layer 10. Formed of copper or an alloy of copper and nickel as a solder diffusion preventing layer 11 by sputtering or the like on a chromium film or the like having good properties,
After that, patterning is performed by normal photo etching.
Gold or the like is formed thereon as a wetting layer 13 with solder by a plating method. At this time, nickel or the like may be formed as a further layer between the copper and the alloy of copper and nickel and the gold or the like as the solder diffusion preventing layer 12 by plating. If there is an electrically isolated electrode during this plating, the above-mentioned potential difference occurs and film peeling occurs.

【0017】図1、図2及び図3に示した電極では、上
記クロム膜、銅や銅とニッケルの合金のスッパッタリン
グ成膜、ニッケル膜、金膜のめっき成膜における膜特性
のばらつきは発生せず、半田ボ−ルを搭載した時にも膜
剥がれ等は一切発生しなかった。
In the electrodes shown in FIGS. 1, 2 and 3, there are variations in film characteristics in the above chromium film, spattering film formation of copper or an alloy of copper and nickel, and nickel film formation and gold film formation. It did not occur, and no film peeling occurred even when the solder ball was mounted.

【0018】上記実施例では、点対称に電極を配置して
いるが、前後または左右に線対称に配置し、もしくは点
対称かつ線対称に配置しても同様に目的を達成できる。
In the above embodiment, the electrodes are arranged symmetrically with respect to the points, but the objects can be similarly achieved by arranging the electrodes symmetrically with respect to the front and rear or the left and right, or symmetrically with respect to the points and the line.

【0019】本実施例によれば、薄膜多層配線基板製作
用のフォトマスクの変更だけで容易に実施できる特徴が
ある。
According to this embodiment, there is a feature that it can be easily carried out only by changing a photomask for manufacturing a thin film multilayer wiring board.

【0020】[0020]

【発明の効果】以上説明したように、本発明によれば、
多層配線基板の半田ボール搭載用電極を対称配置すると
共に孤立電極がないようにしたので、熱歪の発生を防止
して寿命を大幅に改善できる効果がある。
As described above, according to the present invention,
Since the electrodes for mounting the solder balls of the multilayer wiring board are symmetrically arranged and there is no isolated electrode, there is an effect that the occurrence of thermal strain can be prevented and the life can be greatly improved.

【0021】また、ダミー電極をスルーホールや薄膜多
層配線を介して基板裏側に電気的に接続したので、電気
的に浮いた電極がなくなり、膜剥がれ等を防止すること
ができる効果がある。
Further, since the dummy electrode is electrically connected to the back side of the substrate through the through hole or the thin film multi-layer wiring, the electrically floating electrode is eliminated, and the film peeling can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の半田ボール搭載用電極を有す
る薄膜多層配線基板の平面配置図である。
FIG. 1 is a plan layout view of a thin film multilayer wiring board having solder ball mounting electrodes according to an embodiment of the present invention.

【図2】図1の断面を示す図である。FIG. 2 is a diagram showing a cross section of FIG.

【図3】半田ボール搭載用電極の膜構成を示す図であ
る。
FIG. 3 is a diagram showing a film configuration of a solder ball mounting electrode.

【図4】従来の技術により半導体チップを半田ポールを
介して接続した薄膜多層配線基板を示す図である。
FIG. 4 is a diagram showing a thin-film multilayer wiring board in which semiconductor chips are connected via solder poles by a conventional technique.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 半田ボ−ル 3 薄膜多層配線基板 4 半田ボ−ル搭載用電極 5 半田ボ−ル搭載用電極 6 半田ボ−ル搭載用電極(孤立電極) 7 半田ボ−ル搭載用電極(ダミ−電極) 8 薄膜内装配線 9 層間絶縁膜 10 接着層 11 半田拡散防止層 12半田拡散防止めっき層 13 半田ぬれ層 1 Semiconductor Chip 2 Solder Ball 3 Thin Film Multilayer Wiring Board 4 Solder Ball Mounting Electrode 5 Solder Ball Mounting Electrode 6 Solder Ball Mounting Electrode (Isolated Electrode) 7 Solder Ball Mounting Electrode ( Dummy electrode) 8 Thin film internal wiring 9 Interlayer insulating film 10 Adhesive layer 11 Solder diffusion prevention layer 12 Solder diffusion prevention plating layer 13 Solder wetting layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半田ボ−ルを介して半導体チップを接続
する多層配線基板において、半田ボ−ル搭載用電極を基
板の中心に対し点対称、もしくは線対称、もしくは点対
称かつ線対称に配置した多層配線基板。
1. In a multilayer wiring board for connecting a semiconductor chip via a solder ball, electrodes for mounting a solder ball are arranged in point symmetry, line symmetry, or point symmetry and line symmetry with respect to the center of the board. Multilayer wiring board.
【請求項2】 前記半田ボ−ル搭載用電極のうち、半導
体チップに電気的な機能の供給もしくは取り出しを必要
としない電極を、スル−ホ−ルまたは導体配線を介して
基板裏側に電気的に接続したことを特徴とする請求項1
記載の多層配線基板。
2. Among the electrodes for mounting the solder ball, an electrode which does not require supply or extraction of an electric function to a semiconductor chip is electrically connected to the back side of the substrate through a through hole or a conductor wiring. The device is connected to
The multilayer wiring board described.
【請求項3】 前記半田ボ−ル搭載用電極のうち、半導
体チップに電気的な機能の供給もしくは取り出しを必要
とする電極に隣接する格子点に少なくとも1個以上の電
極を配置したことを特徴とする請求項1または2のいず
れか1記載の多層配線基板。
3. At least one electrode is arranged at a grid point adjacent to an electrode of the solder ball mounting electrode that needs to be supplied or taken out of an electrical function from a semiconductor chip. The multilayer wiring board according to claim 1 or 2.
JP06228892A 1992-03-18 1992-03-18 Multilayer wiring board Expired - Fee Related JP3169254B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06228892A JP3169254B2 (en) 1992-03-18 1992-03-18 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06228892A JP3169254B2 (en) 1992-03-18 1992-03-18 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH05267392A true JPH05267392A (en) 1993-10-15
JP3169254B2 JP3169254B2 (en) 2001-05-21

Family

ID=13195787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06228892A Expired - Fee Related JP3169254B2 (en) 1992-03-18 1992-03-18 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3169254B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7019221B1 (en) 1998-11-27 2006-03-28 Nec Corporation Printed wiring board
JP2007294706A (en) * 2006-04-26 2007-11-08 Nec Electronics Corp Semiconductor device and method of manufacturing the same
JP2008078238A (en) * 2006-09-19 2008-04-03 Nec Corp Structure and method for mounting electronic component
JP2019079835A (en) * 2017-10-20 2019-05-23 日本特殊陶業株式会社 Ceramic substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7019221B1 (en) 1998-11-27 2006-03-28 Nec Corporation Printed wiring board
JP2007294706A (en) * 2006-04-26 2007-11-08 Nec Electronics Corp Semiconductor device and method of manufacturing the same
US8030201B2 (en) 2006-04-26 2011-10-04 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2008078238A (en) * 2006-09-19 2008-04-03 Nec Corp Structure and method for mounting electronic component
JP2019079835A (en) * 2017-10-20 2019-05-23 日本特殊陶業株式会社 Ceramic substrate

Also Published As

Publication number Publication date
JP3169254B2 (en) 2001-05-21

Similar Documents

Publication Publication Date Title
JP2916326B2 (en) Pad structure of semiconductor device
US20030232492A1 (en) Semiconductor device package and method of making the same
JP2004022730A (en) Semiconductor device and its producing process
JP2001127243A (en) Laminated semiconductor device
WO2005114728A1 (en) Semiconductor device, wiring board and manufacturing method thereof
JPH10163319A (en) Manufacture of semiconductor insulated circuit device
JP2000058583A (en) Semiconductor device
JP3648585B2 (en) Semiconductor device and manufacturing method thereof
JP5755102B2 (en) Semiconductor light emitting device
JPH0799265A (en) Multilayered interconnection substrate and manufacture thereof
JP3169254B2 (en) Multilayer wiring board
JPH07193166A (en) Semiconductor device with solder bump and manufacture thereof
JP3442738B2 (en) Semiconductor device
TW200843063A (en) Structure of semiconductor chip and package structure having semiconductor chip embedded therein
JP2001068602A (en) Semiconductor device
JP3869220B2 (en) Semiconductor device
JP2760360B2 (en) Solder bump and its manufacturing method
JPH08172273A (en) Ceramic wiring board and its mounting structure
JPH02106956A (en) Semiconductor device and manufacture thereof
JPH05183007A (en) Pad structure for semiconductor substrate
JPH02170434A (en) Semiconductor integrated circuit device provided with bump electrode
JP3565872B2 (en) Thin film multilayer wiring board
JP4594599B2 (en) Semiconductor integrated circuit
JP2822996B2 (en) Semiconductor device
JPH07221101A (en) Formation of bump electrode on semiconductor wafer

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees